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arXiv 2023年

作者： Liu, Xiaogeng Li, Minghui Wang, Haoyu Hu, Shengshan Ye, Dengpan Jin, Hai Wu, Libing Xiao, Chaowei School of Cyber Science and Engineering Huazhong University of Science and Technology China School of Computer Science and Technology Huazhong University of Science and Technology China School of Software Engineering Huazhong University of Science and Technology China National Engineering Research Center for Big Data Technology and System China Services Computing Technology and System Lab China Hubei Key Laboratory of Distributed System Security China Hubei Engineering Research Center on Big Data Security China Cluster and Grid Computing Lab China School of Cyber Science and Engineering Wuhan University China Arizona State University United States

Deep neural networks are proven to be vulnerable to backdoor attacks. Detecting the trigger samples during the inference stage, i.e., the test-time trigger sample detection, can prevent the backdoor from being triggered. However, existing detection methods often require the defenders to have high accessibility to victim models, extra clean data, or knowledge about the appearance of backdoor triggers, limiting their practicality. In this paper, we propose the test-time corruption robustness consistency evaluation (TeCo)1, a novel test-time trigger sample detection method that only needs the hard-label outputs of the victim models without any extra information. Our journey begins with the intriguing observation that the backdoor-infected models have similar performance across different image corruptions for the clean images, but perform discrepantly for the trigger samples. Based on this phenomenon, we design TeCo to evaluate test-time robustness consistency by calculating the deviation of severity that leads to predictions' transition across different corruptions. Extensive experiments demonstrate that compared with state-of-the-art defenses, which even require either certain information about the trigger types or accessibility of clean data, TeCo outperforms them on different backdoor attacks, datasets, and model architectures, enjoying a higher AUROC by 10% and 5 times of stability. Copyright © 2023, The Authors. All rights reserved.

关键词： Crime

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Downstream-agnostic Adversarial Examples

arXiv

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arXiv 2023年

作者： Zhou, Ziqi Hu, Shengshan Zhao, Ruizhi Wang, Qian Zhang, Leo Yu Hou, Junhui Jin, Hai School of Cyber Science and Engineering Huazhong University of Science and Technology China School of Computer Science and Technology Huazhong University of Science and Technology China School of Cyber Science and Engineering Wuhan University China School of Information and Communication Technology Griffith University Australia Department of Computer Science City University of Hong Kong Hong Kong National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Hubei Key Laboratory of Distributed System Security China Hubei Engineering Research Center on Big Data Security China Cluster and Grid Computing Lab

Self-supervised learning usually uses a large amount of unlabeled data to pre-train an encoder which can be used as a general-purpose feature extractor, such that downstream users only need to perform fine-tuning operations to enjoy the benefit of "large model". Despite this promising prospect, the security of pre-trained encoder has not been thoroughly investigated yet, especially when the pre-trained encoder is publicly available for commercial use. In this paper, we propose AdvEncoder, the first framework for generating downstream-agnostic universal adversarial examples based on the pre-trained encoder. AdvEncoder aims to construct a universal adversarial perturbation or patch for a set of natural images that can fool all the downstream tasks inheriting the victim pre-trained encoder. Unlike traditional adversarial example works, the pre-trained encoder only outputs feature vectors rather than classification labels. Therefore, we first exploit the high frequency component information of the image to guide the generation of adversarial examples. Then we design a generative attack framework to construct adversarial perturbations/patches by learning the distribution of the attack surrogate dataset to improve their attack success rates and transferability. Our results show that an attacker can successfully attack downstream tasks without knowing either the pre-training dataset or the downstream dataset. We also tailor four defenses for pre-trained encoders, the results of which further prove the attack ability of AdvEncoder. Our codes are available at: https://github. com/CGCL-codes/AdvEncoder. Copyright © 2023, The Authors. All rights reserved.

关键词： Machine learning

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Securing Sdn/Nfv-Enabled Campus Networks with Software-Defined Perimeter-Based Zero-Trust Architecture

SSRN

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SSRN 2023年

作者： Ruambo, Francis A. Zou, Deqing Lopes, Ivandro O. Yuan, Bin School of Cyber Science and Engineering Huazhong University of Science and Technology Wuhan430074 China Hubei Key Laboratory of Distributed System Security Wuhan China Hubei Engineering Research Center on Big Data Security Wuhan China National Engineering Research Center for Big Data Technology and System Wuhan China Services Computing Technology and System Lab Wuhan China Cluster and Grid Computing Lab Wuhan China Mbeya university of Science and Technology Mbeya131 Tanzania United Republic of Nucleo Operacional para a Sociedade de Informacao Cape Verde Songshan Laboratory Zhengzhou China

Network softwarization is a breakthrough in designing modern networks and providing numerous new network operations and services. This change is exemplified by Software Defined Networks (SDN) and Network Function Virtualization (NFV). As a result, the combination of SDN and NFV (SDN/NFV) frameworks and individual SDN and NFV frameworks have gained substantial traction in network security over the past decade, significantly supporting on-demand protection measures. However, the inherent security shortcomings of SDN, NFV, and SDN/NFV frameworks provide the fundamental issue in implementing security procedures via network softwarization. To solve this issue, we present a Software-Defined Perimeter (SDP)-powered Zero-Trust Architecture (ZTA) to improve security in the SDN/NFV-enabled campus network holistically. In addition to this, we also propose a threat model and quantitatively assess the suggested approach's performance and security. Furthermore, we highlight potential zero-trust network security function implementations in SDN/NFV-enabled infrastructure to increase protection for endpoint devices, network resources, and flows for detecting threats and responding effectively with minimal latency and overhead. © 2023, The Authors. All rights reserved.

关键词： Access control

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Sparse online relative similarity learning

arXiv

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arXiv 2021年

作者： Yao, Dezhong Zhao, Peilin Yu, Chen Jin, Hai Li, Bin Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan430074 China Data Analytics Department Institute for Infocomm Research A*STAR 138632 Singapore Economics and Management School Wuhan University Wuhan430072 China

For many data mining and machine learning tasks, the quality of a similarity measure is the key for their performance. To automatically find a good similarity measure from datasets, metric learning and similarity learning are proposed and studied extensively. Metric learning will learn a Mahalanobis distance based on positive semi-definite (PSD) matrix, to measure the distances between objectives, while similarity learning aims to directly learn a similarity function without PSD constraint so that it is more attractive. Most of the existing similarity learning algorithms are online similarity learning method, since online learning is more scalable than offline learning. However, most existing online similarity learning algorithms learn a full matrix with d2 parameters, where d is the dimension of the instances. This is clearly inefficient for high dimensional tasks due to its high memory and computational complexity. To solve this issue, we introduce several Sparse Online Relative Similarity (SORS) learning algorithms, which learn a sparse model during the learning process, so that the memory and computational cost can be significantly reduced. We theoretically analyze the proposed algorithms, and evaluate them on some real-world high dimensional datasets. Encouraging empirical results demonstrate the advantages of our approach in terms of efficiency and efficacy. Copyright © 2021, The Authors. All rights reserved.

关键词： Learning algorithms

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Clairvoyance: Intelligent route planning for electric buses based on urban big data

arXiv

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arXiv 2021年

作者： Lu, Xiangyong Ota, Kaoru Dong, Mianxiong Yu, Chen Jin, Hai Graduate School of Information Sciences Tohoku University Sendai Japan Serviecs Computing Technology and System Lab Big Data Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan430074 China Department of Information and Electronic Engineering Muroran Institute of Technology Hokkaido Muroran Japan

Nowadays many cities around the world have introduced electric buses to optimize urban traffic and reduce the local carbon emissions. In order to cut the carbon emissions and maximize the utility of electric buses, it is important to choose suitable routes for them. Traditionally, route selection is on the basis of dedicated surveys, which are costly in time and labor. In this paper, we mainly focus attention on planning electric bus routes intelligently, depending on the unique needs of each region throughout the city. We propose Clairvoyance, a route planning system that leverages a deep neural network and a multilayer perceptron to predict the future people’s trips and the future transportation carbon emission in the whole city, respectively. Given the future information of people’s trips and transportation carbon emission, we utilize a greedy mechanism to recommend bus routes for electric buses that will depart in an ideal state. Furthermore, representative features of the two neural networks are extracted from the heterogeneous urban datasets. We evaluate our approach through extensive experiments on the real-world data sources in Zhuhai, China. The results show that our designed neural network-based algorithms are consistently superior to the typical baselines. Additionally, the recommended routes for electric buses are helpful in reducing the peak value of carbon emissions and making full use of electric buses in the city. Copyright © 2021, The Authors. All rights reserved.

关键词： Multilayer neural networks

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LCCG: A Locality-Centric Hardware Accelerator for High Throughput of Concurrent Graph Processing

LCCG: A Locality-Centric Hardware Accelerator for High Throu...

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Supercomputing Conference

作者： Jin Zhao Yu Zhang Xiaofei Liao Liaang He Binzsheng He Haikun Liu Hai Jin Huazhong University of Science and Technology China National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China University of Warwick United Kingdom National University of Singapore Singapore

ISBN: (数字)9781450384421

ISBN: (纸本)9781665483902

In modern data centers, massive concurrent graph processing jobs are being processed on large graphs. However, existing hardware/-software solutions suffer from irregular graph traversal and intense resource contention. In this paper, we propose LCCG, a Locality-entric programmable accelerator that augments the many-core processor for achieving higher throughput of Concurrent Graph processing jobs. Specifically, we develop a novel topology-aware execution approach into the accelerator design to regularize the graph traversals for multiple jobs on-the-fly according to the graph topology, which is able to fully consolidate the graph data accesses from concurrent jobs. By reusing the same graph data among more jobs and coalescing the accesses of the vertices' states for these jobs, LCCG can improve the core utilization. We conduct extensive experiments on a simulated 64-core processor. The results show that LCCG improves the throughput of the cutting-edge software system by 11.3~23.9 times with only 0.5% additional area cost. More-over, LCCG gains the speedups of 4.7~10.3, 5.5~13.2, and 3.8~8.4 times over state-of-the-art hardware graph processing accelerators (namely, HATS, Minnow, and PHI, respectively).

关键词： Data centers Costs High performance computing Throughput Software systems Topology Hardware acceleration

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Hardware-Based Address-Centric Acceleration of Key-Value Store

Hardware-Based Address-Centric Acceleration of Key-Value Sto...

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IEEE Symposium on High-Performance Computer Architecture

作者： Chencheng Ye Yuanchao Xu Xipeng Shen Xiaofei Liao Hai Jin Yan Solihin National Engineering Research Center for Big Data Technology and System/Services Computing Technology and System Lab/Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China North Carolina State University Raleigh North Carolina USA Computer Science University of Central Florida Florida USA

Efficiently retrieving data is essential for key-value store applications. A major part of the retrieving time is on data addressing, that is, finding the location of the value in memory that corresponds to a key. This paper introduces an address-centric approach to speed up the addressing by creating a shortcut for the translation of a key to the physical address of the value. The new technique is materialized with a novel in-memory table, STLT, a virtual-physical address buffer, and two new instructions. It creates a fast path for data addressing and meanwhile opens up opportunities for the use of simpler and faster hash tables to strike a better tradeoff between hashing conflicts and hashing overhead. Together, the new technique brings up to 1.4× speedups on key-value store application Redis and up to 13× speedups on some widely used indexing data structures, consistently outperforming prior solutions significantly.

关键词： Production Data structures Acceleration Indexing

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Superpage-Friendly Page Table Design for Hybrid Memory Systems 6th

Superpage-Friendly Page Table Design for Hybrid Memory Syste...

引用

6th International Conference of Pioneering Computer Scientists, Engineers and Educators, ICPCSEE 2020

作者： Wang, Xiaoyuan Liu, Haikun Liao, Xiaofei Jin, Hai National Engineering Research Center for Big Data Technology and System Huazhong University of Science and Technology Wuhan430074 China Service Computing Technology and System Lab Huazhong University of Science and Technology Wuhan430074 China Cluster and Grid Computing Lab Huazhong University of Science and Technology Wuhan430074 China School of Computer Science and Technology Huazhong University of Science and Technology Wuhan430074 China

ISBN: (纸本)9789811579806

Page migration has long been adopted in hybrid memory systems comprising dynamic random access memory (DRAM) and non-volatile memories (NVMs), to improve the system performance and energy efficiency. However, page migration introduces some side effects, such as more translation lookaside buffer (TLB) misses, breaking memory contiguity, and extra memory accesses due to page table updating. In this paper, we propose superpage-friendly page table called SuperPT to reduce the performance overhead of serving TLB misses. By leveraging a virtual hashed page table and a hybrid DRAM allocator, SuperPT performs address translations in a flexible and efficient way while still remaining the contiguity within the migrated pages. © 2020, Springer Nature Singapore Pte Ltd.

关键词： Energy efficiency

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A Heterogeneous PIM Hardware-Software Co-Design for Energy-Efficient Graph Processing

A Heterogeneous PIM Hardware-Software Co-Design for Energy-E...

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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： Yu Huang Long Zheng Pengcheng Yao Jieshan Zhao Xiaofei Liao Hai Jin Jingling Xue National Engineering Research Center for Big Data Technology and System/Service Computing Technology and System Lab/Cluster and Grid Computing Lab Huazhong University of Science and Technology China UNSW Sydney Australia

ISBN: (数字)9781728168760

ISBN: (纸本)9781728168777

Processing-In-Memory (PIM) is an emerging technology that addresses the memory bottleneck of graph processing. In general, analog memristor-based PIM promises high parallelism provided that the underlying matrix-structured crossbar can be fully utilized while digital CMOS-based PIM has a faster single-edge execution but its parallelism can be low. In this paper, we observe that there is no absolute winner between these two representative PIM technologies for graph applications, which often exhibit irregular workloads. To reap the best of both worlds, we introduce a new heterogeneous PIM hardware, called Hetraph, to facilitate energy-efficient graph processing. Hetraph incorporates memristor-based analog computation units (for high-parallelism computing) and CMOS-based digital computation cores (for efficient computing) on the same logic layer of a 3D die-stacked memory device. To maximize the hardware utilization, our software design offers a hardware heterogeneity-aware execution model and a workload offloading mechanism. For performance speedups, such a hardware-software co-design outperforms the state-of-the-art by 7.54 ×(CPU), 1.56 ×(GPU), 4.13× (memristor-based PIM) and 3.05× (CMOS-based PIM), on average. For energy savings, Hetraph reduces the energy consumption by 57.58× (CPU), 19.93× (GPU), 14.02 ×(memristor-based PIM) and 10.48 ×(CMOS-based PIM), on average.

关键词： Hardware Computer architecture Parallel processing Three-dimensional displays Computational modeling Graphics processing units Memristors

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Spara: An Energy-Efficient ReRAM-Based Accelerator for Sparse Graph Analytics Applications

Spara: An Energy-Efficient ReRAM-Based Accelerator for Spars...

引用

International Symposium on Parallel and Distributed Processing (IPDPS)

作者： Long Zheng Jieshan Zhao Yu Huang Qinggang Wang Zhen Zeng Jingling Xue Xiaofei Liao Hai Jin National Engineering Research Center for Big Data Technology and System/Service Computing Technology and System Lab/Cluster and Grid Computing Lab Huazhong University of Science and Technology China UNSW Sydney Australia

ISBN: (数字)9781728168760

ISBN: (纸本)9781728168777

Resistive random access memory (ReRAM) addresses the high memory bandwidth requirement challenge of graph analytics by integrating the computing logic in the memory. Due to the matrix-structured crossbar architecture, existing ReRAM-based accelerators, when handling real-world graphs that often have the skewed degree distribution, suffer from the severe sparsity problem arising from zero fillings and activation nondeterminism, incurring substantial ineffectual *** this paper, we observe that the sparsity sources lie in the consecutive mapping of source and destination vertex index onto the wordline and bitline of a crossbar. Although exhaustive graph reordering improves the sparsity-induced inefficiency, its totally-random (source and destination) vertex mapping leads to expensive overheads. This work exploits the insight in a mid-point vertex mapping with the random wordlines and consecutive bitlines. A cost-effective preprocessing is proposed to exploit the insight by rapidly exploring the crossbar-fit vertex reorderings but ignores the sparsity arising from activation dynamics. We present a novel ReRAM-based graph analytics accelerator, named Spara, which can maximize the workload density of crossbars dynamically by using a tightly-coupled bank parallel architecture further proposed. Results on real-world and synthesized graphs show that Spara outperforms GraphR and GraphSAR by 8.21 × and 5.01 × in terms of performance, and by 8.97 × and 5.68× in terms of energy savings (on average), while incurring a reasonable (

关键词： Indexes Electrodes Random access memory Parallel architectures Resistance Memory management

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