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作者： Xu, Hui Ding, Xiaofeng Jin, Hai Yu, Qing National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China

Although cloud computing saves the cost of enterprises and individuals to manage data in various applications on public cloud servers, it also causes the problem of the leakage of critical personal information and sensitive data. Therefore, the issues about data privacy of the published personal information have become a challenging problem. Most of the existing methods focus on cryptography-based techniques by encrypting the sensitive data before publishing. However, these techniques are either too computation expensive or only some authorized users can get access to the encrypted cloud data. The consequence is that the search response time is not satisfactory and the sharing extent of the cloud data is becoming limited. Motivated by this, we propose a perturbation-based method to preserve the privacy of data in cloud. To accelerate the query processing without privacy breaches, a high-efficiency multi-dimensional index is built for answering range counting queries under differential privacy, which embeds privacy-preserving R-tree index in Content Addressable Network. Experimental results demonstrate that our methods not only protect data privacy in different degree, but also accelerate the query speed efficiently. Compared with the existing method Quad-opt, our method provides about 20% better data utility under the same differential privacy principles. © 2019 John Wiley & Sons, Ltd.

关键词： Sensitive data

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FDGLib: A Communication Library for Efficient Large-Scale Graph Processing in FPGA-Accelerated Data Centers

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Journal of Computer Science & technology 2021年第5期36卷 1051-1070页

作者： Yu-Wei Wu Qing-Gang Wang Long Zheng Xiao-Fei Liao Hai Jin Wen-Bin Jiang Ran Zheng Kan Hu National Engineering Research Center for Big Data Technology and System School of Computer Science and Technology Huazhong University of Science and TechnologyWuhan 430074China Services Computing Technology and System Laboratory School of Computer Science and Technology Huazhong University of Science and TechnologyWuhan 430074China Cluster and Grid Computing Laboratory School of Computer Science and TechnologyHuazhong University of Science and TechnologyWuhan 430074China

With the rapid growth of real-world graphs,the size of which can easily exceed the on-chip(board)storage capacity of an accelerator,processing large-scale graphs on a single Field Programmable Gate Array(FPGA)becomes *** multi-FPGA acceleration is of great necessity and *** cloud providers(e.g.,Amazon,Microsoft,and Baidu)now expose FPGAs to users in their data centers,providing opportunities to accelerate large-scale graph *** this paper,we present a communication library,called FDGLib,which can easily scale out any existing single FPGA-based graph accelerator to a distributed version in a data center,with minimal hardware engineering *** provides six APIs that can be easily used and integrated into any FPGA-based graph accelerator with only a few lines of code *** the torus-based FPGA interconnection in data centers,FDGLib also improves communication efficiency using simple yet effective torus-friendly graph partition and placement *** interface FDGLib into AccuGraph,a state-of-the-art graph *** results on a 32-node Microsoft Catapult-like data center show that the distributed AccuGraph can be 2.32x and 4.77x faster than a state-of-the-art distributed FPGA-based graph accelerator ForeGraph and a distributed CPU-based graph system Gemini,with better scalability.

关键词： data center accelerator graph processing distributed architecture communication optimization

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FaaSTube: Optimizing GPU-oriented Data Transfer for Serverless computing

arXiv

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arXiv 2024年

作者： Wu, Hao Deng, Junxiao Yu, Minchen Yu, Yue Liu, Yaochen Fan, Hao Wu, Song Wang, Wei National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology China Hong Kong University of Science and Technology Hong Kong The Chinese University of Hong Kong Shenzhen China

Serverless computing has gained significant traction for machine learning inference applications, which are often deployed as serverless workflows consisting of multiple CPU and GPU functions with data dependency. However, existing data-passing solutions for serverless computing primarily reply on host memory for fast data transfer, mandating substantial data movement and resulting in salient I/O overhead. In this paper, we present FaaSTube, a GPU-efficient data passing system for serverless inference. FaaSTube manages intermediate data within a GPU memory pool to facilitate direct data exchange between GPU functions. It enables fine-grained bandwidth sharing over PCIe and NVLink, minimizing data-passing latency for both host-to-GPU and GPU-to-GPU while providing performance isolation between functions. Additionally, FaaSTube implements an elastic GPU memory pool that dynamically scales to accommodate varying data-passing demands. Evaluations on real-world applications show that FaaSTube reduces end-to-end latency by up to 90% and achieves up to 12x higher throughput compared to the state-of-the-art. Copyright © 2024, The Authors. All rights reserved.

关键词： Computer graphics equipment

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No Free Lunch Theorem for Privacy-Preserving LLM Inference

arXiv

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arXiv 2024年

作者： Zhang, Xiaojin Fei, Yulin Kang, Yan Chen, Wei Fan, Lixin Jin, Hai Yang, Qiang Huazhong University of Science and Technology China WeBank China Hong Kong University of Science and Technology China National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan430074 China

Individuals and businesses have been significantly benefited by Large Language Models (LLMs) including PaLM, Gemini and ChatGPT in various ways. For example, LLMs enhance productivity, reduce costs, and enable us to focus on more valuable tasks. Furthermore, LLMs possess the capacity to sift through extensive datasets, uncover underlying patterns, and furnish critical insights that propel the frontiers of technology and science. However, LLMs also pose privacy concerns. Users’ interactions with LLMs may expose their sensitive personal or company information. A lack of robust privacy safeguards and legal frameworks could permit the unwarranted intrusion or improper handling of individual data, thereby risking infringements of privacy and the theft of personal identities. To ensure privacy, it is essential to minimize the dependency between shared prompts and private information. Various randomization approaches have been proposed to protect prompts’ privacy, but they may incur utility loss compared to unprotected LLMs prompting. Therefore, it is essential to evaluate the balance between the risk of privacy leakage and loss of utility when conducting effective protection mechanisms. The current study develops a framework for inferring privacy-protected Large Language Models (LLMs) and lays down a solid theoretical basis for examining the interplay between privacy preservation and utility. The core insight is encapsulated within a theorem that is called as the NFL (abbreviation of the word No-Free-Lunch) Theorem. Copyright © 2024, The Authors. All rights reserved.

关键词： Computational linguistics

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A Data-Centric Accelerator for High-Performance Hypergraph Processing 22

A Data-Centric Accelerator for High-Performance Hypergraph P...

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Proceedings of the 55th Annual IEEE/ACM International Symposium on Microarchitecture

作者： Qinggang Wang Long Zheng Ao Hu Yu Huang Pengcheng Yao Chuangyi Gui Xiaofei Liao Hai Jin Jingling Xue National Engineering Research Center for Big Data Technology and System/Services Computing Technology and System Lab/Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China and Zhejiang Lab Hangzhou China National Engineering Research Center for Big Data Technology and System/Services Computing Technology and System Lab/Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China School of Computer Science and Engineering University of New South Wales Sydney NSW Australia

ISBN: (纸本)9781665462723

Hypergraph processing has emerged as a powerful approach for analyzing complex multilateral relationships among multiple entities. Past research on building hypergraph systems suggests that changing the scheduling order of bipartite edge tasks can improve the overlap-induced data locality in hypergraph processing. However, due to the complex intertwined connections between vertices and hyperedges, it is almost impossible to find a locality-optimal scheduling order. Thus, these task-centric hypergraph systems often suffer from substantial off-chip *** this paper, we first propose a novel data-centric Load-Trigger-Reduce (LTR) execution model to exploit fully the locality in hypergraph processing. Unlike a task-centric model that loads the required data along with a task, our LTR model invokes tasks as per the data used. Specifically, once the hypergraph data is loaded into the on-chip memory, all of its relevant computation tasks will be triggered simultaneously to output intermediate results, which are finally reduced to update the final results. Our LTR model enables all hypergraph data to be accessed once in each iteration. To fully exploit the LTR performance potential, we further architect an LTR-driven hypergraph accelerator, XuLin, which features with an adaptive data loading mechanism to minimize the loading cost via chunk merging at runtime. XuLin is also equipped with a priority-based differential data reduction scheme to reduce the impact of conflicting updates on performance. We have implemented XuLin both on a Xilinx Alveo U250 FPGA card and using a cycle-accurate simulator. The results show that XuLin outperforms the state-of-the-art hypergraph processing solutions Hygra and ChGraph by 20.47× and 8.77× on average, respectively.

关键词： hypergraph data-centric accelerator

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Can Large Language Models Serve as Evaluators for Code Summarization?

arXiv

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arXiv 2024年

作者： Wu, Yang Wan, Yao Chu, Zhaoyang Zhao, Wenting Liu, Ye Zhang, Hongyu Shi, Xuanhua Yu, Philip S. Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan430074 China Big Data and Social Computing Lab University of Illinois Chicago Chicago United States Salesforce Research Palo Alto United States School of Big Data and Software Engineering Chongqing University Chongqing China

Code summarization facilitates program comprehension and software maintenance by converting code snippets into natural-language descriptions. Over the years, numerous methods have been developed for this task, but a key challenge remains: effectively evaluating the quality of generated summaries. While human evaluation is effective for assessing code summary quality, it is labor-intensive and difficult to scale. Commonly used automatic metrics, such as BLEU, ROUGE-L, METEOR, and BERTScore, often fail to align closely with human judgments. In this paper, we explore the potential of Large Language Models (LLMs) for evaluating code summarization. We propose CODERPE (Role-Player for Code Summarization Evaluation), a novel method that leverages role-player prompting to assess the quality of generated summaries. Specifically, we prompt an LLM agent to play diverse roles, such as code reviewer, code author, code editor, and system analyst. Each role evaluates the quality of code summaries across key dimensions, including coherence, consistency, fluency, and relevance. We further explore the robustness of LLMs as evaluators by employing various prompting strategies, including chain-of-thought reasoning, in-context learning, and tailored rating form designs. The results demonstrate that LLMs serve as effective evaluators for code summarization methods. Notably, our LLM-based evaluator, CODERPE, achieves an 81.59% Spearman correlation with human evaluations, outperforming the existing BERTScore metric by 17.27%. © 2024, CC BY.

关键词： Software agents

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Efficient mobile code offloading in heterogeneous wireless networks

Efficient mobile code offloading in heterogeneous wireless n...

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作者： Lu, Feng Liu, Ruoxue Li, Wei Jin, Hai Zomaya, Albert Y. Services Computing Technology and System Lab Big Data Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China Center for Distributed and High Performance Computing School of Information Technologies The University of Sydney Sydney Australia

Mobile data offloading has already appeared to offer the means of addressing the challenges of limited computing capability and battery life of mobile devices. Most existing code offloading frameworks only consider migrating an application within a single network at a time and failed to fully utilize the energy efficiency mechanism of the latest CPU chips. To tackle these issues, we propose an offloading approach under both a multitasking environment and a heterogeneous network to increase energy and execution efficiency. The offloading problem was formulated as a biobjective optimization problem that aims to save energy and keep a good performance by combining mobile cloud computing with *** technology under a heterogeneous network equipped with cellular and WiFi connectivity. By varying the applications and network scenarios, the experimental results show that with offloading a single application using our proposed framework, the data-intensive application can obviously benefit when the access point density of WiFi reaches 0.0002 unit/m2. Under multiple application scenarios, our proposed framework can increase processing speed by an average of 0.3× over the single application and can save an average of 25% power over the single application. © 2019 John Wiley & Sons, Ltd.

关键词： Heterogeneous networks

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GraSU: A fast graph update library for fpga-based dynamic graph processing 21

GraSU: A fast graph update library for fpga-based dynamic gr...

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2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2021

作者： Wang, Qinggang Zheng, Long Huang, Yu Yao, Pengcheng Gui, Chuangyi Liao, Xiaofei Jin, Hai Jiang, Wenbin Mao, Fubing National Engineering Research Center for Big Data Technology and System Service Computing Technology and System Lab Cluster and Grid Computing Lab Huazhong University of Science and Technology China

ISBN: (纸本)9781450382182

Existing FPGA-based graph accelerators, typically designed for static graphs, rarely handle dynamic graphs that often involve substantial graph updates (e.g., edge/node insertion and deletion) over time. In this paper, we aim to fill this gap. The key innovation of this work is to build an FPGA-based dynamic graph accelerator easily from any off-the-shelf static graph accelerator with minimal hardware engineering efforts (rather than from scratch). We observe\em spatial similarity of dynamic graph updates in the sense that most of graph updates get involved with only a small fraction of vertices. We therefore propose an FPGA library, called GraSU, to exploit spatial similarity for fast graph updates. GraSU uses a differential data management, which retains the high-value data (that will be frequently accessed) in the specialized on-chip UltraRAM while the overwhelming majority of low-value ones reside in the off-chip memory. Thus, GraSU can transform most of off-chip communications arising in dynamic graph updates into fast on-chip memory accesses. Our experiences show that GraSU can be easily integrated into existing state-of-the-art static graph accelerators with only 11 lines of code modifications. Our implementation atop AccuGraph using a Xilinx Alveo#8482;\U250 board outperforms two state-of-the-art CPU-based dynamic graph systems, Stinger and Aspen, by an average of 34.24× and 4.42× in terms of update throughput, improving further overall efficiency by 9.80× and 3.07× on average. © 2021 ACM.

关键词： Field programmable gate arrays (FPGA)

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On the Effectiveness of Function-Level Vulnerability Detectors for Inter-Procedural Vulnerabilities 24

On the Effectiveness of Function-Level Vulnerability Detecto...

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44th ACM/IEEE International Conference on Software Engineering, ICSE 2024

作者： Li, Zhen Wang, Ning Zou, Deqing Li, Yating Zhang, Ruqian Xu, Shouhuai Zhang, Chao Jin, Hai Hubei Key Laboratory of Distributed System Security Hubei Engineering Research Center on Big Data Security Cluster and Grid Computing Lab National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Hong Kong Jin YinHu Laboratory Wuhan China School of Cyber Science and Engineering Huazhong University of Science and Technology Wuhan China University of Colorado Colorado Springs Department of Computer Science Colorado Springs Colorado United States Institute for Network Sciences and Cyberspace Tsinghua University Beijing China School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China

ISBN: (纸本)9798400702174

Software vulnerabilities are a major cyber threat and it is important to detect them. One important approach to detecting vulnerabilities is to use deep learning while treating a program function as a whole, known as function-level vulnerability detectors. However, the limitation of this approach is not understood. In this paper, we investigate its limitation in detecting one class of vulnerabilities known as inter-procedural vulnerabilities, where the to-be-patched statements and the vulnerability-triggering statements belong to different functions. For this purpose, we create the first Inter -Procedural Vulnerability Dataset (InterPVD) based on C/C++ open-source software, and we propose a tool dubbed VulTrigger for identifying vulnerability-triggering statements across functions. Experimental results show that VulTrigger can effectively identify vulnerability-triggering statements and inter-procedural vulnerabilities. Our findings include: (i) inter-procedural vulnerabilities are prevalent with an average of 2.8 inter-procedural layers;and (ii) function-level vulner-ability detectors are much less effective in detecting to-be-patched functions of inter-procedural vulnerabilities than detecting their counterparts of intra-procedural vulnerabilities. © 2024 ACM.

关键词： Open source software

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GradedDAG: An Asynchronous DAG-based BFT Consensus with Lower Latency

GradedDAG: An Asynchronous DAG-based BFT Consensus with Lowe...

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Reliable Distributed Systems

作者： Xiaohai Dai Zhaonan Zhang Jiang Xiao Jingtao Yue Xia Xie Hai Jin National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology China School of Computer Science and Technology Hainan University China

To enable parallel processing, the Directed Acyclic Graph (DAG) structure is introduced to the design of asyn-chronous Byzantine Fault Tolerant (BFT) consensus protocols, known as DAG-based BFT. Existing DAG-based BFT protocols operate in successive waves, with each wave containing three or four Reliable Broadcast (RBC) rounds to broadcast data, resulting in high latency due to the three communication steps required in each RBC. For instance, Tusk, a state-of-the-art DAG-based BFT protocol, has a good-case latency of 7 communication steps and an expected worst latency of 21 communication steps. To reduce latency, we propose GradedDAG, a new DAG-based BFT consensus protocol based on our adapted RBC called Graded RBC (GRBC) and the Consistent Broadcast (CBC), with each wave consisting of only one GRBC round and one CBC round. Through GRBC, a replica can deliver data with a grade of 1 or 2, and a non-faulty replica delivering the data with grade 2 can ensure that more than 2/3 of replicas have delivered the same data. Meanwhile, through CBC, data delivered by different non-faulty replicas must be identical. In each wave, a block in the GRBC round will be elected as the leader. If a leader block has been delivered with grade 2, it and all its ancestor blocks can be committed. GradedDAG offers a good-case latency of 4 communication steps and an expected worst latency of 7.5 communication steps, significantly lower than the state-of-the-art. Experimental results demonstrate GradedDAG's feasibility and efficiency.

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