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5th IEEE International Conference on Cloud computing and Big Data Analytics, ICCCBDA 2020

作者： Zhang, Wei Liao, Xiaofei Jin, Hai Huazhong University of Science and Technology National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Wuhan China

ISBN: (纸本)9781728160245

FPGA has been considered as a promising solution to accelerate Convolutional Neural Networks (CNNs) for its excellent performance in energy efficiency and programmability. However, prior designs are usually designed for inference only as designers can map pre-trained models to the hardware in a very efficient way. However, those approaches may not be suitable for training CNN models. In this paper, we propose FConv, in which the CPU and FPGA work together in a fine-grained manner. The FPGA accelerator in FConv uses one Winograd-based convolver, which reduces the design complexity and improves performance. We apply double-buffer for output routine to effectively overlap computation and data transfer. We also integrate multiple PEs to improve data parallelism. We propose our analytical model for prediction and use it as a guide in task scheduling. We find the upper limit of performance under the current design based on the analytical model. We evaluate our design on VGG-16 and Densnet-40 on ImageNet and CIFAR-10. We achieve 262.43 GOP/s on the VGG-16 model, which is 2.13 times of the performance compared to FFT-based implementation on the same platform. We also achieve at most 4 times+ performance improvement compared MKL with 20 threads running on 10 core Intel processors. © 2020 IEEE.

关键词： Field programmable gate arrays (FPGA)

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RGraph: Asynchronous graph processing based on asymmetry of remote direct memory access

RGraph: Asynchronous graph processing based on asymmetry of ...

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作者： Chen, Hanhua Yuan, Jie Jin, Hai Wang, Yonghui Wu, Sijie Jiang, Zhihao National Engineering Research Center for Big Data Technology and System Cluster and Grid Computing Lab Services Computing Technology and System Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China

The scale of real-world graphs is constantly growing. To deal with large-scale graphs, distributed graph processing has attracted much research efforts. Existing distributed graph processing systems are commonly built on traditional TCP/IP communication stack, which leads to network bottleneck because of low bandwidth and heavy kernel stack operations. Meanwhile, in real power-law graphs, the average number of mirror vertices after graph partitioning is very large, resulting in significant communication overhead among nodes. The emerging high-performance Remote Direct Memory Access (RDMA) network has the features of low latency, high bandwidth, and low CPU overhead, which brings new opportunities for distributed graph processing systems. Existing RDMA-assisted graph processing systems focus on synchronous execution, which imposes barriers between consecutive iterations. Synchronous execution transfers bulk data among nodes and thus only needs a small number of network transfers. However, synchronous execution is usually less efficient than asynchronous execution because of bulk synchronization. Asynchronous execution accelerates graph processing by eliminating barriers, which in turn requires to transfer a large amount of small size data. In this paper, we propose RGraph, an RDMA-assisted asynchronous distributed graph processing system. RGraph distributes edges into two parts to isolate master and mirror vertices. RGraph exploits the asymmetry of RDMA to accelerate the one-to-many communication between master and mirror vertices. We implement RGraph on top of PowerGraph and conduct comprehensive experiments with large-scale real graphs to evaluate its performance. Results show that compared to existing designs, RGraph reduces the execution time by up to 81%. © 2021 John Wiley & Sons Ltd.

关键词： Mirrors

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Towards High-Performance Graph Processing: From a Hardware/Software Co-Design Perspective

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Journal of Computer Science & technology 2024年第2期39卷 245-266页

作者：廖小飞赵文举金海姚鹏程黄禹王庆刚赵进郑龙张宇邵志远 National Engineering Research Center for Big Data Technology and System School of Computer Science and Technology Huazhong University of Science and TechnologyWuhan 430074China Services Computing Technology and System Laboratory School of Computer Science and Technology Huazhong University of Science and TechnologyWuhan 430074China Cluster and Grid Computing Laboratory School of Computer Science and TechnologyHuazhong University of Science and TechnologyWuhan 430074China Zhejiang Lab Hangzhou 311121China

Graph processing has been widely used in many scenarios,from scientific computing to artificial *** processing exhibits irregular computational parallelism and random memory accesses,unlike traditional ***,running graph processing workloads on conventional architectures(e.g.,CPUs and GPUs)often shows a significantly low compute-memory ratio with few performance benefits,which can be,in many cases,even slower than a specialized single-thread graph *** domain-specific hardware designs are essential for graph processing,it is still challenging to transform the hardware capability to performance boost without coupled software *** article presents a graph processing ecosystem from hardware to *** start by introducing a series of hardware accelerators as the foundation of this ***,the codesigned parallel graph systems and their distributed techniques are presented to support graph ***,we introduce our efforts on novel graph applications and hardware *** results show that various graph applications can be efficiently accelerated in this graph processing ecosystem.

关键词： graph processing hardware accelerator software system high performance ecosystem

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DroidAuditor: A framework for auditing covert communication on Android

DroidAuditor: A framework for auditing covert communication ...

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作者： Qiang, Weizhong Xin, Shifan Jin, Hai Sun, Guozhong Services Computing Technology and System Lab Cluster and Grid Computing Lab Big Data Technology and System Lab Huazhong University of Science and Technology Wuhan430074 China Co. Ltd. Beijing100193 China

Exploitation of covert channels in smartphone operating systems may lead to furtive data transmission between applications with different permissions, which might threaten users' privacy. Restricting the access to shared system resources can effectively prevent the exploitation of known covert channels. However, it inevitably limits the normal usage of those resources. In this paper, we propose a general method that detects covert channel attack at runtime without impacting the accessibility of shared resources in the system. The main idea of the method is to track and audit the use of system resources known as potential covert channel variables and impose interferences on those channels to reduce their capacity once violations are detected. We implement a prototype framework, which is able to audit and interfere covert communication both in the application layer and in the native layer of Android. The experimental results demonstrate that our method can effectively reduce the data rate of user-defined covert channels while the overhead is negligible. Copyright © 2017 John Wiley & Sons, Ltd.

关键词： Android (operating system)

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High Performance DDoS Attack Detection System Based on Distribution Statistics 16th

High Performance DDoS Attack Detection System Based on Distr...

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16th IFIP WG 10.3 International Conference on Network and Parallel computing, NPC 2019

作者： Xie, Xia Li, Jinpeng Hu, Xiaoyang Jin, Hai Chen, Hanhua Ma, Xiaojing Huang, Hong National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan430074 China

ISBN: (纸本)9783030307080

Nowadays, web servers often face the threat of distributed denial of service attacks and their intrusion prevention systems cannot detect those attacks effectively. Many existing intrusion prevention systems detect attacks by the state of per-flow and current processing speed cannot fulfill the requirements of real-time detection due to the high speed traffic. In this paper, we propose a powerful system TreeSketchShield which can improve sketch data structure and detect attacks quickly. First, we discuss a novel structure TreeSketch to obtain statistics of network flow, which utilizes the stepped structure of binary tree to map the distribution and reduces the complexity of the statistic calculation. Second, we present a two-level detection scheme that could make a compromise between the detection speed and detection accuracy. Experimental results show that our method can process more than 100,000 records per second. The false alarm rate can achieve 2% to 25% performance improvement. © 2019, IFIP International Federation for Information Processing.

关键词： Binary trees

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An Efficient Data Prefetch Strategy for Deep Learning Based on Non-volatile Memory 15th

An Efficient Data Prefetch Strategy for Deep Learning Based ...

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15th International Conference on Green, Pervasive, and Cloud computing, GPC 2020

作者： Jiang, Wenbin Liu, Pai Jin, Hai Peng, Jing National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan430074 China

ISBN: (纸本)9783030642426

Deep learning (DL) systems usually utilize asynchronous prefetch to improve data reading performance. However, the efficiency of the data transfer path from hard disk to DRAM is still limited by disk performance. The emerging non-volatile memory (NVRAM) provides a novel solution for this problem, while few existing researches have considered it. We propose a novel efficient data prefetch strategy for DL based on a heterogeneous memory system combining NVRAM with DRAM. Benefitting from the large capacity and fast reading speed of NVRAM, the strategy uses an asynchronous reading method named sliding NVRAM cache (SNC) to improve the performance of the data transfer paths. A sliding window is applied to map the data from disk to NVRAM and continuously update the data, while non-ideal writing performance of NVRAM can be remitted to a large extent in this strategy. Experiments show that SNC can improve the time performance of diverse deep neural networks training by more than 30%. © 2020, Springer Nature Switzerland AG.

关键词： Dynamic random access storage

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Anole: A Lightweight and Verifiable Learned-Based Index for Time Range Query on Blockchain Systems 28th

Anole: A Lightweight and Verifiable Learned-Based Index for...

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28th International Conference on Database Systems for Advanced Applications, DASFAA 2023

作者： Chang, Jian Li, Binhong Xiao, Jiang Lin, Licheng Jin, Hai National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan430074 China

ISBN: (纸本)9783031306365

Time range query is essential to facilitate a wide range of blockchain applications such as data provenance in the supply chain. Existing blockchain systems adopt the storage-consuming tree-based index structure for better query performance, however, fail to efficiently work for most blockchain nodes with limited resources. In this paper, we propose Anole, a lightweight and verifiable time range query mechanism, to present the feasibility of building up a learned-based index to achieve high performance and low storage costs on blockchain systems. The key idea of Anole is to exploit the temporal characteristics of blockchain data distribution and design a tailored lightweight index to reduce storage costs. Moreover, it uses a digital signature to guarantee the correctness and completeness of query results by considering the learned index’s error bounds, and applies batch verification to further improve verification performance. Experimental results demonstrate that Anole improves the query performance by up to 10 × and reduces the storage overhead by 99.4 % compared with the state-of-the-art vChain+. © 2023, The Author(s), under exclusive license to Springer Nature Switzerland AG.

关键词： Blockchain

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Minimal Context-Switching Data Race Detection with Dataflow Tracking

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Journal of Computer Science & technology 2024年第1期39卷 211-226页

作者：郑龙李洋辛杰刘海峰郑然廖小飞金海 National Engineering Research Center for Big Data Technology and System School of Computer Science and Technology Huazhong University of Science and TechnologyWuhan 430074China Services Computing Technology and System Laboratory School of Computer Science and TechnologyHuazhong University of Science and TechnologyWuhan 430074China Cluster and Grid Computing Laboratory School of Computer Science and TechnologyHuazhong University of Science and TechnologyWuhan 430074China

Data race is one of the most important concurrent anomalies in multi-threaded *** con-straint-based techniques are leveraged into race detection,which is able to find all the races that can be found by any oth-er sound race ***,this constraint-based approach has serious limitations on helping programmers analyze and understand data ***,it may report a large number of false positives due to the unrecognized dataflow propa-gation of the ***,it recommends a wide range of thread context switches to schedule the reported race(in-cluding the false one)whenever this race is exposed during the constraint-solving *** ad hoc recommendation imposes too many context switches,which complicates the data race *** address these two limitations in the state-of-the-art constraint-based race detection,this paper proposes DFTracker,an improved constraint-based race detec-tor to recommend each data race with minimal thread context ***,we reduce the false positives by ana-lyzing and tracking the dataflow in the *** this means,DFTracker thus reduces the unnecessary analysis of false race *** further propose a novel algorithm to recommend an effective race schedule with minimal thread con-text switches for each data *** experimental results on the real applications demonstrate that 1)without removing any true data race,DFTracker effectively prunes false positives by 68%in comparison with the state-of-the-art constraint-based race detector;2)DFTracker recommends as low as 2.6-8.3(4.7 on average)thread context switches per data race in the real world,which is 81.6%fewer context switches per data race than the state-of-the-art constraint based race ***,DFTracker can be used as an effective tool to understand the data race for programmers.

关键词： data race satisfiability modulo theory multi-threaded program dynamic detection

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Efficient Remote Memory Paging for Disaggregated Memory Systems 1

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22nd International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 2022

作者： Wang, Tao Liu, Haikun Jin, Hai National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan430074 China

ISBN: (数字)9783031226779

ISBN: (纸本)9783031226762

Memory disaggregation has attracted increasing attention in recent years because it is a cost-efficient approach to scale memory capacity for applications in a data center. However, the latency of remote memory access is a major concern in disaggregated memory systems. This paper presents VANDI, a virtual memory paging mechanism that allows applications to use remote memory pools transparently. VANDI enables effective data caching and prefetching mechanisms to address the problem of high access latency in disaggregated memory systems. VANDI exploits a low-complexity cache replacement strategy to optimize the asynchronous staging queue so that the remote write latency can be significantly reduced. VANDI can also prefetch data in multi-granularity from a remote memory pool in an adaptive manner, and thus further improves the hit rate of the local cache to reduce the read latency of remote memory. Our extensive experiments using micro-benchmarks show that VANDI can improve the performance of typical remote paging system–Infiniswap by up to 15 × –102 ×. VANDI can also improve the performance of state-of-the-art disaggregated memory system–Valet by 1.2 × –2.7 ×. For typical machine learning workloads, VANDI can achieve 20% to 80% performance improvement compared with the state-of-the-art Valet. © 2023, Springer Nature Switzerland AG.

关键词： Paging systems

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Failure order: A missing piece in disk failure processing of data centers 21

Failure order: A missing piece in disk failure processing of...

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21st IEEE International Conference on High Performance computing and Communications, 17th IEEE International Conference on Smart City and 5th IEEE International Conference on Data Science and Systems, HPCC/SmartCity/DSS 2019

作者： Yi, Yusheng Xiao, Jiang Wu, Song Li, Huichuwu Jin, Hai National Engineering Research Center for Big Data Technology System Services Computing Technology System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan430074 China

ISBN: (纸本)9781728120584

To avoid data loss, data centers adopt disk failure prediction (DFP) technology to raise warnings ahead of actual disk failures, and process the warnings in the order they are raised, i.e., a first-in-first-out (FIFO) warning order. The FIFO-guided warning order can process warnings timely when disk failures are rare in data centers. With the growing scale of data centers, the increasing number of disk failures leads to a complex situation that multiple warnings are raised simultaneously, where the FIFO-guided warning order neither processes warnings timely, nor manages warnings properly due to lack of the priority of warnings. Thus, a real-time and finer-grained priority guidance for warning order management is an urgent need. To this end, we turn our attention to the failures since each warning corresponds to a fail event. The key insight is that the interdependence of failures, i.e., the order failure occurred, indicates the order of warning processing. With an accurate failure order, data centers can decrease the probability of data loss and the downtime of latency-sensitive applications by processing urgent warnings in advance. In this paper, we predict the failure order with a LambdaMART model, which is a state-of-the-art ranking algorithm in information retrieval. To avoid overly concerning on the correctness of high-rank warnings in information retrieval, we design a symmetric metric to evaluate the prediction evaluation of failure order. Experiment on a public dataset, provided by the Backblaze company, shows that our model outperforms the FIFO order and the order from previous DFP models. © 2019 IEEE.

关键词： Information retrieval

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