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23rd USENIX Conference on File and Storage Technologies, FAST 2025

作者： Duan, Zhuohui Feng, Hao Liu, Haikun Liao, Xiaofei Jin, Hai Li, Bangyu National Engineering Research Center for Big Data Technology and System Service Computing Technology and System Lab/Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology China

ISBN: (纸本)9781939133458

The key-value separation is renowned for its significant mitigation of the write amplification inherent in traditional LSM trees. However, KV separation potentially increases performance overhead in the management of Value region, especially for garbage collection (GC) operation that is used to reduce the redundant space occupation. In response, many efforts have been made to optimize the GC mechanism for KV separation. However, our analysis indicates that such solution based on trade-offs between CPU and I/O overheads cannot simultaneously satisfy the three requirements of KV separated systems in terms of throughput, tail latency, and space usage. This limitation hinders their real-world application. In this paper, we introduce AegonKV, a "three-birds-one-stone" solution that comprehensively enhances the throughput, tail latency, and space usage of KV separated systems. AegonKV first proposes a SmartSSD-based GC offloading mechanism to enable asynchronous GC operations without competing with LSM read/write for bandwidth or CPU. AegonKV leverages offload-friendly data structures and hardware/software execution logic to address the challenges of GC offloading. Experiments demonstrate that AegonKV achieves the largest throughput improvement of 1.28-3.3 times, a significant reduction of 37%-66% in tail latency, and 15%-85% in space overhead compared to existing KV separated systems. © 2025 FAST. All Rights Reserved.

关键词： Digital storage

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Ciphertext-Policy Attribute-Based Encryption with Short Keys

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Chinese Journal of Electronics 2025年第4期23卷 655-660页

作者： Peng Xu Yong Tang Wenbin Jiang Hai Jin Deqing Zou Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China

Ciphertext-policy attribute-based encryption (CP-ABE) allows a user with some attributes to decrypt the ciphertexts associated with these attributes. Though several CP-ABE schemes with the constant size ciphertext were proposed to reduce the communication cost, their master public and secret keys still have the size linear in the total number of attributes. These schemes are unpractical for the attribute-scalable and many-attributes scenario. A new CP-ABE scheme is proposed. Each attribute is mapped to a mathematical value by a combination method. The master public and secret keys of the proposed CP-ABE scheme have the size linear in the binary size of a hash function's range. It has the comparable performance with existing schemes in the aspects like the time costs of encryption and decryption, the expressiveness of access policy and the provable security.

关键词： Costs Encryption

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Soft-GNN:towards robust graph neural networks via self-adaptive data utilization

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Frontiers of Computer Science 2025年第4期19卷 1-12页

作者： Yao WU Hong HUANG Yu SONG Hai JIN National Engineering Research Center for Big Data Technology and System Service Computing Technology and System LabCluster and Grid Computing LabSchool of Computer Science and TechnologyHuazhong University of Science and TechnologyWuhan 430074China College of Information and Communication National University of Defense TechnologyWuhan 430019China Department of Computer Science and Operations Research Universitéde MontréalMontreal H3C 3J7Canada

Graph neural networks(GNNs)have gained traction and have been applied to various graph-based data analysis tasks due to their high ***,a major concern is their robustness,particularly when faced with graph data that has been deliberately or accidentally polluted with *** presents a challenge in learning robust GNNs under noisy *** address this issue,we propose a novel framework called Soft-GNN,which mitigates the influence of label noise by adapting the data utilized in *** approach employs a dynamic data utilization strategy that estimates adaptive weights based on prediction deviation,local deviation,and global *** better utilizing significant training samples and reducing the impact of label noise through dynamic data selection,GNNs are trained to be more *** evaluate the performance,robustness,generality,and complexity of our model on five real-world datasets,and our experimental results demonstrate the superiority of our approach over existing methods.

关键词： graph neural networks node classification label noise robustness

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RTGA: A Redundancy-free Accelerator for High-Performance Temporal Graph Neural Network Inference 24

RTGA: A Redundancy-free Accelerator for High-Performance Tem...

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61st ACM/IEEE Design Automation Conference, DAC 2024

作者： Yu, Hui Zhang, Yu Tan, Andong Lu, Chenze Zhao, Jin Liao, Xiaofei Jin, Hai Liu, Haikun National Engineering Research Center for Big Data Technology and System Service Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology China

ISBN: (纸本)9798400706011

Temporal Graph Neural Network (TGNN) has attracted much research attention because it can capture the dynamic nature of complex networks. However, existing solutions suffer from redundant computation overhead and excessive off-chip communications for TGNN inference because they often rely on redundant graph sampling and repeatedly fetching the features and vertex memory. This paper proposes a redundancy-free accelerator, RTGA, for high-performance TGNN inference. Specifically, RTGA proposes a redundancy-aware execution approach with temporal tree into a novel accelerator design to effectively eliminate unnecessary data processing for fewer redundant computations and off-chip communications and also designs a temporal-aware data caching method to improve data locality for TGNN. We have implemented and evaluated RTGA on a Xilinx Alveo U280 FPGA card. Compared with cutting-edge software solutions (i.e., TGN and TGL) and hardware solutions (i.e., BlockGNN and FlowGNN), RTGA improves the performance of TGNN inference by an average of 473.2x, 87.4x, 8.2x, and 6.9x and saves energy by 542.8x, 102.2x, 9.4x, and 8.3x, respectively. © 2024 Copyright is held by the owner/author(s). Publication rights licensed to ACM.

关键词： Spatio-temporal data

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High-Performance and Resource-Efficient Dynamic Memory Management in High-Level Synthesis 24

High-Performance and Resource-Efficient Dynamic Memory Manag...

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61st ACM/IEEE Design Automation Conference, DAC 2024

作者： Wang, Qinggang Zheng, Long An, Zhaozeng Huang, Haoqin Zhu, Haoran Huang, Yu Yao, Pengcheng Liao, Xiaofei Jin, Hai National Engineering Research Center for Big Data Technology and System Service Computing Technology and System Lab Cluster and Grid Computing Lab Huazhong University of Science and Technology Wuhan China Zhejiang Lab Hangzhou China

ISBN: (纸本)9798400706011

With the merits of high productivity and ease of use, highlevel synthesis (HLS) tools bring hope to fast FPGA-based architecture development. However, their usability and popularity are still limited due to lack of support for dynamic memory management (DMM). Though HLS-compatible DMM solutions have been proposed recently, nevertheless, based on our investigation, none of them can hit high performance (i.e., minimal memory (de-)allocation latency) and resource efficiency (i.e., managing arbitrarily sized memory with minimal FPGA resource consumption) with one stone, seriously limiting their practicality. In response, we propose HeroDMM, a high-performance and resource-efficient dynamic memory manager for HLS. Specifically, HeroDMM organizes the managed memory area with a novel cartesian-like tree (CT) structure, a key to resolving the dilemma between (de-)allocation latency and resource efficiency standing in front of prior efforts. With the CT structure, HeroDMM further devises a delicate memory management algorithm and specializes the hardware implementation for achieving ever-higher performance while ensuring resource efficiency. Results show that HeroDMM outperforms state-of-the-art HLS-compatible DMM solutions by 61.69%∼99.99% in performance improvement and 23.79%∼97.22% in resource consumption savings. © 2024 Copyright is held by the owner/author(s). Publication rights licensed to ACM.

关键词： Memory management

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LSGraph: A Locality-centric High-performance Streaming Graph Engine 24

LSGraph: A Locality-centric High-performance Streaming Graph...

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19th European Conference on Computer Systems, EuroSys 2024

作者： Qi, Hao Wu, Yiyang He, Ligang Zhang, Yu Luo, Kang Cai, Minzhi Jin, Hai Zhang, Zhan Zhao, Jin National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology China Department of Computer Science University of Warwick United Kingdom Zhejiang Lab China

ISBN: (纸本)9798400704376

Streaming graph has been broadly employed across various application domains. It involves updating edges to the graph and then performing analytics on the updated graph. However, existing solutions either suffer from poor data locality and high computation complexity for streaming graph analytics, or need high overhead to search and move graph data to ensure ordered neighbors during streaming graph update. This paper presents a novel locality-centric streaming graph engine, called LSGraph, to enable efficient both graph analytics and graph update. The main novelty of this engine is a differentiated hierarchical indexed streaming graph representation approach to achieve efficient data search and movement for graph update and also maintain data locality and ordered neighbors for efficient graph analytics simultaneously. Besides, a locality-aware streaming graph data update mechanism is also proposed to efficiently regulate the distance of data movement, minimizing the overhead of memory access during graph update. We have implemented LSGraph and conducted a systematic evaluation on both real-world and synthetic datasets. Compared with three cutting-edge streaming graph engines, i.e., Terrace, Aspen, and PaC-tree, LSGraph achieves 2.98×-81.08×, 1.46×-12.56×, and 1.26×-10.31× speedups during graph update, while obtaining 1.02×-4.28×, 1.58×-3.55×, and 1.20×-2.72× speedups during graph analytics, respectively. © 2024 Owner/Author.

关键词： Engines

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P3DC:Reducing DRAM Cache Hit Latency by Hybrid Mappings

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Journal of Computer Science & technology 2024年第6期39卷 1341-1360页

作者： Ye Chi Ren-Tong Guo Xiao-Fei Liao Hai-Kun Liu Jianhui Yue National Engineering Research Center for Big Data Technology and System Wuhan 430074China Services Computing Technology and System Laboratory Wuhan 430074China Cluster and Grid Computing Laboratory Wuhan 430074China School of Computer Science and Technology Huazhong University of Science and TechnologyWuhan 430074China School of Big Data and Internet Shenzhen Technology UniversityShenzhen 518118China Department of Computer Science Michigan Technological UniversityHoughton 49931-1295U.S.A.

Die-stacked dynamic random access memory(DRAM)caches are increasingly advocated to bridge the performance gap between the on-chip cache and the main *** fully realize their potential,it is essential to improve DRAM cache hit rate and lower its cache hit *** order to take advantage of the high hit-rate of set-association and the low hit latency of direct-mapping at the same time,we propose a partial direct-mapped die-stacked DRAM cache called *** design is motivated by a key observation,i.e.,applying a unified mapping policy to different types of blocks cannot achieve a high cache hit rate and low hit latency *** address this problem,P3DC classifies data blocks into leading blocks and following blocks,and places them at static positions and dynamic positions,respectively,in a unified set-associative *** also propose a replacement policy to balance the miss penalty and the temporal locality of different *** addition,P3DC provides a policy to mitigate cache thrashing due to block type *** results demonstrate that P3DC can reduce the cache hit latency by 20.5%while achieving a similar cache hit rate compared with typical set-associative caches.P3DC improves the instructions per cycle(IPC)by up to 66%(12%on average)compared with the state-of-the-art direct-mapped cache—BEAR,and by up to 19%(6%on average)compared with the tag-data decoupled set-associative cache—DEC-A8.

关键词： die-stacked dynamic random access memory(DRAM) cache set-associative direct-mapped hit latency

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Anole: A Lightweight and Verifiable Learned-Based Index for Time Range Query on Blockchain Systems 28th

Anole: A Lightweight and Verifiable Learned-Based Index for...

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28th International Conference on Database Systems for Advanced Applications, DASFAA 2023

作者： Chang, Jian Li, Binhong Xiao, Jiang Lin, Licheng Jin, Hai National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan430074 China

ISBN: (纸本)9783031306365

Time range query is essential to facilitate a wide range of blockchain applications such as data provenance in the supply chain. Existing blockchain systems adopt the storage-consuming tree-based index structure for better query performance, however, fail to efficiently work for most blockchain nodes with limited resources. In this paper, we propose Anole, a lightweight and verifiable time range query mechanism, to present the feasibility of building up a learned-based index to achieve high performance and low storage costs on blockchain systems. The key idea of Anole is to exploit the temporal characteristics of blockchain data distribution and design a tailored lightweight index to reduce storage costs. Moreover, it uses a digital signature to guarantee the correctness and completeness of query results by considering the learned index’s error bounds, and applies batch verification to further improve verification performance. Experimental results demonstrate that Anole improves the query performance by up to 10 × and reduces the storage overhead by 99.4 % compared with the state-of-the-art vChain+. © 2023, The Author(s), under exclusive license to Springer Nature Switzerland AG.

关键词： Blockchain

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Efficient Remote Memory Paging for Disaggregated Memory Systems 1

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22nd International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 2022

作者： Wang, Tao Liu, Haikun Jin, Hai National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan430074 China

ISBN: (数字)9783031226779

ISBN: (纸本)9783031226762

Memory disaggregation has attracted increasing attention in recent years because it is a cost-efficient approach to scale memory capacity for applications in a data center. However, the latency of remote memory access is a major concern in disaggregated memory systems. This paper presents VANDI, a virtual memory paging mechanism that allows applications to use remote memory pools transparently. VANDI enables effective data caching and prefetching mechanisms to address the problem of high access latency in disaggregated memory systems. VANDI exploits a low-complexity cache replacement strategy to optimize the asynchronous staging queue so that the remote write latency can be significantly reduced. VANDI can also prefetch data in multi-granularity from a remote memory pool in an adaptive manner, and thus further improves the hit rate of the local cache to reduce the read latency of remote memory. Our extensive experiments using micro-benchmarks show that VANDI can improve the performance of typical remote paging system–Infiniswap by up to 15 × –102 ×. VANDI can also improve the performance of state-of-the-art disaggregated memory system–Valet by 1.2 × –2.7 ×. For typical machine learning workloads, VANDI can achieve 20% to 80% performance improvement compared with the state-of-the-art Valet. © 2023, Springer Nature Switzerland AG.

关键词： Paging systems

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Fast Parallel Recovery for Transactional Stream Processing on Multicores 40

Fast Parallel Recovery for Transactional Stream Processing o...

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40th IEEE International Conference on Data Engineering, ICDE 2024

作者： Zhao, Jianjun Liu, Haikun Zhang, Shuhao Duan, Zhuohui Liao, Xiaofei Jin, Hai Zhang, Yu School of Computer Science and Technology Huazhong University of Science and Technology National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab Wuhan China School of Computer Science and Engineering Nanyang Technological University Singapore

ISBN: (纸本)9798350317152

Transactional stream processing engines (TSPEs) have gained increasing attention due to their capability of processing real-time stream applications with transactional semantics. However, TSPEs remain susceptible to system failures and power outages. Existing TSPEs mainly focus on performance improvement, but still face a significant challenge to guarantee fault tolerance while offering high-performance services. We revisit commonly-used fault tolerance approaches in stream processing and database systems, and find that these approaches do not work well on TSPEs due to complex data dependencies. In this paper, we propose a novel TSPE called MorphStreamR to achieve fast failure recovery while guaranteeing low performance overhead at runtime. The key idea of MorphStreamR is to record intermediate results of resolved dependencies at runtime, and thus eliminate data dependencies to improve task parallelism during failure recovery. MorphStreamR further mitigates the runtime overhead by selectively tracking data dependencies and incorporating workload-aware log commitment. Experimental results show that MorphStreamR can significantly reduce the recovery time by up to 3.1 x while experiencing much less performance slowdown at runtime, compared with other applicable fault tolerance approaches. © 2024 IEEE.

关键词： Fault tolerance

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