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2023 World Wide Web Conference, WWW 2023

作者： Wang, Kaibin He, Qiang Chen, Feifei Chen, Chunyang Huang, Faliang Jin, Hai Yang, Yun School of Computer Science and Technology Huazhong University of Science and Technology China Department of Computing Technologies Swinburne University of Technology Australia School of Information Technology Deakin University Australia Faculty of Information Technology Monash University Australia Guangxi Key Lab of Human-machine Interaction and Intelligent Decision Nanning Normal University China National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab Huazhong University of Science and Technology Wuhan430074 China

ISBN: (纸本)9781450394161

Mobile and Web-of-Things (WoT) devices at the network edge account for more than half of the world's web traffic, making a great data source for various machine learning (ML) applications, particularly federated learning (FL) which offers a promising solution to privacy-preserving ML feeding on these data. FL allows edge mobile and WoT devices to train a shared global ML model under the orchestration of a central parameter server. In the real world, due to resource heterogeneity, these edge devices often train different versions of models (e.g., VGG-16 and VGG-19) or different ML models (e.g., VGG and ResNet) for the same ML task (e.g., computer vision and speech recognition). Existing FL schemes have assumed that participating edge devices share a common model architecture, and thus cannot facilitate FL across edge devices with heterogeneous ML model architectures. We explored this architecture heterogeneity challenge and found that FL can and should accommodate these edge devices to improve model accuracy and accelerate model training. This paper presents our findings and FlexiFed, a novel scheme for FL across edge devices with heterogeneous model architectures, and three model aggregation strategies for accommodating architecture heterogeneity under FlexiFed. Experiments with four widely-used ML models on four public datasets demonstrate 1) the usefulness of FlexiFed;and 2) that compared with the state-of-the-art FL scheme, FlexiFed improves model accuracy by 2.6%-9.7% and accelerates model convergence by 1.24 × -4.04 ×. © 2023 ACM.

关键词： Speech recognition

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How to Select Pre-Trained Code Models for Reuse? A Learning Perspective

arXiv

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arXiv 2025年

作者： Bi, Zhangqian Wan, Yao Chu, Zhaoyang Hu, Yufei Zhang, Junyi Zhang, Hongyu Xu, Guandong Jin, Hai National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab Wuhan China School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China School of Big Data and Software Engineering Chongqing University Chongqing China School of Computer Science University of Technology Sydney Sydney Australia

Pre-training a language model and then fine-tuning it has shown to be an efficient and effective technique for a wide range of code intelligence tasks, such as code generation, code summarization, and vulnerability detection. However, pre-training language models on a large-scale code corpus is computationally expensive. Fortunately, many off-the-shelf Pre-trained Code Models (PCMs), such as CodeBERT, CodeT5, CodeGen, and Code Llama, have been released publicly. These models acquire general code understanding and generation capability during pre-training, which enhances their performance on downstream code intelligence tasks. With an increasing number of these public pre-trained models, selecting the most suitable one to reuse for a specific task is essential. In this paper, we systematically investigate the reusability of PCMs. We first explore three intuitive model selection methods that select by size, training data, or brute-force fine-tuning. Experimental results show that these straightforward techniques either perform poorly or suffer high costs. Motivated by these findings, we explore learning-based model selection strategies that utilize pre-trained models without altering their parameters. Specifically, we train proxy models to gauge the performance of pre-trained models, and measure the distribution deviation between a model's latent features and the task's labels, using their closeness as an indicator of model transferability. We conduct experiments on 100 widely-used open-source PCMs for code intelligence tasks, with sizes ranging from 42.5 million to 3 billion parameters. The results demonstrate that learning-based selection methods reduce selection time to 100 seconds, compared to 2,700 hours with brute-force fine-tuning, with less than 6% performance degradation across related tasks. © 2025, CC BY-NC-SA.

关键词： Adversarial machine learning

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The Power of Bamboo: On the Post-Compromise Security for Searchable Symmetric Encryption 30

The Power of Bamboo: On the Post-Compromise Security for Sea...

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30th Annual Network and Distributed System Security Symposium, NDSS 2023

作者： Chen, Tianyang Xu, Peng Picek, Stjepan Luo, Bo Susilo, Willy Jin, Hai Liang, Kaitai National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab China Hubei Key Laboratory of Distributed System Security Hubei Engineering Research Center on Big Data Security School of Cyber Science and Engineering China Cluster and Grid Computing Lab School of Computer Science and Technology China Huazhong University of Science and Technology Wuhan430074 China Digital Security Group Radboud University Nijmegen Netherlands Department of EECS Institute of Information Sciences The University of Kansas LawrenceKS United States Institute of Cybersecurity and Cryptology School of Computing and Information Technology University of Wollongong WollongongNSW2522 Australia Faculty of Electrical Engineering Mathematics and Computer Science Delft University of Technology Delft2628 CD Netherlands

ISBN: (纸本)1891562835

Dynamic searchable symmetric encryption (DSSE) enables users to delegate the keyword search over dynamically updated encrypted databases to an honest-but-curious server without losing keyword privacy. This paper studies a new and practical security risk to DSSE, namely, secret key compromise (e.g., a user’s secret key is leaked or stolen), which threatens all the security guarantees offered by existing DSSE schemes. To address this open problem, we introduce the notion of searchable encryption with key-update (SEKU) that provides users with the option of non-interactive key updates. We further define the notion of post-compromise secure with respect to leakage functions to study whether DSSE schemes can still provide data security after the client’s secret key is compromised. We demonstrate that post-compromise security is achievable with a proposed protocol called "Bamboo". Interestingly, the leakage functions of Bamboo satisfy the requirements for both forward and backward security. We conduct a performance evaluation of Bamboo using a real-world dataset and compare its runtime efficiency with the existing forward-and-backward secure DSSE schemes. The result shows that Bamboo provides strong security with better or comparable performance. © 2023 30th Annual Network and Distributed System Security Symposium, NDSS 2023. All Rights Reserved.

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RAHP: A Redundancy-aware Accelerator for High-performance Hypergraph Neural Network

RAHP: A Redundancy-aware Accelerator for High-performance Hy...

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IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： Hui Yu Yu Zhang Ligang He Yingqi Zhao Xintao Li Ruida Xin Jin Zhao Xiaofei Liao Haikun Liu Bingsheng He Hai Jin National Engineering Research Center for Big Data Technology and System Service Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China Department of Computer Science University of Warwick United Kingdom National University of Singapore Singapore

ISBN: (数字)9798350350579

ISBN: (纸本)9798350350586

Hypergraph Neural Network (HyperGNN) has emerged as a potent methodology for dissecting intricate multilateral connections among various entities. Current software/hardware solutions leverage a sequential execution model that relies on hyperedge and vertex indices for conducting standard matrix operations for HyperGNN inference. Yet, they are impeded by the dual challenges of redundant computation and irregular memory access overheads. This is primarily due to the frequent and repetitive access and updating of a number of feature vectors corresponding to the same hyperedges and vertices. To address these challenges, we propose the first redundancy-aware accelerator, RAHP, which enables high performance execution of HyperGNN inference. Specifically, we present a redundancy-aware asynchronous execution approach into the accelerator design for HyperGNN to reduce redundant computations and off-chip memory accesses. To unveil opportunities for data reuse and unlock the parallelism that existing HyperGNN solutions fail to capture, it prioritizes vertices with the highest degree as roots, prefetching other vertices along the hypergraph structure to capture the common vertices among multiple hyperedges, and synchronizing the computations of hyperedges and vertices in real-time. By such means, this facilitates the concurrent processing of relevant hyperedge and vertex computations of the common vertices along the hypergraph topology, resulting in smaller redundant computations overhead. Furthermore, by efficiently caching intermediate results of the common vertices, it curtails memory traffic and off-chip communications. To fully harness the performance potential of our proposed approach in the accelerator, RAHP incorporates a topology-driven data loading mechanism to minimize off-chip memory accesses on the fly. It is also endowed with an adaptive data synchronization scheme to mitigate the effects of conflicting updates of both hyperedges and vertices. Moreover, RAHP emplo

关键词： Computational modeling Neural networks Memory management Loading Energy conservation Vectors Software Topology Synchronization Standards

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A Scalable, Efficient, and Robust Dynamic Memory Management Library for HLS-based FPGAs

A Scalable, Efficient, and Robust Dynamic Memory Management ...

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IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： Qinggang Wang Long Zheng Zhaozeng An Shuyi Xiong Runze Wang Yu Huang Pengcheng Yao Xiaofei Liao Hai Jin Jingling Xue National Engineering Research Center for Big Data Technology and System/Services Computing Technology and System Lab/Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China Zhejiang Lab Hangzhou China School of Computer Science and Engineering University of New South Wales Sydney NSW Australia

ISBN: (数字)9798350350579

ISBN: (纸本)9798350350586

Nowadays, high-level synthesis (HLS) has gained prominence for FPGA-based architecture prototyping, enhancing productivity significantly. Despite this advancement, HLS tools are impeded by a critical drawback: they lack support for dynamic memory management (DMM), leading to static mem-ory allocation and suboptimal use of memory resources. In response, numerous efforts have been made to develop DMM solutions compatible with HLS. However, our analysis indicates that existing solutions fail to concurrently meet the desired trifecta of scalability (efficient management of memory of any size), efficiency (minimal latency in memory (de-)allocation), and robustness (low allocation failure rates). This limitation hampers their applicability in real-world scenarios. In this paper, we introduce GraDMM, a “three-birds-one- stone” solution that comprehensively enhances the scalability, efficiency, and robustness of DMM. The key insight is to formulate memory (de-)allocation as graph analytics and lever-age sophisticated FPGA-based graph processing techniques. To achieve scalability, GraDMM specializes a simplified pipeline that significantly suppresses resource utilization expansion caused by managed memory scaling. This is crucial for managing arbitrarily sized memory on resource-limited FPGA platforms. For efficiency, GraDMM implements a data-centric concurrent traversal scheme and a shortcut-assisted fast traversal policy to accelerate (de-)allocation-guided graph traversal, reducing mem-ory (de-)allocation latency. To enhance robustness, GraDMM incorporates an adaptive memory defragmenter that defragments managed memory to minimize fragmentation-induced allocation failures. GraDMM is encapsulated as a library, providing high- level interfaces for users and ensuring synthesizability with Vi- vado HLS. Experimental results demonstrate that GraDMM out-performs three state-of-the-art HLS-compatible DMM solutions by significant margins: 56.71 %-85.59% in resource consumption sa

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AFaVS: Accurate Yet Fast Version Switching for Graph Processing Systems

AFaVS: Accurate Yet Fast Version Switching for Graph Process...

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International Conference on Data Engineering

作者： Long Zheng Xiangyu Ye Haifeng Liu Qinggang Wang Yu Huang Chuangyi Gui Pengcheng Yao Xiaofei Liao Hai Jin Jingling Xue National Engineering Research Center for Big Data Technology and System/Services Computing Technology and System Lab/Cluster and Grid Computing Laboratory Huazhong University of Science and Technology Wuhan China Zhejiang Lab Hangzhou China School of Computer Science and Engineering UNSW Sydney Australia

Multi-version graph processing has been widely used to solve many real-world problems. The process of the multi-version graph processing typically includes: (1) a history graph version switching at a specific time and (2) graph processing on this history graph. Existing multi-version graph systems assume ideally that every request for a particular graph version at a particular time will have a corresponding snapshot available. However, in most cases, this is not true. Then existing solutions usually have to settle with an "approximating" version as a substitute, leading to unexpected results for the underlying graph algorithm and thus reducing the practicality of a multi-version graph system for many application scenarios *** this paper, we observe that only a few graph updates have a great impact on the final results. We therefore present AFaVS, a novel multi-version graph system that can improve accuracy effectively in both time- and memory-efficient manners. The cornerstone of AFaVS lies in a novel concept "value" that characterizes the importance of graph updates. AFaVS proposes differential management of updates based on their values and achieves higher accuracy while preserving processing and memory efficiency. AFaVS is also equipped with value-guided version switching and locality-aware optimizations to boost its overall efficiency. Our results on a variety of real-world datasets show that AFaVS outperforms four state-of-the-art multi-version graph systems by 74.35%~95.72% in terms of accuracy improvement and 57.03%~90.44% in terms of memory reduction while introducing less than 2.96% extra computing time. We have deployed AFaVS in a disaster recovery system on the production cluster of Alibaba, achieving 78.8%~90.1% fewer error rates than advanced systems at a comparable efficiency.

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Layered Structure Aware Dependent Microservice Placement Toward Cost Efficient Edge Clouds

Layered Structure Aware Dependent Microservice Placement Tow...

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IEEE Annual Joint Conference: INFOCOM, IEEE computer and Communications Societies

作者： Deze Zeng Hongmin Geng Lin Gu Zhexiong Li School of Computer Science China University of Geosciences Wuhan China National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China

Although the containers are featured by light-weightness, it is still resource-consuming to pull and startup a large container image, especially in relatively resource-constrained edge cloud. Fortunately, Docker, as the most widely used container, provides a unique layered architecture that allows the same layer to be shared between microservices so as to lower the deployment cost. Meanwhile, it is highly desirable to deploy dependent microservices of an application together to lower the operation cost. Therefore, the balancing of microservice deployment cost and the operation cost should be considered comprehensively to achieve minimal overall cost of an on-demand application. In this paper, we first formulate this problem into a Quadratic Integer Programming form (QIP) and prove it as a NP-hard problem. We further propose a Randomized Rounding-based Microservice Deployment and Layer Pulling (RR-MDLP) algorithm with low computation complexity and guaranteed approximation ratio. Through extensive experiments, we verify the high efficiency of our algorithm by the fact that it significantly outperforms existing state-of-the-art microservice deployment strategies.

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Efficient FPGA-based graph processing with hybrid pull-push computational model

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Frontiers of computer Science 2020年第4期14卷 13-28页

作者： Chengbo YANG Long ZHENG Chuangyi GUI Hai JIN National Engineering Research Center for Big Data Technology and System/Service Computing Technology and System Lab/Cluster and Grid Computing Lab School of Computer Science and TechnologyHuazhong University of Science and TechnologyWuhan430074China

Hybrid pull-push computational model can provide compelling results over either of single one for processing real-world *** and pipeline parallelism of FPGAs make it potential to process different stages of graph ***,considering the limited on-chip resources and streamline pipeline computation,the efficiency of hybrid model on FPGAs often suffers due to well-known random access feature of graph *** this paper,we present a hybrid graph processing system on FPGAs,which can achieve the best of both *** approach on FPGAs is unique and novel as ***,we propose to use edge block(consisting of edges with the same destination vertex set),which allows to sequentially access edges at block granularity for locality while still preserving the *** to the independence of blocks in the sense that all edges in an inactive block are associated with inactive vertices,this also enables to skip invalid blocks for reducing redundant ***,we consider a large number of vertices and their associated edge-blocks to maintain a predictable execution *** also present to switch models in advance with few stalls using their state *** evaluation on a wide variety of graph algorithms for many real-world graphs shows that our approach achieves up to 3.69x speedup over state-of-the-art FPGA-based graph processing systems.

关键词： graph processing efficiency computational model FPGAs

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A Data-Centric Accelerator for High-Performance Hypergraph Processing 22

A Data-Centric Accelerator for High-Performance Hypergraph P...

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Proceedings of the 55th Annual IEEE/ACM International Symposium on Microarchitecture

作者： Qinggang Wang Long Zheng Ao Hu Yu Huang Pengcheng Yao Chuangyi Gui Xiaofei Liao Hai Jin Jingling Xue National Engineering Research Center for Big Data Technology and System/Services Computing Technology and System Lab/Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China and Zhejiang Lab Hangzhou China National Engineering Research Center for Big Data Technology and System/Services Computing Technology and System Lab/Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China School of Computer Science and Engineering University of New South Wales Sydney NSW Australia

ISBN: (纸本)9781665462723

Hypergraph processing has emerged as a powerful approach for analyzing complex multilateral relationships among multiple entities. Past research on building hypergraph systems suggests that changing the scheduling order of bipartite edge tasks can improve the overlap-induced data locality in hypergraph processing. However, due to the complex intertwined connections between vertices and hyperedges, it is almost impossible to find a locality-optimal scheduling order. Thus, these task-centric hypergraph systems often suffer from substantial off-chip *** this paper, we first propose a novel data-centric Load-Trigger-Reduce (LTR) execution model to exploit fully the locality in hypergraph processing. Unlike a task-centric model that loads the required data along with a task, our LTR model invokes tasks as per the data used. Specifically, once the hypergraph data is loaded into the on-chip memory, all of its relevant computation tasks will be triggered simultaneously to output intermediate results, which are finally reduced to update the final results. Our LTR model enables all hypergraph data to be accessed once in each iteration. To fully exploit the LTR performance potential, we further architect an LTR-driven hypergraph accelerator, XuLin, which features with an adaptive data loading mechanism to minimize the loading cost via chunk merging at runtime. XuLin is also equipped with a priority-based differential data reduction scheme to reduce the impact of conflicting updates on performance. We have implemented XuLin both on a Xilinx Alveo U250 FPGA card and using a cycle-accurate simulator. The results show that XuLin outperforms the state-of-the-art hypergraph processing solutions Hygra and ChGraph by 20.47× and 8.77× on average, respectively.

关键词： hypergraph data-centric accelerator

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Risk Modeling and Traceability of Boundary Attacks on Internet of Power Systems Based on Complex Networks 9

Risk Modeling and Traceability of Boundary Attacks on Intern...

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9th IEEE International Conference on Data Science in Cyberspace, DSC 2024

作者： Li, Xin Qu, Zhaoyang Yu, Tong Xie, Ming Yu, Fu Ding, Wei Northeast Electric Power University School of Electrical Engineering Jilin132012 China People's Bank of China Qinghai Provincial Branch Xining810000 China China Southern Power Grid Guangxi Power Grid Co. Ltd. Research Institute Nanning530023 China China Guizhou Power Grid Co. Ltd. Bijie Power Supply Bureau Bijie551700 China Qilu University of Technology Shandong Academy of Sciences Key Laboratory of Computing Power Network and Information Security Ministry of Education Shandong Computer Science Center National Supercomputer Center in Jinan Jinan250014 China Shandong Fundamental Research Center for Computer Science Shandong Provincial Key Laboratory of Computer Networks Jinan250014 China

ISBN: (纸本)9798350391367

With the increasing intelligence of power IoT terminal devices, the massive volume of data transmission, and the widespread adoption of shared services, traditional terminal boundary security mechanisms are unable to keep up with the rapid development of network technologies and applications. Additionally, they fail to trace and source network attacks, leading to frequent organized and purposeful malicious attack incidents. To address these issues, this paper proposes a research method for risk modeling and traceability of boundary attacks on power IoT terminals based on complex networks. First, based on the node information of power IoT terminal devices and complex network theory, a terminal boundary attack network (TBAN) is established. Next, using indicators related to complex network theory, such as degree, in-degree, and out-degree, the terminal boundary attack network is analyzed. Furthermore, a staged TBAN is proposed to analyze the attack risks at different times. Then, combining causal theory, a method for tracing and sourcing terminal boundary attacks based on a causal Bayesian network is proposed to identify and trace malicious attacks. Finally, validation and testing analysis are conducted using the actual deployment of power IoT terminal devices. The proposed analysis method transforms the spatial characteristics of the power IoT terminal boundary into a temporally sequential TBAN, which not only visually reflects attack risks but also reveals the temporal relationships of terminal boundary attacks between lines. © 2024 IEEE.

关键词： Internet of things

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