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IEEE International Conference on computer-Aided Design

作者： Haichuan Hu Zichen Xu Yuhao Wang Fangming Liu Services Computing Technology and System Lab Cluster and Grid Computing Lab National Engineering Research Center for Big Data Technology and System School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China School of Mathematics and Computer Science Nanchang University Nanchang China Pengcheng Laboratory Shenzhen China

The natural bijection between a proposed circuit design and its graph representation shall allow any graph optimization algorithm deploying into many-core systems efficiently. However, this process suffers from the exponentially growing overhead and heavy memory footprint with the signal propagation. To conquer the unique challenge, we systematically study the simulation with millions of gates, and identify that the processing complexity could grow exponentially from the signal inputs, the skewness of the computational graph stays. Thus, we present ZhouBi, a fast and scalable gate-level simulation framework to fully exploit the parallelism from many-core systems. ZhouBi contributes in threefolds, (I) a graph representation that colors gate-level netlists and identifies skew partitions based on the graph skewness; (II) A set of heuristic algorithms that picks opportunistic and conservative algorithms to accelerate the simulation; (III) A system facility that supports selective mapping between simulation and many-core, providing a tradeoff between the risk of concurrent simulation fail and performance gain. We have prototyped ZhouBi and evaluated it with practical baselines. ZhouBi can achieve a 27.6× performance gain, as compared to the state-of-the-practice Veriwell without compromising any correctness. Our framework supports large graphs enabling scale-out gate-level simulations for chip design.

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SumPA: Efficient Pattern-Centric Graph Mining with Pattern Abstraction 21

SumPA: Efficient Pattern-Centric Graph Mining with Pattern A...

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Proceedings of the 30th International Conference on Parallel Architectures and Compilation Techniques

作者： Chuangyi Gui Xiaofei Liao Long Zheng Pengcheng Yao Qinggang Wang Hai Jin National Engineering Research Center for Big Data Technology and System/Service Computing Technology and System Lab/Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China

ISBN: (纸本)9781665442787

Graph mining aims to explore interesting structural information of a graph. Pattern-centric systems typically transform a generic-purpose graph mining problem into a series of subgraph matching problems for high performance. Existing pattern-centric mining systems reduce the substantial search space towards a single pattern by exploring a highly-optimized matching order, but inherent computational redundancies of such a matching order itself still suffer severely, leading to significant performance degradation. The key innovation of this work lies in a general redundancy criterion that characterizes computational redundancies arising in not only handing a single pattern but also matching multiple patterns simultaneously. In this paper, we present SumPA, a high-performance pattern-centric graph mining system that can sufficiently remove redundant computations for any complex graph mining problems. SumPA features three key designs: (1) a pattern abstraction technique that can simplify numerous complex patterns into a few simple abstract patterns based on pattern similarity, (2) abstraction-guided pattern matching that completely eliminates (totally and partially) redundant computations during subgraph enumeration, and (3) a suite of system optimizations to maximize storage and computation efficiency. Our evaluation on a wide variety of real-world graphs shows that SumPA outperforms the two state-of-the-art systems Peregrine and GraphPi by up to 61.89× and 8.94×, respectively. For many mining problems on large graphs, Peregrine takes hours or even days while SumPA finishes in only a few minutes.

关键词： data reuse

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HiNUMA: NUMA-Aware Data Placement and Migration in Hybrid Memory Systems

HiNUMA: NUMA-Aware Data Placement and Migration in Hybrid Me...

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IEEE International Conference on computer Design: VLSI in computers and Processors, (ICCD)

作者： Zhuohui Duan Haikun Liu Xiaofei Liao Hai Jin Wenbin Jiang Yu Zhang National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab/Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China

Non-uniform memory access (NUMA) architectures feature asymmetrical memory access latencies on different CPU nodes. Hybrid memory systems composed of non-volatile memory (NVM) and DRAM further diversify memory access latencies due to the relatively large performance gap between NVM and DRAM. Traditional NUMA memory management policies fail to manage hybrid memories effectively and may even hurt application performance. In this paper, we present HiNUMA, a new NUMA abstraction for memory allocation and migration in hybrid memory systems. HiNUMA advocates NUMA topologyaware hybrid memory allocation policies for the initial data placement. HiNUMA also proposes a new NUMA balancing mechanism called HANB for memory migration at runtime. HANB considers both data access frequency and memory bandwidth utilization to reduce the cost of memory accesses in hybrid memory systems. We evaluate the performance of HiNUMA with several typical workloads. Experimental results show that HiNUMA can effectively utilize hybrid memories, and deliver much higher application performance than conventional NUMA memory management policies and other state-of-the-art work.

关键词： Nonvolatile memory Random access memory Bandwidth Memory management Resource management Task analysis Memory architecture

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Reasoning Based Workload Performance Prediction in Cloud Data Centers

Reasoning Based Workload Performance Prediction in Cloud Dat...

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IEEE International Conference on Cloud computing technology and science

作者： Adeel Aslam Hanhua Chen Jiang Xiao Hai Jin National Engineering Research Center for Big Data Technology and System Cluster and Grid Computing Lab Services Computing Technology and System Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China

Cloud computing provides utility-based and scalable services to end-users. In the past decade, the demands for resource management in cloud computing have increased substantially which lead to certain challenges such as optimal resource utilization, power consumption, and service level agreement violations. Workload performance prediction serves as an assistance to address these issues. In this paper, we propose a prediction model based on clustered Case-Based Reasoning (CBR). The proposed model determines the performance metrics for workload prior to the co-operation of autonomic computing characteristics. Thus, CBR provides optimal scheduling of resources and workload monitoring for cloud data centers. In order to validate the proposed CBR-based prediction model, we perform a series of experiments and evaluate the effectiveness in terms of precision, recall, f-measure, and mean square error rate. We generate the cases for CBR using traces from the Google cluster data center. Moreover, we also validate our proposed prediction model against Support Vector Machine (SVM) prediction scheme. Experimental results show that the proposed CBR outperforms the SVM-based approach and yields 10% improvement in terms of precision.

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Grace: An Efficient Parallel SPARQL Query System over Large-Scale RDF Data

Grace: An Efficient Parallel SPARQL Query System over Large-...

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International Conference on computer Supported Cooperative Work in Design

作者： Xiang Kang Yuying Zhao Pingpeng Yuan Hai Jin National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China

As a markup language for describing web resources, RDF is often used to represent graph data. SPARQL is a standard query language for RDF data, which is convenient in querying RDF. As RDF data grows rapidly, how to deal with complex queries over large-scale data in a reasonable time still remains many challenges. The existing RDF query systems often fail to respond within a reasonable time when dealing with complex SPARQL queries. Therefore, we propose an efficient parallel SPARQL query system and novel in three aspects. First, the proposed design provides a dynamic selectivity estimation strategy and generates an optimal query plan for parallel query processing. Second, the new design proposes a parallel processing model to maximize the parallelism of the system. Finally, chunk-based task distribution strategy is implemented to assist the parallel processing model. Based on the proposed design, we implement an efficient parallel query system (Grace). Extensive experiments on LUBM and BTC benchmarks show that Grace outperforms RDF-3X, Virtuoso, TripleBit and achieves a good performance of scalability on the number of threads.

关键词： Distribution strategy Scalability Query processing Markup languages Instruction sets Estimation Parallel processing

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Fine-grained Scheduling in FPGA-Based Convolutional Neural Networks

Fine-grained Scheduling in FPGA-Based Convolutional Neural N...

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IEEE International Conference on Cloud computing and Big Data Analysis (ICCCBDA)

作者： Wei Zhang Xiaofei Liao Hai Jin National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China

ISBN: (数字)9781728160245

ISBN: (纸本)9781728160252

FPGA has been considered as a promising solution to accelerate Convolutional Neural Networks (CNNs) for its excellent performance in energy efficiency and programmability. However, prior designs are usually designed for inference only as designers can map pre-trained models to the hardware in a very efficient way. However, those approaches may not be suitable for training CNN models. In this paper, we propose FConv, in which the CPU and FPGA work together in a fine-grained manner. The FPGA accelerator in FConv uses one Winograd-based convolver, which reduces the design complexity and improves performance. We apply double-buffer for output routine to effectively overlap computation and data transfer. We also integrate multiple PEs to improve data parallelism. We propose our analytical model for prediction and use it as a guide in task scheduling. We find the upper limit of performance under the current design based on the analytical model. We evaluate our design on VGG-16 and Densnet-40 on ImageNet and CIFAR-10. We achieve 262.43 GOP/s on the VGG-16 model, which is 2.13× of the performance compared to FFT-based implementation on the same platform. We also achieve at most 4×+ performance improvement compared MKL with 20 threads running on 10 core Intel processors.

关键词： Field programmable gate arrays Computational modeling Training Convolution Acceleration Bandwidth Task analysis

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Multi-task representation learning with multi-view graph convolutional networks

arXiv

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arXiv 2021年

作者： Huang, Hong Song, Yu Wu, Yao Shi, Jia Xie, Xia Jin, Hai National Engineering Research Center for Big Data Technology Service Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan430074 China

Link prediction and node classification are two important downstream tasks of network representation learning. Existing methods have achieved acceptable results but they perform these two tasks separately, which requires a lot of duplication of work and ignores the correlations between tasks. Besides, conventional models suffer from the identical treatment of information of multiple views, thus they fail to learn robust representation for downstream tasks. To this end, we tackle link prediction and node classification problems simultaneously via multi-task multi-view learning in this paper. We first explain the feasibility and advantages of multi-task multi-view learning for these two tasks. Then we propose a novel model named as MT-MVGCN to perform link prediction and node classification tasks simultaneously. More specifically, we design a multi-view graph convolutional network to extract abundant information of multiple views in a network, which is shared by different tasks. We further apply two attention mechanisms: view attention mechanism and task attention mechanism to make views and tasks adjust the view fusion process. Moreover, view reconstruction can be introduced as an auxiliary task to boost the performance of the proposed model. Experiments on real-world network datasets demonstrate that our model is efficient yet effective, and outperforms advanced baselines in these two tasks. © 2021, CC BY.

关键词： Data mining

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Optimal Margin Distribution Machine with Sparsity Inducing Penalty

Optimal Margin Distribution Machine with Sparsity Inducing P...

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International Conference on Big Data and Smart computing (BIGCOMP)

作者： Teng Zhang Hai Jin National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China

ISBN: (数字)9781728160344

ISBN: (纸本)9781728160351

Recently a promising research direction of statistical learning has been advocated, i.e., the optimal margin distribution learning, with the central idea of optimizing the margin distribution. As the most representative approach of this new learning paradigm, the optimal margin distribution machine (ODM) considers maximizing the margin mean and minimizing the margin variance simultaneously. The standard ODM exploits the ℓ_2-norm penalty, which gives rise to a dense decision boundary. However, in some situations, the model with parsimonious representation is more preferred, due to the redundant noisy features or limited computing resources. In this paper, we propose the sparse optimal margin distribution machine (Sparse ODM), which aims to achieve better generalization performance with moderate model size. For optimization, we extends an efficient coordinate descent method to solve the final problem since the variables are decoupled. In each iteration, we propose a modified Newton method to solve the one-variable sub-problem. Experimental results on both synthetic and real data sets show the superiority of the proposed method.

关键词： Standards Newton method Noise measurement Optimization Support vector machines Computational modeling Training

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A Locality-Aware Energy-Efficient Accelerator for Graph Mining Applications

A Locality-Aware Energy-Efficient Accelerator for Graph Mini...

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IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： Pengcheng Yao Long Zheng Zhen Zeng Yu Huang Chuangyi Gui Xiaofei Liao Hai Jin Jingling Xue National Engineering Research Center for Big Data Technology and System/Services Computing Technology and System Lab/Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China School of Computer Science and Engineering UNSW Sydney Australia

ISBN: (数字)9781728173832

ISBN: (纸本)9781728173849

Graph mining is becoming increasingly important due to the ever-increasing demands on analyzing complex structures in graphs. Existing graph accelerators typically hold most of the randomly-accessed data in an on-chip memory to avoid off-chip communications. However, graph mining exhibits substantial random accesses from not only vertex dimension but also edge dimension (with the latter being excessively more complex than the former), leading to significant degradations in terms of both performance and energy *** observe that the most random memory requests arising in graph mining come from accessing a small fraction of valuable (vertex and edge) data when handling real-world graphs. To exploit this extension locality with maximum parallelism, we architect GRAMER, the first graph mining accelerator. GRAMER contains a specialized memory hierarchy, where the valuable data (precisely identified through a cost-efficient heuristic) is permanently resident in a high-priority memory while others are maintained in a cache-like memory under a lightweight replacement policy. The specific pipelined processing units are carefully designed to maximize computational parallelism. GRAMER is also equipped with a work-stealing mechanism to reduce load imbalance. We have implemented GRAMER on a Xilinx Alveo U250 accelerator card. Compared with two state-of-the-art CPU-based graph mining systems, Fractal and RStream, running on a 14-core Intel E5-2680 v4 processor, GRAMER achieves not only considerable speedups (1.11 × ~ 129.95 ) but also significant energy savings (5.79 × ~ 678.34×)

关键词： Memory management Parallel processing Feature extraction Energy efficiency Fractals System-on-chip Data mining

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CPSAA: Accelerating Sparse Attention using Crossbar-based Processing-In-Memory Architecture

arXiv

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arXiv 2022年

作者： Li, Huize Jin, Hai Zheng, Long Liao, Xiaofei Huang, Yu Liu, Cong Xu, Jiahong Duan, Zhuohui Chen, Dan Gui, Chuangyi National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China

The attention-based neural network attracts great interest due to its excellent accuracy enhancement. However, the attention mechanism requires huge computational efforts to process unnecessary calculations, significantly limiting the system’s performance. To reduce the unnecessary calculations, researchers propose sparse attention to convert some dense-dense matrices multiplication (DDMM) operations to sampled dense-dense matrix multiplication (SDDMM) and sparse matrix multiplication (SpMM) operations. However, current sparse attention solutions introduce massive off-chip random memory access since the sparse attention matrix is generally unstructured. We propose CPSAA, a novel crossbar-based processing-in-memory (PIM)-featured sparse attention accelerator to eliminate off-chip data transmissions. First, we present a novel attention calculation mode to balance the crossbar writing and crossbar processing latency. Second, we design a novel PIM-based sparsity pruning architecture to eliminate the pruning phase’s off-chip data transfers. Finally, we present novel crossbar-based SDDMM and SpMM methods to process unstructured sparse attention matrices by coupling two types of crossbar arrays. Experimental results show that CPSAA has an average of 89.6×, 32.2×, 17.8×, 3.39×, and 3.84× performance improvement and 755.6×, 55.3×, 21.3×, 5.7×, and 4.9× energy-saving when compare with GPU, FPGA, SANGER, ReBERT, and ReTransformer. Copyright © 2022, The Authors. All rights reserved.

关键词： Memory architecture

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