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Design, Automation and Test in Europe Conference and Exhibition

作者： Zhan Zhang Jianhui Yue Xiaofei Liao Hai Jin National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computing Science and Technology Huazhong University of Science and Technology Wuhan China Computer Science Department Michigan Technological University Houghton Michigan

ISBN: (数字)9783981926347

ISBN: (纸本)9781728144689

The persistent memory (PM) requires maintaining the crash consistency and encrypting data, to ensure data recoverability and data confidentiality. The enforcement of these two goals does not only put more burden on programmers but also degrades performance. To address this issue, we propose a hardware-assisted encrypted persistent memory system. Specifically, logging and data encryption are assisted by hardware. Furthermore, we apply the counter-based encryption and the cipher feedback (CFB) mode encryption to data and log respectively, reducing the encryption overhead. Our primary experimental results show that the transaction throughput of the proposed design outperforms the baseline design by up to 34.4%.

关键词： Encryption computer crashes Hardware Writing Programming

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ACGraph: Accelerating Streaming Graph Processing via Dependence Hierarchy

ACGraph: Accelerating Streaming Graph Processing via Depende...

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Design Automation Conference

作者： Zihan Jiang Fubing Mao Yapu Guo Xu Liu Haikun Liu Xiaofei Liao Hai Jin Wei Zhang National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China Department of Electronic and Computer Engineering HKUST Hong Kong

Streaming graph processing needs to timely evaluate continuous queries. Prior systems suffer from massive redundant computations due to the irregular order of processing vertices influenced by updates. To address this issue, we propose ACGraph, a novel streaming graph processing approach for monotonic graph algorithms. It maintains dependence trees during runtime, and makes affected vertices processed in a top-to-bottom order in the hierarchy of the dependence trees, thus normalizing the state propagation order and coalescing of multiple propagation to the same vertices. Experimental results show that ACGraph reduces the number of updates by 50% on average, and achieves the speedup of 1.75~7.43× over state-of-the-art systems.

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Superpage-Friendly Page Table Design for Hybrid Memory Systems

Superpage-Friendly Page Table Design for Hybrid Memory Syste...

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2020国际计算机前沿大会

作者： Xiaoyuan Wang Haikun Liu Xiaofei Liao Hai Jin National Engineering Research Center for Big Data Technology and System Huazhong University of Science and Technology Service Computing Technology and System Lab Huazhong University of Science and Technology Cluster and Grid Computing Lab Huazhong University of Science and Technology School of Computer Science and Technology Huazhong University of Science and Technology

Page migration has long been adopted in hybrid memory systems comprising dynamic random access memory(DRAM) and non-volatile memories(NVMs), to improve the system performance and energy ***, page migration introduces some side effects, such as more translation lookaside buffer(TLB) misses, breaking memory contiguity, and extra memory accesses due to page table updating. In this paper, we propose superpagefriendly page table called SuperPT to reduce the performance overhead of serving TLB misses. By leveraging a virtual hashed page table and a hybrid DRAM allocator, SuperPT performs address translations in a flexible and efficient way while still remaining the contiguity within the migrated pages.

关键词： Pagetable Hybridmemorysystem Pagemigration Multiplepagesizes Addresstranslation

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GIDN: A Lightweight Graph Inception Diffusion Network for High-efficient Link Prediction

arXiv

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arXiv 2022年

作者： Wang, Zixiao Guo, Yuluo Zhao, Jin Zhang, Yu Yu, Hui Liao, Xiaofei Wang, Biao Yu, Ting National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China Zhejiang Lab Hangzhou China

In this paper, we propose a Graph Inception Diffusion Networks(GIDN) model. This model generalizes graph diffusion in different feature spaces, and uses the inception module to avoid the large amount of computations caused by complex network structures. We evaluate GIDN model on Open Graph Benchmark(OGB) datasets, reached an 11% higher performance than AGDN on ogbl-collab dataset. Copyright © 2022, The Authors. All rights reserved.

关键词： Complex networks

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FlashWalker: An In-Storage Accelerator for Graph Random Walks

FlashWalker: An In-Storage Accelerator for Graph Random Walk...

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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： Fuping Niu Jianhui Yue Jiangqiu Shen Xiaofei Liao Haikun Liu Hai Jin National Engineering Research Center for Big Data Technology and System/Services Computing Technology and System Lab/Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China Department of Computer Science Michigan Technological University Houghton Michigan USA

Graph random walk is widely used in the graph processing as it is a fundamental component in graph analysis, ranging from vertices ranking to the graph embedding. Different from traditional graph processing workload, random walk features massive processing parallelisms and poor graph data reuse, being limited by low I/O efficiency. Prior designs for random walk mitigate slow I/O operations. However, the state-of-the-art random walk processing systems are bounded by slow disk I/O bandwidth, which is confirmed by our experiments with real-world graphs. To address this issue, we propose FlashWalker, an in-storage accelerator for random walk that moves walk updating close to graph data stored in flash memory, by exploiting significant parallelisms inside SSD. Featuring a heterogeneous and parallel processing system, FlashWalker includes a board-level accelerator, channel-level accelerators, and chip-level accelerators. To address challenges posed by the tight resource constraints for processing large-scale graphs, we propose novel designs: storing a few popular subgraphs in accelerators, the pre-walking for dense walks, two optimizations to search the subgraph mapping table, and a subgraph scheduling algorithm. We implement FlashWalker in RTL, showing small circuit area overhead. Our evaluation shows FlashWalker reduces the execution time of random walk algorithms by up to 660.50×, compared with GraphWalker, which is the state-of-the-art system for random walk algorithms.

关键词： Distributed processing Scheduling algorithms Bandwidth Parallel processing Distance measurement Flash memories Optimization

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On Pipelined GCN with Communication-Efficient Sampling and Inclusion-Aware Caching

On Pipelined GCN with Communication-Efficient Sampling and I...

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IEEE Annual Joint Conference: INFOCOM, IEEE computer and Communications Societies

作者： Shulin Wang Qiang Yu Xiong Wang Yuqing Li Hai Jin National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China School of Cyber Science and Engineering Wuhan University Wuhan China

ISBN: (数字)9798350383508

ISBN: (纸本)9798350383515

Graph convolutional network (GCN) has achieved enormous success in learning structural information from unstructured data. As graphs become increasingly large, distributed training for GCNs is severely prolonged by frequent cross-worker communications. Existing efforts to improve the training efficiency often come at the expense of GCN performance, while the communication overhead persists. In this paper, we propose PSC-GCN, a holistic pipelined framework for distributed GCN training with communication-efficient sampling and inclusion-aware caching, to address the communication bottleneck while ensuring satisfactory model performance. Specifically, we devise an asynchronous pre-fetching scheme to retrieve stale statistics (features, embedding, gradient) of boundary nodes in advance, such that the embedding aggregation and model update are pipelined with statistics transmission. To alleviate communication volume and staleness effect, we introduce a variance-reduction based sampling policy, which prioritizes inner nodes over boundary ones for reducing the access frequency to remote neighbors, thus mitigating cross-worker statistics exchange. Complementing graph sampling, a feature caching module is co-designed to buffer hot nodes with high inclusion probability, ensuring that frequently sampled nodes will be available in local memory. Extensive evaluations on real-world datasets show the superiority of PSC-GCN over state-of-the-art methods, where we can reduce training time by 72%-80% without sacrificing model accuracy.

关键词： Training Estimation error Accuracy Graph convolutional networks Computational modeling Probability Benchmark testing

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An Efficient Block Validation Mechanism for UTXO-based Blockchains

An Efficient Block Validation Mechanism for UTXO-based Block...

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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： Xiaohai Dai Bin Xiao Jiang Xiao Hai Jin National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology China Department of Computing The Hong Kong Polytechnic University Hong Kong

It has been recognized that one of the bottlenecks in the UTXO-based blockchain systems is the slow block validation - the process of validating a newly-received block by a node before locally storing it and further broadcasting it. As a block contains multiple inputs, the block validation mainly involves checking the inputs against the status data, which is also known as the Unspent Transaction Outputs (UTXO) set. As time goes by, the UTXO set becomes more and more expansive, most of which can only be stored on disks. This considerably slows down the input checking and thus block validation, which can potentially compromise system security. To deal with the above problem, we disassemble the function of input checking into three parts: existence validation (EV), unspent validation (UV), and script validation (SV). Based on the disassembly, we propose EBV, an efficient block validation mechanism to speed up EV, UV, and SV individually. First, EBV changes the representation of status data, from UTXO set to a bit-vector set, which drastically reduces its size. The smaller status data can be entirely maintained in memory, thereby accelerating UV and also block validation. Second, EBV requires each transaction to carry the proof data, which enables EV and SV without accessing the disks. Furthermore, we also cope with two challenges in the design of EBV, namely transaction inflation and fake positions. To evaluate the EBV mechanism, we implement a prototype on top of Bitcoin, the most widely known UTXO-based blockchain, and conduct extensive experiments to compare EBV and Bitcoin. The experimental results demonstrate that EBV successfully reduces the memory requirement by 93.1 % and the block validation time by up to 93.5%.

关键词： Distributed processing Memory management Prototypes Bitcoin Broadcasting Blockchains Delays

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LOPO: An Out-of-order Layer Pulling Orchestration Strategy for Fast Microservice Startup

LOPO: An Out-of-order Layer Pulling Orchestration Strategy f...

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IEEE Annual Joint Conference: INFOCOM, IEEE computer and Communications Societies

作者： Lin Gu Junhao Huang Shaoxing Huang Deze Zeng Bo Li Hai Jin National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China School of Computer Science China University of Geosciences Wuhan China Department of Computer Science and Engineering Hong Kong University of Science and Technology Hong Kong

Container based microservices have been widely applied to promote the cloud elasticity. The mainstream Docker containers are structured in layers, which are organized in stack with bottom-up dependency. To start a microservice, the required layers are pulled from a remote registry and stored on its host server, following the layer dependency order. This incurs long microservice startup time and hinders the performance efficiency. In this paper, we discover that, for the first time, the layer pulling order can be adjusted to accelerate the microservice startup. Specifically, we address the problem on microservice layer pulling orchestration for startup time minimization and prove it as NP-hard. We propose a Longest-chain based Out-of-order layer Pulling Orchestration (LOPO) strategy with low computational complexity and guaranteed approximation ratio. Through extensive real-world trace driven experiments, we verify the efficiency of our LOPO and demonstrate that it reduces the microservice startup time by 22.71% on average in comparison with state-of-the-art solutions.

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A Hybrid Memory Architecture Supporting Fine-Grained Data Migration

SSRN

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SSRN 2022年

作者： Chi, Ye Yue, Jianhui Liao, Xiaofei Liu, Haikun Jin, Hai National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan430074 China Computer Science Michigan Technological University HoughtonMI United States

We propose Mocha, a non-hierarchical caching architecture that organizes DRAM and NVM in a flat address space physically, but manages DRAM/NVM in a cache/memory hierarchy in this paper. Since the commercial NVM device-Intel Optane DC Persist Memory Modules (DCPMM) actually access the physical media at a granularity of 256 bytes (an Optane block), we manage the DRAM cache at the 256-byte size to adapt to this device feature of Optane. This design not only enables fine-grained data migration and management for the DRAM cache, but also avoids write amplification for Optane DCPMM. We also create a the \textit{ Indirect Address Cache} (IAC) in \textit{Hybrid Memory Controller}(HMC) and propose a reverse address mapping table in the DRAM to speed up address translation and cache replacement. Besides, we exploit an utility-based caching mechanism to filter cold blocks in the NVM, and further improve DRAM cache effectiveness. We implement Mocha in an architecture simulator. Experimental results indicate that MOCHA can improve performance of applications by 8.2\% on average (up to 24.6\%), provide 6.9\% reduction in average energy consumption and 25.9\% reduction in average data migration traffic, compared to the most advanced hybrid memory architecture-HSCC. © 2022, The Authors. All rights reserved.

关键词： Dynamic random access storage

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FusionANNS: An Efficient CPU/GPU Cooperative Processing Architecture for Billion-scale Approximate Nearest Neighbor Search

arXiv

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arXiv 2024年

作者： Tian, Bing Liu, Haikun Tang, Yuhang Xiao, Shihai Duan, Zhuohui Liao, Xiaofei Zhang, Xuecang Zhu, Junhua Zhang, Yu National Engineering Research Center for Big Data Technology and System Service Computing Technology and System Lab/Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology China Huawei Technologies Co. Ltd China

Approximate nearest neighbor search (ANNS) has emerged as a crucial component of database and AI infrastructure Ever-increasing vector datasets pose significant challenges in terms of performance, cost, and accuracy for ANNS services None of modern ANNS systems can address these issues simultaneously. We present FusionANNS, a high-throughput, low-latency cost-efficient, and high-accuracy ANNS system for billion scale datasets using SSDs and only one entry-level GPU The key idea of FusionANNS lies in CPU/GPU collabo rative filtering and re-ranking mechanisms, which signifi cantly reduce I/O operations across CPUs, GPU, and SSDs to break through the I/O performance bottleneck. Specifically we propose three novel designs: (1) multi-tiered indexing to avoid data swapping between CPUs and GPU, (2) heuristic re-ranking to eliminate unnecessary I/Os and computations while guaranteeing high accuracy, and (3) redundant-aware I/O deduplication to further improve I/O efficiency. We imple ment FusionANNS and compare it with the state-of-the-art SSD-based ANNS system–SPANN and GPU-accelerated in memory ANNS system–RUMMY. Experimental results show that FusionANNS achieves 1) 9.4-13.1× higher query per second (QPS) and 5.7-8.8× higher cost efficiency compared with SPANN;2) and 2-4.9× higher QPS and 2.3-6.8× higher cost efficiency compared with RUMMY, while guaranteeing low latency and high accuracy. Copyright © 2024, The Authors. All rights reserved.

关键词： Nearest neighbor search

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