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International Conference on Reconfigurable Computing and FPGAs (ReConFig)

作者： Omar W. Ibraheem Arif Irwansyah Jens Hagemeyer Mario Porrmann Ulrich Rueckert Cognitronics and Sensor Systems Group Bielefeld University Bielefeld Germany

In vision processing systems, many applications require multi-camera support. For the connection of the cameras to the processing system, multiple interfaces and a platform capable of handling sustained high data rates are essential. To cope with these requirements, a hardware-based solution using FPGA technology is advisable, especially when targeting space and energy constrained embedded systems. The aim of this work is to develop and implement an FPGA-based scalable and resource-efficient multi-camera GigE Vision IP core for video and image processing. To reduce the number of interfaces needed, the IP core supports the connection of multi-camera interfaces to a single Gigabit Ethernet port using an Ethernet switch. The multi-camera GigE Vision IP core is able to extract the raw video data from multiple GigE Vision video streams, reconstruct the video frames from every camera and pass these data for further processing. To test the system, four GigE Vision cameras are used. The IP core is implemented on a Xilinx Virtex-4 FPGA and integrated in a complete video processing platform for a full system realization. In addition to the IP core, bilinear interpolation for image demosaicing with Bayer pattern and an automatic white balance algorithm are implemented for evaluation of the platform. Benchmarking of the hardware implementation has been performed with a total resolution of up to 2048x2048 pixels. Achieved frame rates vary from 25 fps to 345 fps depending on the selected resolution and on the number of used cameras.

关键词： Cameras IP networks Streaming media Field programmable gate arrays Data mining Machine vision Protocols

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A 65 nm standard cell library for ultra low-power applications

A 65 nm standard cell library for ultra low-power applicatio...

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European Conference on Circuit Theory and Design, ECCTD

作者： Marten Vohrmann Saikat Chatterjee Sven Lütkemeier Thorsten Jungeblut Mario Porrmann Ulrich Rückert Cognitronics and Sensor Systems Group Bielefeld University Bielefeld Germany Beckhoff Automation GmbH & Co. KG

This paper describes the development of a 65nm standard cell library designed for building highly energy-efficient digital circuits. In total 43 logic cells and 19 special cells for clock-tree synthesis and place and route purposes are implemented using a commercial 65 nm bulk technology. As a result full-chip implementation of low-power systems operating at ultra-low voltage is feasible. The benefits of this subthreshold cell design are demonstrated by synthesis and analysis of a sample circuit for supply voltages from 250 mV to 1.2 V. Power analysis at gate-level shows an improvement in energy consumption by a factor of 9.25 with a total energy consumption of 11.7pJ per clock cycle in the subthreshold domain.

关键词： Clocks Logic gates Libraries Standards Transistors Optimization Robustness

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Evaluation of Interconnect Fabrics for an Embedded MPSoC in 28 nm FD-SOI

Evaluation of Interconnect Fabrics for an Embedded MPSoC in ...

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IEEE International Symposium on Circuits and systems

作者： Gregor Sievers Johannes Ax Nils Kucza Martin Flasskamp Thorsten Jungeblut Wayne Kelly Mario Porrmann Ulrich Ruckert Cognitronics and Sensor Systems Group CITEC Bielefeld University Bielefeld Germany Science and Engineering Faculty Queensland University of Technology Brisbane Australia

ISBN: (纸本)9781479983926

Embedded many-core architectures contain dozens to hundreds of CPU cores that are connected via a highly scalable NoC interconnect. Our Multiprocessor-System-on-Chip CoreVA-MPSoC combines the advantages of tightly coupled bus-based communication with the scalability of NoC approaches by adding a CPU cluster as an additional level of hierarchy. In this work, we analyze different cluster interconnect implementations with 8 to 32 CPUs and compare them in terms of resource requirements and performance to hierarchical NoCs approaches. Using 28 nm FD-SOI technology the area requirement for 32 CPUs and AXI crossbar is 5.59mm~2 including 23.61% for the interconnect at a clock frequency of 830MHz. In comparison, a hierarchical MPSoC with 4 CPU cluster and 8 CPUs in each cluster requires only 4.83 mm~2 including 11.61% for the interconnect. To evaluate the performance, we use a compiler for streaming applications to map programs to the different MPSoC configurations. We use this approach for a design-space exploration to find the most efficient architecture and partitioning for an application.

关键词： central processing units resource requirements clock frequency Scalability Space Exploration compilers core construction embedding

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Comparison of Shared and Private L1 Data Memories for an Embedded MPSoC in 28nm FD-SOI

Comparison of Shared and Private L1 Data Memories for an Emb...

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IEEE International Symposium on Embedded Multicore Socs (MCSoC)

作者： Gregor Sievers Julian Daberkow Johannes Ax Martin Flasskamp Wayne Kelly Thorsten Jungeblut Mario Porrmann Ulrich Rückert Cognitronics and Sensor Systems Group CITEC Bielefeld University Bielefeld Germany Science and Engineering Faculty Queensland University of Technology Brisbane Australia

Tightly coupling CPUs within clusters allows for low latency, high bandwidth communication in MPSoCs. Our CoreVA-MPSoC integrates multiple clusters using an on-chip network. In this work we introduce a shared L1 data memory that can be accessed by all CPUs of a cluster with low latency. A Mesh-of-Trees (MoT) and a crossbar as topology for the shared memory interconnect are presented. A cluster that integrates the shared L1 memory is compared with an architecture that features an AXI interconnect and a local L1 data memory for each CPU. In addition, we consider an architecture that integrates both. We present implementation results using a 28nm FD-SOI standard cell technology. The shared L1 memory shows similar area results compared to the local memory architecture. Place and route results of a cluster with 8 CPUs, 128kB local-and 128kB shared L1 data memory divided into 16 memory banks show a frequency of 728MHz and an area of 1.77mm2. To map programs to the different CPU cluster configurations a compiler for streaming applications is used. An architecture with both local and shared L1 data memory and 4 memory banks shows best performance results in combination with a high resource efficiency.

关键词： Clocks Memory management Central Processing Unit Standards Routing Topology

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Data centres for IoT applications: The M2DC approach (Invited paper)

Data centres for IoT applications: The M2DC approach (Invite...

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International Conference on Embedded Computer systems: Architectures, Modeling and Simulation (IC-SAMOS)

作者： Michal Kierzynka Ariel Oleksiak Giovanni Agosta Carlo Brandolese William Fornaciari Gerardo Pelosi Micha vor dem Berge Wolfgang Christmann Stefan Krupop Mariano Cecowski Robert Plestenjak Justin Cinkelj Mario Porrmann Jens Hagemeyer René Griessl Meysam Peykanu Lennart Tigges Loïc Cudennec Thierry Goubier Jean-Marc Philippe Sven Rosinger Daniel Schlitt Christian Pieper Chris Adeniyi-Jones Udo Janssen Luca Ceva Poznan Supercomputing and Networking Center Poznan Poland DEIB – Politecnico di Milano Milano Italy christmann informationstechnik + medien GmbH & Co. KG Ilsede Germany XLAB d.o.o. Ljubljana Slovenia Cognitronics and Sensor Systems Group CITEC Bielefeld University Germany CEA LIST OFFIS e. V. – Institute for Information Technology ARM Ltd. Cambridge UK CEWE Stiftung & Co. KGaA

The Modular Microserver DataCentre (M2DC) project investigates, develops and demonstrates a modular, highly-efficient, cost-optimized server architecture composed of heterogeneous micro server computing resources, being able to be tailored to meet requirements from various application domains, including the Internet of Things. M2DC is built on three main pillars: a flexible server architecture that can be easily customised, maintained and updated; advanced management strategies and system efficiency enhancements (SEE); well-defined interfaces to surrounding software data centre ecosystem.

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Data centres for IoT applications: The M2DC approach (Invited paper) 16

Data centres for IoT applications: The M2DC approach (Invite...

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16th International Conference on Embedded Computer systems: Architectures, Modeling and Simulation, SAMOS 2016

作者： Oleksiak, Michal Kierzynka Ariel Agosta, Giovanni Brandolese, Carlo Fornaciari, William Pelosi, Gerardo Vor Dem Berge, Micha Christmann, Wolfgang Krupop, Stefan Cecowski, Mariano Plestenjak, Robert Cinkelj, Justin Porrmann, Mario Hagemeyer, Jens Griessl, Rene Peykanu, Meysam Tigges, Lennart Cudennec, Loic Goubier, Thierry Philippe, Jean-Marc Rosinger, Sven Schlitt, Daniel Pieper, Christian Adeniyi-Jones, Chris Janssen, Udo Ceva, Luca Poznan Supercomputing and Networking Center ul. Noskowskiego 10 Poznan61-704 Poland DEIB - Politecnico di Milano Piazza Leonardo da Vinci 32 Milano Italy Christmann Informationstechnik + Medien GmbH and Co. KG Ilseder Huette 10c Ilsede31241 Germany XLAB D.o.o. Pot za Brdom 100 Ljubljana1000 Slovenia Cognitronics and Sensor Systems Group CITEC Bielefeld University Germany CEA LIST PC 172 Gif-sur-Yvette Cedex91191 France OFFIS E.V. - Institute for Information Technology Germany ARM Ltd. CPC-1 Capital Park Fulbourn CambridgeCB21 5XE United Kingdom CEWE Stiftung and Co. KGaA Germany Vodafone Telematics United Kingdom

ISBN: (纸本)9781509030767

The Modular Microserver DataCentre (M2DC) project investigates, develops and demonstrates a modular, highly-efficient, cost-optimized server architecture composed of heterogeneous micro server computing resources, being able to be tailored to meet requirements from various application domains, including the Internet of Things. M2DC is built on three main pillars: a flexible server architecture that can be easily customised, maintained and updated;advanced management strategies and system efficiency enhancements (SEE);well-defined interfaces to surrounding software data centre ecosystem. © 2016 IEEE.

关键词： Internet of things

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Identification of athletes during walking and jogging based on gait and electrocardiographic patterns

Communications in Computer and Information Science

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Communications in Computer and Information Science 2014年 452卷 240-257页

作者： Christ, Peter Rückert, Ulrich Cognitronics and Sensor Systems Group CITEC Bielefeld University Universitätsstr. 21-23 Bielefeld33615 Germany

ISBN: (纸本)9783662444849

We propose a biometric method for identifying athletes based on information extracted from the gait style and the electrocardiographic (ECG) waveform. The required signals are recorded within a non-clinical acquisition setup using a wireless body sensor attached to a chest strap with integrated textile electrodes. Our method combines both sources of information to allow identification despite severe intra-subjects variations in the gait patterns (walking and jogging) and motion related artefacts in the ECG patterns. For identification we use features extracted in time and frequency domain and a standard classifier. Within a treadmill experiment with 22 subjects we obtained an accuracy of 98.1% for velocities from 3 to 9 km/h. On a second data set consisting of 9 subjects and two sessions of recording, our method achieved 93.8% despite variations in the patterns due to reapplying the body sensor and an increased velocity (up to 11 km/h). © Springer-Verlag Berlin Heidelberg 2014.

关键词： Pattern recognition

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CoreVA: A Configurable Resource-Efficient VLIW Processor Architecture

CoreVA: A Configurable Resource-Efficient VLIW Processor Arc...

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IEEE/IFIP International Conference on Embedded and Ubiquitous Computing, EUC

作者： Boris Hübener Gregor Sievers Thorsten Jungeblut Mario Porrmann Ulrich Rückert Cognitronics and Sensor Systems Group Bielefeld University Bielefeld Germany

Mobile signal processing applications have a limited energy budget and require resource-efficient processing elements. General purpose VLIW CPUs offer a high energy efficiency and allow for the execution of a wide range of applications in this domain. In this work we present the configurable 32 bit VLIW processor architecture CoreVA. Besides the number of issue slots, it allows for a fine-grained configuration of the amount and characteristics of the processor's functional units (e.g., ALUs, MACs, or LD/ST units). A design-space exploration is performed to evaluate how these functional units impact area and power consumption. The basic configuration with one ALU, MAC, DIV, and LD/ST unit has a power consumption of 11.796 mW and an area of 0.142 mm2 at a clock frequency of 750 MHz in a 28 nm FD-SOI process. The maximum clock frequency in this process node is 833 MHz. To bear a relation of the hardware requirements to possible performance gains of the application, a signal processing algorithm is used as a benchmark to evaluate the energy consumption of different hardware configurations. The lowest energy consumption is observed with a configuration of 4 issue slots using 4 ALUs, 4 MACs, and 2 LD/ST units. This is an improvement by a factor of 1.68 compared to the single issue slot configuration.

关键词： VLIW Registers Pipelines Clocks Computer architecture Hardware Power demand

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A respiration sensor for a chest-strap based wireless body sensor

A respiration sensor for a chest-strap based wireless body s...

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IEEE sensorS

作者： Marc Hesse Peter Christ Timm Hörmann Ulrich Rückert Cognitronics and Sensor Systems Group CITEC Bielefeld University Bielefeld

In this paper we present a respiration sensor suitable for an integration into a wireless body sensor worn around the chest. The thorax expansion and contraction during in- and exhalation is captured using a force-sensing resistor. Based on the captured thoracic movements, the breaths are determined with a peak detection algorithm. For evaluation, a treadmill experiment with five subjects was conducted using an ergospirometry system as a reference. Overall, an average deviation of -0.32±0.68 min -1 in the respiration rate between the ergospirometry and our sensor was observed. In general, the captured thoracic movements showed breaths as distinctive oscillations, but in some cases a non-optimal pressure transfer between thorax and sensor was observed. Therefore, a mechanical housing mechanism was developed. A comparison of our construction with a respiratory inductance plethysmography (RIP)-based sensor shows a close relationship with the captured thoracic movements during normal and deep respiration.

关键词： Resistors Temperature measurement Wireless sensor networks Wireless communication Biomedical monitoring Plethysmography Accelerometers

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AXI-based SpaceFibre IP core implementation 6

AXI-based SpaceFibre IP core implementation

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6th International SpaceWire Conference, SpaceWire 2014

作者： Jungewelter, D. Cozzi, D. Kleibrink, D. Korf, S. Hagemeyer, J. Porrmann, M. Ilstad, J. Cognitronics and Sensor Systems Group CITEC Bielefeld University Inspiration 1 Bielefeld33619 Germany TEC-EDP ESTEC European Space Agency Keplerlaan 1 Noordwijk ZH2220 AG Netherlands

ISBN: (纸本)9780955719653

The steadily increasing demand of high-throughput interfaces, e.g., in satellite payload processing systems, drives the development of faster data transmission systems. The emerging SpaceFibre standard offers a multi-gigabit serial connection which is specified on the physical and data link layer while reusing the SpaceWire protocol specification on the higher protocol layers, thus enabling compatibility on the software layer. The AXI SpaceFibre IP core presented in this paper combines the SpaceFibre CODEC IP core developed by STAR-Dundee, a TLK2711 WizardLink Transceiver (meeting the SpaceFibre specification with up to 2.7 Gbit/s), and a DMA interface that connects the IP core to any AXI-based reconfigurable system-on-chip using FPGAs. The IP core configuration and initialization registers for the SpaceFibre RX and TX channels are accessible via AXI4-lite slave interfaces while the payload data is handled by a dedicated scatter/gather AXI-DMA core, which is connected to AXI-Stream FIFOs to provide the maximal possible payload transaction performance. The SpaceFibre IP core can be configured to implement 1 to 8 virtual channels. To evaluate the performance of the SpaceFibre IP core, we integrated it into the "Dynamically Reconfigurable Processing Module" (DRPM), a multi FPGA platform for satellite data payload processing. The AXI-based SpaceFibre IP core was synthesized on a Xilinx Spartan-6 LX150, utilizing in total 2668 slices and 36 BRAMs. For data segments larger than 1 kByte, a bandwidth of approximately 1.9 Gbit/s was achieved, corresponding to 95 % of the possible bandwidth. The IP core will be part of the ESA IP core repository. © 2014 University of Dundee.

关键词： System-on-chip

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