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International SpaceWire Conference (SpaceWire)

作者： D. Jungewelter D. Cozzi D. Kleibrink S. Korf J. Hagemeyer M. Porrmann J. Ilstad Cognitronics and Sensor Systems Group CITEC Bielefeld University Bielefeld Germany TEC-EDP ESTEC European Space Agency Noordwijk ZH The Netherlands

The steadily increasing demand of high-throughput interfaces, e.g., in satellite payload processing systems, drives the development of faster data transmission systems. The emerging SpaceFibre standard offers a multi-gigabit serial connection which is specified on the physical and data link layer while reusing the SpaceWire protocol specification on the higher protocol layers, thus enabling compatibility on the software layer. The AXI SpaceFibre IP core presented in this paper combines the SpaceFibre CODEC IP core developed by STAR-Dundee, a TLK2711 WizardLink Transceiver (meeting the SpaceFibre specification with up to 2.7 Gbit/s), and a DMA interface that connects the IP core to any AXI-based reconfigurable system-on-chip using FPGAs. The IP core configuration and initialization registers for the SpaceFibre RX and TX channels are accessible via AXI4-lite slave interfaces while the payload data is handled by a dedicated scatter/gather AXI-DMA core, which is connected to AXI-Stream FIFOs to provide the maximal possible payload transaction performance. The SpaceFibre IP core can be configured to implement 1 to 8 virtual channels. To evaluate the performance of the SpaceFibre IP core, we integrated it into the “Dynamically Reconfigurable Processing Module” (DRPM), a multi FPGA platform for satellite data payload processing. The AXI-based SpaceFibre IP core was synthesized on a Xilinx Spartan-6 LX150, utilizing in total 2668 slices and 36 BRAMs. For data segments larger than 1 kByte, a bandwidth of approximately 1.9 Gbit/s was achieved, corresponding to 95 % of the possible bandwidth. The IP core will be part of the ESA IP core repository.

关键词： IP networks Field programmable gate arrays Bandwidth Payloads Codecs Power cables Registers

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A communication model and partitioning algorithm for streaming applications for an embedded MPSoC

A communication model and partitioning algorithm for streami...

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IEEE International Symposium on System-on-Chip

作者： Wayne Kelly Martin Flaßkamp Gregor Sievers Johannes Ax Jianing Chen Christian Klarhorst Christoph Ragg Thorsten Jungeblut Andrew Sorensen Science and Engineering Faculty Queensland University of Technology Brisbane Australia Universitat Bielefeld Bielefeld Nordrhein-Westfalen DE Cognitronics and Sensor Systems Group Bielefeld University Bielefeld Germany

Energy efficient embedded computing enables new application scenarios in mobile devices like software-defined radio and video processing. The hierarchical multiprocessor considered in this work may contain dozens or hundreds of resource efficient VLIW CPUs. Programming this number of CPU cores is a complex task requiring compiler support. The stream programming paradigm provides beneficial properties that help to support automatic partitioning. This work describes a compiler for streaming applications targeting the self-build hierarchical CoreVA-MPSoC multiprocessor platform. The compiler is supported by a programming model that is tailored to fit the streaming programming paradigm. We present a novel simulated-annealing (SA) based partitioning algorithm, called Smart SA. The overall speedup of Smart SA is 12.84 for an MPSoC with 16 CPU cores compared to a single CPU implementation. Comparison with a state of the art partitioning algorithm shows an average performance improvement of 34.07%.

关键词： Program processors Partitioning algorithms Signal processing algorithms Parallel processing Simulated annealing Pipelines Computer architecture

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A Scalable Server Architecture for Next-Generation Heterogeneous Compute Clusters

A Scalable Server Architecture for Next-Generation Heterogen...

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IEEE/IFIP International Conference on Embedded and Ubiquitous Computing, EUC

作者： René Griessl Meysam Peykanu Jens Hagemeyer Mario Porrmann Stefan Krupop Micha vor dem Berge Thomas Kiesel Wolfgang Christmann Cognitronics and Sensor Systems Group Bielefeld University Germany Christmann informationstechnik + medien GmbH & Co. KG Ilsede Germany Christmann Informationstechnik + Medien GmbH & Co. KG Ilsede Germany

Increasing the energy efficiency of today's high-performance computing systems requires new approaches that go beyond homogeneous architectures, which primarily target maximum performance per node. Heterogeneous architectures that can be tailored towards the specific needs of a particular application are a promising alternative to state-of-the-art server systems. In this paper, we present a novel highly-scalable server architecture that seamlessly integrates variable combinations of general purpose CPUs, embedded CPUs, FPGAs, and GPUs. Embedded CPUs based on the latest ARM Cortex-A15 devices with integrated embedded GPUs are combined with FPGA-based reconfigurable SoCs, which can be used for application-specific hardware acceleration. A dedicated monitoring network enables continuous control and fine-grained observation of all relevant system parameters. Communication between the compute nodes is established by a flexible multi-level interconnect that can be adapted to various Ethernet and Infiniband standards. The communication facilities are further enhanced by direct high-bandwidth, low-latency links between the embedded FPGA-based reconfigurable SoCs.

关键词： Monitoring Computer architecture Field programmable gate arrays Switches Servers Hardware Standards

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Pareto-optimal signal processing on low-power microprocessors

Pareto-optimal signal processing on low-power microprocessor...

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12th IEEE sensorS 2013 Conference

作者： Christ, Peter Sievers, Gregor Einhaus, Julian Jungeblut, Thorsten Porrmann, Mario Ruckert, Ulrich Cognitronics and Sensor Systems Group CITEC Bielefeld University 33619 Bielefeld Germany

ISBN: (纸本)9781467346405

Miniaturised wireless body sensors equipped with low-power microcontrollers are used in various energy-constrained applications. The signal-processing algorithms often require running in real-time on a low computational and memory budget. In this paper we present a framework for the exploration of the design space of resource-efficient signal processing suitable for embedded processors. Using a velocity estimation algorithm for an athlete, we show which configurations of the algorithm perform best in respect to classification accuracy and runtime. Altering the sampling frequency, the feature combination, the classifier (Artificial Neural Network (ANN), Decision Tree (DT)), or the classifier's parametrisation, we obtained 15 Pareto-optimal configurations out of 1008 simulations. The highest classification accuracy of 93.92% was obtained using an ANN, and required 22422 clock cycles per classification. The lowest cycle count of 204 was obtained with a DT configuration which resulted in 84.66 % accuracy. © 2013 IEEE.

关键词： Decision trees

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Athlete identification using acceleration and electrocardiographic measurements recorded with a wireless body sensor

Athlete identification using acceleration and electrocardiog...

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International Conference on Bio-Inspired systems and Signal Processing, BIOSIGNALS 2013

作者： Christ, Peter Werner, Felix Rückert, Ulrich Mielebacher, Jörg Cognitronics and Sensor Systems Group CITEC Bielefeld University Bielefeld Germany Mielebacher Informatiksysteme Fahrenheitstr. 1 Bremen Germany

ISBN: (纸本)9789898565365

In this paper we propose a biometric method for identifying humans during walking and jogging. We use acceleration and electrocardiographic measurements recorded with a wireless body sensor attached to a chest strap. Our method does not require a particular acquisition setup. Information on the gait style and on the physiology is combined to identify a human despite severe motion related artefacts in the electrocardiograph and variations in the gait patterns. We propose to identify humans using features extracted in time and frequency domain and a standard classifier. With the collected data of 22 subjects on a treadmill at velocities from 3 to 9km/h we obtained an accuracy of 98.1%. The sensitivity of the identification ranged between 94.6 to 99.5 % for the different subjects and the specificity was higher than 99.7 %.

关键词： Pattern recognition

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Design-space exploration of the configurable 32 bit VLIW processor CoreVA for signal processing applications

Design-space exploration of the configurable 32 bit VLIW pro...

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Norchip

作者： Gregor Sievers Peter Christ Julian Einhaus Thorsten Jungeblut Mario Porrmann Ulrich Rückert Cognitronics and Sensor Systems Group CITEC Bielefeld University Bielefeld Germany

In this paper we present the results of a design-space exploration for a classification algorithm with respect to the inherent parallelism of the CoreVA CPU. The CoreVA is a configurable VLIW processor which has been mainly designed for energy-constrained applications. Energy-efficient signal-processing is essential for real-time applications on wireless body sensors (WBSs). Using a velocity-estimation algorithm for a runner as an example, we show which hardware and algorithm configurations perform best in respect to classification accuracy, runtime and energy consumption. We obtained 9 Pareto-optimal configurations out of 504 simulations. The highest classification accuracy of 93.4% requires 34687 clock cycles and has an energy consumption of 1.559 μJ. The lowest energy requirements of 0.015μJ per classification are observed with a Pareto-optimal configuration at 76.3% accuracy. The three-issue VLIW configuration shows the best results with respect to the area-energy trade-off.

关键词： VLIW Accuracy Computer architecture Algorithm design and analysis Artificial neural networks Energy consumption Signal processing algorithms

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Pareto-optimal Signal Processing on Low-Power Microprocessors

Pareto-optimal Signal Processing on Low-Power Microprocessor...

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IEEE sensors

作者： Peter Christ Gregor Sievers Julian Einhaus Thorsten Jungeblut Mario Porrmann Ulrich Ruckert Cognitronics and Sensor Systems Group CITEC Bielefeld University 33619 Bielefeld

ISBN: (纸本)9781467346412

Miniaturised wireless body sensors equipped with low-power microcontrollers are used in various energy-constrained applications. The signal-processing algorithms often require running in real-time on a low computational and memory budget. In this paper we present a framework for the exploration of the design space of resource-efficient signal processing suitable for embedded processors. Using a velocity estimation algorithm for an athlete, we show which configurations of the algorithm perform best in respect to classification accuracy and runtime. Altering the sampling frequency, the feature combination, the classifier (Artificial Neural Network (ANN), Decision Tree (DT)), or the classifier's parametrisation, we obtained 15 Pareto-optimal configurations out of 1008 simulations. The highest classification accuracy of 93.92 % was obtained using an ANN, and required 22422 clock cycles per classification. The lowest cycle count of 204 was obtained with a DT configuration which resulted in 84.66 % accuracy.

关键词： Processing Signal Pareto-optimal

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Teletesting: Path planning experimentation and benchmarking in the Teleworkbench

Teletesting: Path planning experimentation and benchmarking ...

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European Conference on Mobile Robots (ECMR)

作者： Andry Tanoto Javier V. Gómez Nikolaos Mavridis Hanyi Li Ulrich Rückert Santiago Garrido System and Circuit Technology University of Paderborn Paderborn Germany RoboticsLab Carlos III University of Madrid Madrid Spain SKEL group Institute of Informatics and Telecommunications Athens Greece Cognitronics and Sensor Systems Group Bielefeld University Bielefeld Germany

Experimental evaluation of navigation algorithms requires physical robots as well as position sensing devices. The common alternative is to use simulations to run the experiments. However, simulation often does not provide an accurate prediction of real-world behavior. Therefore, in this paper, we present an innovative approach towards evaluation of navigation algorithms, which does not need physical robots and position sensors to be present at the experimenter's site, but relies on a special remote internet-accessible physical testbed, the “Teleworkbench”, which can be used in order to evaluate as well as uniformly cross-compare algorithms with no need of spending money on hardware or simulation software. More specifically, in this paper we are using the Teleworkbench to evaluate three different path planning algorithms, and compare it with simulation. Different metrics are proposed, such as the path execution time, smoothness and path clearance deviations. Our results clearly illustrate the superiority of the Telework-bench as an evaluation platform in comparison to simulation, which does not provide an accurate prediction of actual physical performance, and thus illustrate both the viability as well as the power of our novel approach.

关键词： Teleworking Robot sensing systems Frequency modulation Servers Path planning Computer architecture

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Local Navigation Strategies for Multi-Robot Exploration: From Simulation to Experimentation with Mini-Robots

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Procedia Engineering 2012年 41卷 1197-1203页

作者： Andry Tanoto Ulrich Rückert System and Circuit Technology Heinz Nixdorf Institute University of Paderborn Füurstenallee 11 Paderborn 33102 Cognitronics and Sensor Systems Group Cognitive Interaction Technology Centre of Excellence (CITEC) Bielefeld University 33615 Bielefeld Germany

This paper presents two local navigation strategies for multi-robot systems in performing exploration of unknown environments. The strategies are based on the frontier cell for mapping the environment and navigating in it. Additionally, two coordination strategies are used to solve possible conﬂicts among robots. Key criteria investigated are the efﬁciency and effectiveness represented by the completion time, travelled distance, the total steps, and the task distribution. The developed algorithms are tested in simulations as well as in experiments with Khepera III mini robots running on the Teleworkbench. To evaluate the robustness of the developed algorithms, tests are performed under different environmental conﬁgurations and varying numbers of robots. The results show the advantages of both proposed strategies in different situations such as environment types and starting positions.

关键词： Multi-robot system Environment exploration Mini Robot Teleworkbench Robot experiment

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Scalable and flexible vision-based multi-robot tracking system

Scalable and flexible vision-based multi-robot tracking syst...

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IEEE International Symposium on Intelligent Control (ISIC)

作者： Andry Tanoto Hanyi Li Ulrich Rückert Joaquin Sitte System and Circuit Technology Heinz Nixdorf Institute University of Paderborn Paderborn Germany The Cognitronics and Sensor Systems Group Cognitive Interaction Technology Centre of Excellence (CITEC) Bielefeld University Bielefeld Germany The Faculty of Science and Technology Queensland University of Technology Brisbane QLD Australia

Precise position is necessary for a robot to reliably localize itself and navigate in the environment. Robot position can be calculated internally or acquired from an external system. This paper presents a software architecture of a vision-based robot tracking system that can provide precise position information as well as identification of many robots. The software architecture has been designed to take into consideration the need for a flexible and scalable system that can interoperate with many similar systems and support different types of image sources, image processing, and outputs. With the architecture, future enhancements or replacements can be implemented as plug-ins, which can be easily integrated into the system. This paper also demonstrates the proposed architecture in different application scenarios.

关键词： Streaming media Cameras Servers Robot vision systems System recovery

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