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International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015

作者： Irwansyah, Arif Ibraheem, Omar W. Hagemeyer, Jens Porrmann, Mario Rueckert, Ulrich Cognitronics and Sensor Systems Group CITEC Bielefeld University Bielefeld Germany

ISBN: (纸本)9781467394062

Shape-based object detection and recognition are frequently used methods in the field of computer vision. A well-known algorithm for circle detection is the Circular Hough Transform (CHT). This Hough Transform algorithm needs a huge memory space and large computational resources. Field Programmable Gate Array (FPGA)-based hardware accelerators can be used to efficiently handle such compute-intensive applications. In this paper, we present a resource-efficient FPGA-based architecture for the CHT algorithm. Additionally, we introduce a unique approach by combining the CHT algorithm with graph clustering. The combination of these algorithms and their implementation on a Xilinx Virtex-4 FPGA is used to support real-time vision-based multi-robot tracking. Furthermore, an efficient architecture is proposed to significantly reduce the required memory in the CHT module. For the Graph Clustering module, a multiplier-less distance calculation unit is implemented, significantly reducing the required FPGA resources. The proposed CHT design can handle multi-robot localization with an accuracy of 97 %, supporting a maximum video resolution of 1024x1024 with 128 frames per second, resulting in 134 MPixel/s. Our design provides significantly higher throughput compared to other implementations on embedded processors, FPGAs, and general purpose CPUs. Compared to an OpenCV implementation on a 3.2 GHz desktop CPU, our implementation achieves a speed-up of more than 5.7. © 2015 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Robust estimation of physical activity by adaptively fusing multiple parameters 12

Robust estimation of physical activity by adaptively fusing ...

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12th IEEE International Conference on Wearable and Implantable Body sensor Networks, BSN 2015

作者： Hormann, Timm Christ, Peter Hesse, Marc Ruckert, Ulrich Cognitronics and Sensor Systems Group CITEC Bielefeld University Bielefeld33619 Germany

ISBN: (纸本)9781467372015

Raising the awareness of being physically active by utilizing wearable body sensors has become a popular research topic. Recent approaches combine physical and physiological information to obtain a precise prediction of a person;s physical activity ratio. However, the error in the determination of physical activity due to invalid physiological values that are resulting from underlying signal disturbances, has so far not been considered. We therefore present a robust measure of activity that fuses accelerometer data, heart rate and other personalized features, and is adaptively responding to missing physiological sensor data. To set up the model, we make use of regression analysis (MARS). Our findings indicate the need for considering signal quality when estimating physical activity. The predictive model shows close agreement (R2 = 0.97) to the reference from indirect calorimetry, even if the physiological information is partly corrupted. © 2015 IEEE.

关键词： Regression analysis

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System-Level Analysis of Network Interfaces for Hierarchical MPSoCs 8

System-Level Analysis of Network Interfaces for Hierarchical...

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8th International Workshop on Network on Chip Architectures, NoCArc 2015

作者： Ax, Johannes Sievers, Gregor Flasskamp, Martin Kelly, Wayne Jungeblut, Thorsten Porrmann, Mario Cognitronics and Sensor Systems Group CITEC Bielefeld University Bielefeld Germany Science and Engineering Faculty Queensland University of Technology Brisbane Australia

ISBN: (纸本)9781450339636

Network Interfaces (NIs) are used in Multiprocessor System- on-Chips (MPSoCs) to connect CPUs to a packet switched Network-on-Chip. In this work we introduce a new NI archi- tecture for our hierarchical CoreVA-MPSoC. The CoreVA- MPSoC targets streaming applications in embedded systems. The main contribution of this paper is a system-level analysis of different NI configurations, considering both software and hardware costs for NoC communication. Different configura- tions of the NI are compared using a benchmark suite of 10 streaming applications. The best performing NI configuration shows an average speedup of 20 for a CoreVA-MPSoC with 32 CPUs compared to a single CPU. Furthermore, we present physical implementation results using a 28 nm FD-SOI stan- dard cell technology. A hierarchical MPSoC with 8 CPU clusters and 4 CPUs in each cluster running at 800MHz requires an area of 4.56mm2. © 2015 ACM.

关键词： Network-on-chip

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Robust estimation of physical activity by adaptively fusing multiple parameters

Robust estimation of physical activity by adaptively fusing ...

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International Workshop on Wearable and Implantable Body sensor Networks (BSN)

作者： Timm Hörmann Peter Christ Marc Hesse Ulrich Rückert Cognitronics and Sensor Systems Group CITEC Bielefeld University Bielefeld

Raising the awareness of being physically active by utilizing wearable body sensors has become a popular research topic. Recent approaches combine physical and physiological information to obtain a precise prediction of a person;s physical activity ratio. However, the error in the determination of physical activity due to invalid physiological values that are resulting from underlying signal disturbances, has so far not been considered. We therefore present a robust measure of activity that fuses accelerometer data, heart rate and other personalized features, and is adaptively responding to missing physiological sensor data. To set up the model, we make use of regression analysis (MARS). Our findings indicate the need for considering signal quality when estimating physical activity. The predictive model shows close agreement (R 2 = 0.97) to the reference from indirect calorimetry, even if the physiological information is partly corrupted.

关键词： Heart rate Electrocardiography Mathematical model Predictive models Mars Accelerometers Estimation

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Evaluation of Interconnect Fabrics for an Embedded MPSoC in 28 nm FD-SOI

Evaluation of Interconnect Fabrics for an Embedded MPSoC in ...

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IEEE International Symposium on Circuits and systems

作者： Gregor Sievers Johannes Ax Nils Kucza Martin Flasskamp Thorsten Jungeblut Wayne Kelly Mario Porrmann Ulrich Ruckert Cognitronics and Sensor Systems Group CITEC Bielefeld University Bielefeld Germany Science and Engineering Faculty Queensland University of Technology Brisbane Australia

ISBN: (纸本)9781479983926

Embedded many-core architectures contain dozens to hundreds of CPU cores that are connected via a highly scalable NoC interconnect. Our Multiprocessor-System-on-Chip CoreVA-MPSoC combines the advantages of tightly coupled bus-based communication with the scalability of NoC approaches by adding a CPU cluster as an additional level of hierarchy. In this work, we analyze different cluster interconnect implementations with 8 to 32 CPUs and compare them in terms of resource requirements and performance to hierarchical NoCs approaches. Using 28 nm FD-SOI technology the area requirement for 32 CPUs and AXI crossbar is 5.59mm~2 including 23.61% for the interconnect at a clock frequency of 830MHz. In comparison, a hierarchical MPSoC with 4 CPU cluster and 8 CPUs in each cluster requires only 4.83 mm~2 including 11.61% for the interconnect. To evaluate the performance, we use a compiler for streaming applications to map programs to the different MPSoC configurations. We use this approach for a design-space exploration to find the most efficient architecture and partitioning for an application.

关键词： central processing units resource requirements clock frequency Scalability Space Exploration compilers core construction embedding

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Comparison of Shared and Private L1 Data Memories for an Embedded MPSoC in 28nm FD-SOI

Comparison of Shared and Private L1 Data Memories for an Emb...

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IEEE International Symposium on Embedded Multicore Socs (MCSoC)

作者： Gregor Sievers Julian Daberkow Johannes Ax Martin Flasskamp Wayne Kelly Thorsten Jungeblut Mario Porrmann Ulrich Rückert Cognitronics and Sensor Systems Group CITEC Bielefeld University Bielefeld Germany Science and Engineering Faculty Queensland University of Technology Brisbane Australia

Tightly coupling CPUs within clusters allows for low latency, high bandwidth communication in MPSoCs. Our CoreVA-MPSoC integrates multiple clusters using an on-chip network. In this work we introduce a shared L1 data memory that can be accessed by all CPUs of a cluster with low latency. A Mesh-of-Trees (MoT) and a crossbar as topology for the shared memory interconnect are presented. A cluster that integrates the shared L1 memory is compared with an architecture that features an AXI interconnect and a local L1 data memory for each CPU. In addition, we consider an architecture that integrates both. We present implementation results using a 28nm FD-SOI standard cell technology. The shared L1 memory shows similar area results compared to the local memory architecture. Place and route results of a cluster with 8 CPUs, 128kB local-and 128kB shared L1 data memory divided into 16 memory banks show a frequency of 728MHz and an area of 1.77mm2. To map programs to the different CPU cluster configurations a compiler for streaming applications is used. An architecture with both local and shared L1 data memory and 4 memory banks shows best performance results in combination with a high resource efficiency.

关键词： Clocks Memory management Central Processing Unit Standards Routing Topology

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Data centres for IoT applications: The M2DC approach (Invited paper)

Data centres for IoT applications: The M2DC approach (Invite...

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International Conference on Embedded Computer systems: Architectures, Modeling and Simulation (IC-SAMOS)

作者： Michal Kierzynka Ariel Oleksiak Giovanni Agosta Carlo Brandolese William Fornaciari Gerardo Pelosi Micha vor dem Berge Wolfgang Christmann Stefan Krupop Mariano Cecowski Robert Plestenjak Justin Cinkelj Mario Porrmann Jens Hagemeyer René Griessl Meysam Peykanu Lennart Tigges Loïc Cudennec Thierry Goubier Jean-Marc Philippe Sven Rosinger Daniel Schlitt Christian Pieper Chris Adeniyi-Jones Udo Janssen Luca Ceva Poznan Supercomputing and Networking Center Poznan Poland DEIB – Politecnico di Milano Milano Italy christmann informationstechnik + medien GmbH & Co. KG Ilsede Germany XLAB d.o.o. Ljubljana Slovenia Cognitronics and Sensor Systems Group CITEC Bielefeld University Germany CEA LIST OFFIS e. V. – Institute for Information Technology ARM Ltd. Cambridge UK CEWE Stiftung & Co. KGaA

The Modular Microserver DataCentre (M2DC) project investigates, develops and demonstrates a modular, highly-efficient, cost-optimized server architecture composed of heterogeneous micro server computing resources, being able to be tailored to meet requirements from various application domains, including the Internet of Things. M2DC is built on three main pillars: a flexible server architecture that can be easily customised, maintained and updated; advanced management strategies and system efficiency enhancements (SEE); well-defined interfaces to surrounding software data centre ecosystem.

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Data centres for IoT applications: The M2DC approach (Invited paper) 16

Data centres for IoT applications: The M2DC approach (Invite...

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16th International Conference on Embedded Computer systems: Architectures, Modeling and Simulation, SAMOS 2016

作者： Oleksiak, Michal Kierzynka Ariel Agosta, Giovanni Brandolese, Carlo Fornaciari, William Pelosi, Gerardo Vor Dem Berge, Micha Christmann, Wolfgang Krupop, Stefan Cecowski, Mariano Plestenjak, Robert Cinkelj, Justin Porrmann, Mario Hagemeyer, Jens Griessl, Rene Peykanu, Meysam Tigges, Lennart Cudennec, Loic Goubier, Thierry Philippe, Jean-Marc Rosinger, Sven Schlitt, Daniel Pieper, Christian Adeniyi-Jones, Chris Janssen, Udo Ceva, Luca Poznan Supercomputing and Networking Center ul. Noskowskiego 10 Poznan61-704 Poland DEIB - Politecnico di Milano Piazza Leonardo da Vinci 32 Milano Italy Christmann Informationstechnik + Medien GmbH and Co. KG Ilseder Huette 10c Ilsede31241 Germany XLAB D.o.o. Pot za Brdom 100 Ljubljana1000 Slovenia Cognitronics and Sensor Systems Group CITEC Bielefeld University Germany CEA LIST PC 172 Gif-sur-Yvette Cedex91191 France OFFIS E.V. - Institute for Information Technology Germany ARM Ltd. CPC-1 Capital Park Fulbourn CambridgeCB21 5XE United Kingdom CEWE Stiftung and Co. KGaA Germany Vodafone Telematics United Kingdom

ISBN: (纸本)9781509030767

The Modular Microserver DataCentre (M2DC) project investigates, develops and demonstrates a modular, highly-efficient, cost-optimized server architecture composed of heterogeneous micro server computing resources, being able to be tailored to meet requirements from various application domains, including the Internet of Things. M2DC is built on three main pillars: a flexible server architecture that can be easily customised, maintained and updated;advanced management strategies and system efficiency enhancements (SEE);well-defined interfaces to surrounding software data centre ecosystem. © 2016 IEEE.

关键词： Internet of things

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Identification of athletes during walking and jogging based on gait and electrocardiographic patterns

Communications in Computer and Information Science

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Communications in Computer and Information Science 2014年 452卷 240-257页

作者： Christ, Peter Rückert, Ulrich Cognitronics and Sensor Systems Group CITEC Bielefeld University Universitätsstr. 21-23 Bielefeld33615 Germany

ISBN: (纸本)9783662444849

We propose a biometric method for identifying athletes based on information extracted from the gait style and the electrocardiographic (ECG) waveform. The required signals are recorded within a non-clinical acquisition setup using a wireless body sensor attached to a chest strap with integrated textile electrodes. Our method combines both sources of information to allow identification despite severe intra-subjects variations in the gait patterns (walking and jogging) and motion related artefacts in the ECG patterns. For identification we use features extracted in time and frequency domain and a standard classifier. Within a treadmill experiment with 22 subjects we obtained an accuracy of 98.1% for velocities from 3 to 9 km/h. On a second data set consisting of 9 subjects and two sessions of recording, our method achieved 93.8% despite variations in the patterns due to reapplying the body sensor and an increased velocity (up to 11 km/h). © Springer-Verlag Berlin Heidelberg 2014.

关键词： Pattern recognition

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A respiration sensor for a chest-strap based wireless body sensor

A respiration sensor for a chest-strap based wireless body s...

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IEEE sensorS

作者： Marc Hesse Peter Christ Timm Hörmann Ulrich Rückert Cognitronics and Sensor Systems Group CITEC Bielefeld University Bielefeld

In this paper we present a respiration sensor suitable for an integration into a wireless body sensor worn around the chest. The thorax expansion and contraction during in- and exhalation is captured using a force-sensing resistor. Based on the captured thoracic movements, the breaths are determined with a peak detection algorithm. For evaluation, a treadmill experiment with five subjects was conducted using an ergospirometry system as a reference. Overall, an average deviation of -0.32±0.68 min -1 in the respiration rate between the ergospirometry and our sensor was observed. In general, the captured thoracic movements showed breaths as distinctive oscillations, but in some cases a non-optimal pressure transfer between thorax and sensor was observed. Therefore, a mechanical housing mechanism was developed. A comparison of our construction with a respiratory inductance plethysmography (RIP)-based sensor shows a close relationship with the captured thoracic movements during normal and deep respiration.

关键词： Resistors Temperature measurement Wireless sensor networks Wireless communication Biomedical monitoring Plethysmography Accelerometers

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