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International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information technology

作者： Sekson Timakul Somsak Choochuay College of Data Storage Technology and Applications King Mongkut's Institute of Technology Ladkrabang Bangkok 10520 Thailand Faculty of Engineering King Mongkut's Institute of Technology Ladkrabang Bangkok 10520 Thailand

ISBN: (纸本)9781479905461

In LDPC code design, the structure of code's parity check matrix can be very crucial to code performance. In this paper, we have investigated a simple designed parity check matrix when the code is applied to a PMR channel of a storage system. Belief propagation algorithm and min-sum algorithm are two major decoding algorithms used to benchmarked the code's merits. Additive white Gaussian noise channel (AWGN) and perpendicular magnetic recording (PMR) channel with SISO equalizer in PR2 target are the conditions of our investigation. The LDPC code itself is a modified array type. Its construction fairly simple compared to normal array and quasi-cyclic code. We used two decision variables to define the permutation matrix. A method proposed by Tanner's *** had been adapted to the modified array code. The decoders have been tested for 5 and 20. iterations. SNR versus BER and BLER were measured.

关键词： Error correction coding LDPC codes min-sum decoding iterative decoding magnetic recording

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Liquid Sensing: Spoof Plasmon Surfaces: A Novel Platform for THz Sensing (Advanced Optical Materials 8/2013)

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Advanced Optical Materials 2013年第8期1卷 537-537页

作者： Ng, Binghao Wu, Jianfeng Hanham, Stephen M. Fernández-Domínguez, Antonio I. Klein, Norbert Liew, Yun Fook Breese, Mark B. H. Hong, Minghui Maier, Stefan A. Dept. of Physics Imperial College London London South Kensington United Kingdom Data Storage Institute Agency for Science Technology and Research 5 Engineering Drive 1 Singapore Center for Ion Beam Applications (CIBA) Dept. of Physics National University of Singapore 2 Science Drive 3 Singapore Dept. of Materials Imperial College London London South Kensington United Kingdom National Metrology Centre 1 Science Park Drive Singapore Dept. of Electrical and Computer Engineering National University of Singapore 4 Engineering Drive 3 Singapore

An Otto prism coupling setup with a spoof plasmon surface underneath is the centerpiece of work by S. A. Maier and co-workers, in which terahertz liquid sensing with figures-of-merit as high as 49 are demonstrated. On page 543, water molecules are shown to go onto the spoof plasmon surface, which consists of linear arrays of subwavelength grooves, tightly confining the spoof plasmons. The plasmons are sensitive to the refractive index of the dielectric filling the grooves, and phase jumps at spoof plasmon resonances provide the readout response. © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

关键词： Metamaterials Plasmonics Sensors Subwavelength materials THz

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A low-power CMOS RF power detector

A low-power CMOS RF power detector

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IEEE International Conference on Electronics, Circuits and Systems (ICECS)

作者： Siraporn Sakphrom Apinunt Thanachayanont Faculty of Engineering King Mongkut's Institute of Technology Ladkrabang Bangkok Thailand Faculty of Engineering and College of Data Storage Technology and Applications King Mongkut's Institute of Technology Ladkrabang Bangkok Thailand

This paper describes the design and implementation of a low-power wide dynamic range radio-frequency (RF) power detector in a standard 0.18-μm CMOS process. The proposed circuit includes a root-mean-square (RMS) power detector and a logarithmic amplifier. The RMS power detector exploits the nonlinear characteristic of MOSFET to realize the RMS conversion. A current-mirror active load is used in the RMS power detector to increase the RMS conversion gain. Since the output of the RMS power detector is a DC voltage, the following logarithmic amplifier does not require wide operating bandwidth, thus allowing simple circuit realization with minimum power dissipation. Simple differential amplifier is used to realize the limiting gain stage. Post-layout simulation results showed that the proposed circuit was able to detect input power from -70 dBm to -20 dBm with signal frequencies ranging from 0.5 GHz to 5 GHz, while dissipating only 0.9 mW under a 1.8-V power supply voltage.

关键词： Detectors Radio frequency Limiting Dynamic range CMOS integrated circuits MOSFET circuits Power dissipation

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Construction of quasi-cyclic LDPC codes form SFT structure and cyclic shift

Construction of quasi-cyclic LDPC codes form SFT structure a...

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19th IEEE International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2011

作者： Timakul, Sekson Choomchuay, Somsak College of Data Storage Technology and Applications King Mongkut's Institute of Technology Ladkrabang Bangkok 10520 Thailand Faculty of Engineering King Mongkut's Institute of Technology Ladkrabang Bangkok 10520 Thailand

ISBN: (纸本)9781457721663

This paper presents an alternative a method for designing a parity matrix of low density parity check codes. The proposed method can be viewed as a generalized version of Sridara-Fuja-Tanner (SFT) technique which is ideal for regular quasi cyclic code design. Upon the current investigation, the designed code has delivered a comparable BER-SNR performance when compared with that of more complicate designed matrix. The designed code offers similar performance when compared with Sridara-Fuja-Tanner code and Quadratic Congruences structure. In additions, the resulted matrix also has a desirable structure that it suits well the hardware implementation. © 2011 IEEE.

关键词： Satellite communication systems

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A simple algorithm for a high code rate LDPC parity matrix design

A simple algorithm for a high code rate LDPC parity matrix d...

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11th International Symposium on Communications and Information Technologies, ISCIT 2011

ISBN: (纸本)9781457712944

This paper presents a simple method in designing a parity matrix of low density parity check codes. According to its use the use of arithmetic sequence is ideal for high rate code with no existing of cycle 4. The design is applicable to array code, modified array code, and quasi cyclic code. Upon the investigation, the designed code has delivered a similar BER-SNR performance when compared with that of more complicate designed matrices. © 2011 IEEE.

关键词： Design

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A FPGA design of AES core architecture for portable hard disk

A FPGA design of AES core architecture for portable hard dis...

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International Joint Conference on Computer Science and Software Engineering

作者： Thongkhome, Khanob Thanavijitpun, Chalermwat Choomchuay, Somsak College of Data Storage Technology and Applications King Mongkut's Institute of Technology Ladkrabang Bangkok 10520 Thailand Dept. of Electronic Engineering Faculty of Engineering King Mongkut's Institute of Technology Ladkrabang Bangkok 10520 Thailand

ISBN: (纸本)9781457706875

This paper describes a high effective AES core hardware architecture for implementing it to encrypt/decrypt the data in portable hard disk drive system that apply to effectively in the terms of speed, scale size and power consumption to comply with minimum speed of 5 Gbps (USB3.0). We proposed the 128 bits data path of two different AES architectures design, Basic Iterative AES, which reuses the same hardware for all the ten iterations and, One Stage Sub Pipelined AES, with one stage of outer pipelining in the data blocks that both of them are purely 128 bits data path architecture that different from the previous public paper. The implementation result on the targeted FPGA, the basic iterative AES encryption can offer the throughput of 3.85 Gbps at 300 MHz and one stage sub pipelined AES can offer the throughput to increase the efficiency of 6.2 Gbps at 481 MHz clock speed. © 2011 IEEE.

关键词： Cryptography

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A simple algorithm for a high code rate LDPC parity matrix design

A simple algorithm for a high code rate LDPC parity matrix d...

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International Symposium on Communications and Information Technologies (ISCIT)

作者： Sekson Timakul Somsak Choomchuay College of Data Storage Technology and Applications King MongkutGÇƒs Institute of Technology Ladkrabang Bangkok Thailand Faculty of Engineering King MongkutGÇƒs Institute of Technology Ladkrabang Bangkok Thailand

关键词： Parity check codes Arrays Indexes Sparse matrices Encoding Memory Facsimile

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Construction of quasi-cyclic LDPC codes form SFT structure and cyclic shift

Construction of quasi-cyclic LDPC codes form SFT structure a...

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IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)

作者： Sekson Timakul Somsak Choomchuay College of Data Storage Technology and Applications King Mongkut's Institute of Technology Ladkrabang Bangkok Thailand Faculty of Engineering King Mongkut's Institute of Technology Ladkrabang Bangkok Thailand

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A FPGA design of AES core architecture for portable hard disk

A FPGA design of AES core architecture for portable hard dis...

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International Joint Conference on Computer Science and Software Engineering (JCSSE)

作者： Khanob Thongkhome Chalermwat Thanavijitpun Somsak Choomchuay College of Data Storage Technology and Applications King Mongkut's Institute of Technology Ladkrabang Bangkok Thailand Department of Electronic Engineering Faculty of Engineering King Mongkut's Institute of Technology Ladkrabang Bangkok Thailand

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An overlapping Min-Sum LDPC decoder for IEEE 802.11n

An overlapping Min-Sum LDPC decoder for IEEE 802.11n

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18th International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2010

作者： Timakul, Sekson Tanyanon, Itsara Choomchuay, Somsak College of Data Storage Technology and Applications King Mongkut's Institute of Technology Ladkrabang Bangkok 10520 Thailand Faculty of Engineering King Mongkut's Institute of Technology Ladkrabang Bangkok 10520 Thailand

ISBN: (纸本)9781424473717

This paper presents overlapping techniques designed for a compact hardware LDPC decoder with MS algorithm. The design is applicable to IEEE 802.11n standard. We elaborate how to reduce hardware and cycle time between row and column operation. The hardware utilization can be better enhanced and 16-40% cycle time reduction compared to a non-overlapping decoder can be achieved. © 2010 IEEE.

关键词： Decoding

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