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A design of parity check matrix for irregular LDPC codes

A design of parity check matrix for irregular LDPC codes

引用

2009 9th International Symposium on Communications and Information technology, ISCIT 2009

作者： Prasartkaew, Chutima Choomchuay, Somsak College of Data Storage Technology and Applications King Mongkut's Institute of Technology Ladkrabang BKK Thailand Faculty of Engineering King Mongkut's Institute of Technology Ladkrabang BKK 10520 Thailand

This paper outlines a work on a design of parity check matrix for Irregular LDPC codes. The design is based on the adjustment of the modified array LDPC codes and interleave-modified array LDPC codes. The code rate of... 详细信息

ISBN: (纸本)9781424445219

关键词： Matrix algebra

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An overlapping Min-Sum LDPC decoder for IEEE 802.11n

An overlapping Min-Sum LDPC decoder for IEEE 802.11n

引用

18th International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2010

作者： Timakul, Sekson Tanyanon, Itsara Choomchuay, Somsak College of Data Storage Technology and Applications King Mongkut's Institute of Technology Ladkrabang Bangkok 10520 Thailand Faculty of Engineering King Mongkut's Institute of Technology Ladkrabang Bangkok 10520 Thailand

ISBN: (纸本)9781424473717

This paper presents overlapping techniques designed for a compact hardware LDPC decoder with MS algorithm. The design is applicable to IEEE 802.11n standard. We elaborate how to reduce hardware and cycle time between row and column operation. The hardware utilization can be better enhanced and 16-40% cycle time reduction compared to a non-overlapping decoder can be achieved. © 2010 IEEE.

关键词： Decoding

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A design of nonprime block irregular LDPC codes via CRT

A design of nonprime block irregular LDPC codes via CRT

引用

2010 10th International Symposium on Communications and Information Technologies, ISCIT 2010

作者： Chusin, Chalit Prasartkaew, Chutima Timakul, Sekson Choomchuay, Somsak College of Data Storage Technology and Applications King Mongkut's Institute of Technology Ladkrabang BKK 10520 Thailand Faculty of Engineering King Mongkut's Institute of Technology Ladkrabang BKK 10520 Thailand

ISBN: (纸本)9781424470105

This paper presents a new design of irregular LDPC codes that supports arbitrary block length. We propose the efficient construction method when nonprime size sub-matrices are used. The problem where GCD(L1,L 2) that left unsolved has been tackled. We also consider the case GCD(L1,L2)=1 but L1 or L2 is a nonprime number. The results show that our designed codes have superior performance compared to MAC. The resulted codes still hold the attractive properties of LDPC codes. The performances of interleaved codes are higher than noninterleaved codes and it goes higher as SNR is increased. ©2010 IEEE.

关键词： Codes (symbols)

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Construction of quasi-cyclic LDPC codes form SFT structure and cyclic shift

Construction of quasi-cyclic LDPC codes form SFT structure a...

引用

19th IEEE International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2011

作者： Timakul, Sekson Choomchuay, Somsak College of Data Storage Technology and Applications King Mongkut's Institute of Technology Ladkrabang Bangkok 10520 Thailand Faculty of Engineering King Mongkut's Institute of Technology Ladkrabang Bangkok 10520 Thailand

ISBN: (纸本)9781457721663

This paper presents an alternative a method for designing a parity matrix of low density parity check codes. The proposed method can be viewed as a generalized version of Sridara-Fuja-Tanner (SFT) technique which is ideal for regular quasi cyclic code design. Upon the current investigation, the designed code has delivered a comparable BER-SNR performance when compared with that of more complicate designed matrix. The designed code offers similar performance when compared with Sridara-Fuja-Tanner code and Quadratic Congruences structure. In additions, the resulted matrix also has a desirable structure that it suits well the hardware implementation. © 2011 IEEE.

关键词： Satellite communication systems

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A simple algorithm for a high code rate LDPC parity matrix design

A simple algorithm for a high code rate LDPC parity matrix d...

引用

11th International Symposium on Communications and Information Technologies, ISCIT 2011

ISBN: (纸本)9781457712944

This paper presents a simple method in designing a parity matrix of low density parity check codes. According to its use the use of arithmetic sequence is ideal for high rate code with no existing of cycle 4. The design is applicable to array code, modified array code, and quasi cyclic code. Upon the investigation, the designed code has delivered a similar BER-SNR performance when compared with that of more complicate designed matrices. © 2011 IEEE.

关键词： Design

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A FPGA design of AES core architecture for portable hard disk

A FPGA design of AES core architecture for portable hard dis...

引用

International Joint Conference on Computer Science and Software Engineering

作者： Thongkhome, Khanob Thanavijitpun, Chalermwat Choomchuay, Somsak College of Data Storage Technology and Applications King Mongkut's Institute of Technology Ladkrabang Bangkok 10520 Thailand Dept. of Electronic Engineering Faculty of Engineering King Mongkut's Institute of Technology Ladkrabang Bangkok 10520 Thailand

ISBN: (纸本)9781457706875

This paper describes a high effective AES core hardware architecture for implementing it to encrypt/decrypt the data in portable hard disk drive system that apply to effectively in the terms of speed, scale size and power consumption to comply with minimum speed of 5 Gbps (USB3.0). We proposed the 128 bits data path of two different AES architectures design, Basic Iterative AES, which reuses the same hardware for all the ten iterations and, One Stage Sub Pipelined AES, with one stage of outer pipelining in the data blocks that both of them are purely 128 bits data path architecture that different from the previous public paper. The implementation result on the targeted FPGA, the basic iterative AES encryption can offer the throughput of 3.85 Gbps at 300 MHz and one stage sub pipelined AES can offer the throughput to increase the efficiency of 6.2 Gbps at 481 MHz clock speed. © 2011 IEEE.

关键词： Cryptography

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A wideband CMOS variable gain amplifier using active feedback and resistive compensation

A wideband CMOS variable gain amplifier using active feedbac...

引用

2009 9th International Symposium on Communications and Information technology, ISCIT 2009

作者： Sakprom, S. Thanachayanont, A. Khumsat, P. Faculty of Engineering King Mongkut's Institute of Technology Ladkrabang Bangkok 10520 Thailand College of Data Storage Technology and Applications King Mongkut's Institute of Technology Ladkrabang Chalongkrung Road Bangkok 10520 Thailand Department of Electrical Engineering Faculty of Engineering Prince of Songkla University Hat-Yai 90112 Thailand

ISBN: (纸本)9781424445219

This paper describes the design and realization of a low power low voltage variable gain amplifier based on an active feedback topology. The proposed amplifier employs the active feedback topology with resistive compensation technique to enhance the operating bandwidth. Simulation results using a 0.18um CMOS technology show that the proposed amplifier can achieve 3.3 GHz bandwidth and 56 dB gain, while drawing 24 mA from a single 1.8-V power supply voltage. ©2009 IEEE.

关键词： Variable gain amplifiers

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A parity check matrix design for Irregular LDPC codes with 2K block length

A parity check matrix design for Irregular LDPC codes with 2...

引用

IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)

作者： Chutima Prasartkaew Somsak Choomchuay College of Data Storage Technology and Applications King Mongkut's Institute of Technology Ladkrabang Bangkok Thailand Faculty of Engineering King Mongkut's Institute of Technology Ladkrabang Bangkok Thailand

This paper outlines the work on another design of a parity check matrix for Irregular LDPC codes. The design is based on the pattern of Modified Array and Interleaved Modified Array LDPC codes. The application of matrix transposition Quasi-cyclic shifting has resulted in the reduction of 1's. The designed matrix is suitable for codes with short and medium block lengths. The code rate of 0.56 at the BER of 10 -4 is obtained.

关键词： Parity check codes Bit error rate Memory Block codes Signal design Error correction codes Signal to noise ratio Decoding Signal processing Educational institutions

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A simple algorithm for a high code rate LDPC parity matrix design

A simple algorithm for a high code rate LDPC parity matrix d...

引用

International Symposium on Communications and Information Technologies (ISCIT)

作者： Sekson Timakul Somsak Choomchuay College of Data Storage Technology and Applications King MongkutGÇƒs Institute of Technology Ladkrabang Bangkok Thailand Faculty of Engineering King MongkutGÇƒs Institute of Technology Ladkrabang Bangkok Thailand

关键词： Parity check codes Arrays Indexes Sparse matrices Encoding Memory Facsimile

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Construction of quasi-cyclic LDPC codes form SFT structure and cyclic shift

Construction of quasi-cyclic LDPC codes form SFT structure a...

引用

IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)

作者： Sekson Timakul Somsak Choomchuay College of Data Storage Technology and Applications King Mongkut's Institute of Technology Ladkrabang Bangkok Thailand Faculty of Engineering King Mongkut's Institute of Technology Ladkrabang Bangkok Thailand

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