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OpenMP directive extension for BlackFin 561 dual core processor

OpenMP directive extension for BlackFin 561 dual core proces...

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6th IEEE International Conference on Computer and Information Technology, CIT 2006

作者： Seo, Hee Kim, Seon Wook Compilers and Embedded Systems Laboratory Department of Electronics and Computer Engineering Korea University Seoul Korea Republic of

ISBN: (纸本)076952687X

Many researchers and vendors are exploiting the increasing number of transistors to build chip multiprocessors (CMPs) by partitioning a chip into multiple simple ILP cores. As in traditional multiprocessors, CMPs extract thread-level parallelism (TLP) from programs by running multiple independent program segments, i.e., threads, in parallel. Currently CMPs are used widely in high performance servers, and even in embedded systems. In this paper, we present an extension of the OpenMP shared directive for performance optimization on BlackFin 561 (ADSP-BF561) dual core processors. In order to support memory consistency between multiple cores, many architectures have been proposed. On the dual core processor, like ADSP-BF561, each core has its own private LI cache, and a shared L2 cache. In order to execute multithreaded parallel programs, we need to consider carefully where to allocate shared variables on targeted memory architecture. We could improve the speedup by up to 107% and reduce the energy consumption by up to 108% in our measured benchmarks with respect to no use of our extension. © 2006 IEEE.

关键词： Program processors

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OpenMP Directive Extension for BlackFin 561 Dual Core Processor

OpenMP Directive Extension for BlackFin 561 Dual Core Proces...

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International Conference on Computer and Information Technology (CIT)

作者： Hee Seo Seon Wook Kim Compilers and Embedded Systems Laboratory Department of Electronics and Computer Engineering Korea University of Technology and Education Seoul South Korea

Many researchers and vendors are exploiting the increasing number of transistors to build chip multiprocessors (CMPs) by partitioning a chip into multiple simple ILP cores. As in traditional multiprocessors, CMPs extract thread-level parallelism (TLP) from programs by running multiple independent program segments, i.e., threads, in parallel. Currently CMPs are used widely in high performance servers, and even in embedded systems. In this paper, we present an extension of the OpenMP shared directive for performance optimization on BlackFin 561 (ADSPBF561) dual core processors. In order to support memory consistency between multiple cores, many architectures have been proposed. On the dual core processor, like ADSP-BF561, each core has its own private L1 cache, and a shared L2 cache. In order to execute multithreaded parallel programs, we need to consider carefully where to allocate shared variables on targeted memory architecture. We could improve the speedup by up to 107% and reduce the energy consumption by up to 108% in our measured benchmarks with respect to no use of our extension.

关键词： embedded system Yarn Energy consumption Surface-mount technology Parallel processing Energy measurement Velocity measurement Memory management Prefetching Laboratories

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The Effect of Basic Resins on Conductivity Properties of the Polyethylene and Carborundum Composite

The Effect of Basic Resins on Conductivity Properties of the...

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International Conference on Properties and Applications of Properties and Applications of Dielectric Materials

作者： Wen Min Guo Bao Zhong Han Huan Zheng Zhong Hua Li College of Electrical and Electronic Engineering Harbin University of Science and Technology Harbin China Architectures and Compilers for Embedded Systems (ACES) Laboratory University of California Irvine CA USA Harbin University of Science and Technology Harbin Heilongjiang CN

Polymer composite, compared with conventional sing-phase insulation, can have improved dielectric properties. The field dependent conductivity inorganic filler in polymer can make the polymer composite into non-linear insulating materials used to improve the distribution of electric field. In this study, three kinds of polyethylene (LDPE, LLDPE and HDPE) were take as basic resins filled with carborundum (SiC) powder, and the field dependent conductivity properties of these composites were investigated through experiment at different temperatures

关键词： Resins Conductivity Polyethylene Polymers Dielectrics and electrical insulation Plastic insulation Composite materials Conducting materials Dielectric materials Inorganic materials

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Functional validation of programmable architectures

Functional validation of programmable architectures

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Euromicro Symposium on Digital System Design

作者： P. Mishra N. Dutt Architectures and Compilers for Embedded Systems (ACES) Laboratory Center for Embedded Computer Systems University of California Irvine USA

Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current system-on-chip design methodology. A critical challenge in validation of such systems is the lack of a golden reference model. Traditional validation techniques employ different reference models depending on the abstraction level and verification task (e.g., functional simulation or property checking), resulting in potential inconsistencies between multiple reference models. This paper presents a validation methodology that uses an architecture description language (ADL) based specification as a golden reference model for validation of programmable architectures, and generation of executable models such as simulators and hardware prototypes. We present a validation framework that uses the generated hardware as a reference model to verify the hand-written implementation using a combination of symbolic simulation and equivalence checking. We also present functional coverage based test generation techniques for validation of pipelined processor architectures. Finally, the generated simulator and hardware models are also used for early exploration of programmable architectures.

关键词： Pervasive computing Computer architecture embedded computing Computer bugs Hardware Personal digital assistants Coprocessors Computational modeling Handheld computers North America

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Synthesis-driven exploration of pipelined embedded processors

Synthesis-driven exploration of pipelined embedded processor...

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International Conference on VLSI Design

作者： P. Mishra A. Kejariwal N. Dutt Architectures and Compilers for Embedded Systems (ACES) Laboratory Center for Embedded Computer Systems University of California Irvine CA USA

Recent advances on language based software toolkit generation enables performance driven exploration of embedded systems by exploiting the application behavior. There is a need for an automatic generation of hardware to determine the required silicon area, clock frequency, and power consumption of the candidate architectures. In this paper, we present a language based exploration framework that automatically generates synthesizable RTL models for pipelined processors. Our framework allows varied micro-architectural modifications, such as, addition of pipeline stages, pipeline paths, opcodes and new functional units. The generated RTL is synthesized to determine the area, power, and clock frequency of the modified architectures. Our exploration results demonstrate the power of reuse in composing heterogeneous architectures using functional abstraction primitives allowing for a reduction in the time for specification and exploration by at least an order of magnitude.

关键词： Power generation Clocks Pipelines embedded software Software performance Software tools Distributed power generation embedded system Application software Hardware

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Instruction set compiled simulation: a technique for fast and flexible instruction set simulation 03

Instruction set compiled simulation: a technique for fast an...

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Design Automation Conference

作者： M. Reshadi P. Mishra N. Dutt Architectures and Compilers for Embedded Systems Laboratory Center for Embedded Computer Systems University of California Irvine CA USA

ISBN: (纸本)9781581136883

Instruction set simulators are critical tools for the exploration and validation of new programmable architectures. Due to increasing complexity of the architectures and time-to-market pressure, performance is the most important feature of an instruction-set simulator. Interpretive simulators are flexible but slow, whereas compiled simulators deliver speed at the cost of flexibility. This paper presents a novel technique for generation of fast instruction-set simulators that combines the benefit of both compiled and interpretive simulation. We achieve fast instruction accurate simulation through two mechanisms. First, we move the time-consuming decoding process from run-time to compile time while maintaining the flexibility of the interpretive simulation. Second, we use a novel instruction abstraction technique to generate aggressively optimized decoded instructions that further improves simulation performance. Our instruction set compiled simulation (IS-CS) technique delivers up to 40% performance improvement over the best known published result that has the flexibility of the interpretive simulation. We illustrate the applicability of the IS-CS technique using the ARM7 embedded processor.

关键词： Decoding Runtime Computational modeling Computer simulation Computer architecture embedded system Permission Predictive models Switches Program processors

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Rapid exploration of pipelined processors through automatic generation of synthesizable RTL models

Rapid exploration of pipelined processors through automatic ...

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International Workshop on Rapid System Prototyping (RSP)

作者： P. Mishra A. Kejariwal N. Dutt Architectures and Compilers for Embedded Systems (ACES) Laboratory Center for Embedded Computer Systems University of California Irvine CA USA

As embedded systems continue to face increasingly higher performance requirements, deeply pipelined processor architectures are being employed to meet desired system performance. System architects critically need modeling techniques to rapidly explore and evaluate candidate architectures based on area, power, and performance constraints. We present an exploration framework for pipelined processors. We use the EXPRESSION Architecture Description Language (ADL) to capture a wide spectrum of processor architectures. The ADL has been used to enable performance driven exploration by generating a software toolkit from the ADL specification. In this paper, we present a functional abstraction technique to automatically generate synthesizable RTL from the ADL specification. Automatic generation of RTL enables rapid exploration of candidate architectures under given design constraints such as area, clock frequency, power, and performance. Our exploration results demonstrate the power of reuse in composing heterogeneous architectures using functional abstraction primitives allowing for a reduction in the time for specification and exploration by at least an order of magnitude.

关键词： Computer architecture Power system modeling embedded system System performance Architecture description languages Software performance Software tools Power generation Clocks Frequency

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A methodology for validation of microprocessors using equivalence checking

A methodology for validation of microprocessors using equiva...

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International Workshop on Microprocessor Test and Verification (MTV)

作者： P. Mishra N. Dutt Architectures and Compilers for Embedded Systems (ACES) Laboratory Center for Embedded Computer Systems University of California Irvine CA USA

As embedded systems continue to face increasingly higher performance requirements, deeply pipelined processor architectures are being employed to meet desired system performance. Validation of such processor architectures is one of the most complex and expensive tasks in the current systems-on-chip design process. A significant bottleneck in the validation of such systems is the lack of a golden reference model. We present an architecture description language (ADL) driven methodology for generating golden reference model. We use EXPRESSION ADL to capture the structure and behavior of the processor. The synthesizable register transfer language (RTL) description of the architecture is generated from the ADL specification. The generated RTL description is used as a golden reference model for verifying the correctness of the implementation using equivalence checking. We applied our methodology on a RISC DLX architecture to demonstrate the usefulness of our approach.

关键词： Microprocessors Computer architecture embedded system Hardware design languages Process design Space exploration Feedback Architecture description languages Reduced instruction set computing Application software

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New directions in compiler technology for embedded systems

New directions in compiler technology for embedded systems

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Asia and South Pacific Design Automation Conference

作者： N. Dutt A. Nicolau H. Tomiyama A. Halambi Architectures and Compilers for Embedded Systems Laboratory Center for Embedded Computer Systems University of California Irvine CA USA

ISBN: (纸本)0780366336

Traditionally, compiler technology has focused on the generation of code with the goal of improving performance for a variety of applications running on general-purpose processor architectures. In the embedded system space, compiler technology is faced with many new challenges, including: code generation for specialized architectural features, requiring a highly flexible degree of retargetability; memory-aware code generation that exploits the timing and structure of the embedded system's memory organization; optimizing software to meet both real-time and performance constraints; energy- and power-aware software generation, both from the context of energy minimization, as well as power modulation; code size minimization for memory-constrained embedded systems; coarse-grain transformations for tightly-coupled, memory-constrained multi-processor architectures; and interaction with the operating system for active management of embedded system resources. This paper discusses new directions for compiler technology, surveys some of the current research efforts and illustrates proposed solutions to selected issues.

关键词： embedded system Space technology Distributed power generation Power generation Computer architecture embedded software Software performance Application software Timing Memory management

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Processor-memory co-exploration driven by a Memory-Aware Architecture Description Language

Processor-memory co-exploration driven by a Memory-Aware Arc...

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International Conference on VLSI Design

作者： P. Mishra P. Grun N. Dutt A. Nicolau Architectures and Compilers for Embedded Systems (ACES) Laboratory Center for Embedded Computer Systems University of California Irvine CA USA

ISBN: (纸本)0769508316

Memory represents a major bottleneck in modern embedded systems. Traditionally, memory organizations for programmable systems assumed a fixed cache hierarchy. With the widening processor-memory gap, more aggressive memory technologies and organizations have appeared, allowing customization of a heterogeneous memory architecture tuned for the application. However, such a processor-memory co-exploration approach critically needs the ability to explicitly capture heterogeneous memory architectures. We present in this paper a language-based approach to explicitly capture the memory subsystem configuration, and perform exploration of the memory architecture to trade-off cost versus performance. We present a set of experiments using our Memory-Aware Architectural Description Language to drive the exploration of the memory subsystem for the TIC6211 processor architecture, demonstrating a range of cost and performance attributes.

关键词： Architecture description languages Memory architecture Random access memory Costs Computer architecture Software tools embedded system Design optimization Laboratories embedded computing

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