检索结果-内蒙古大学图书馆

IEEE International Test Conference

作者： T.M. Sarfert R. Markgraf E. Trischler M.H. Schulz Department E STE 44 Siemens AG Munich Germany Institute of Computer Aided Design Department of Electrical Engineering Technical University Munich Munich Germany

It is demonstrated that the exploitation of high-level primitives (HLPs) and, in particular, of the knowledge concerning their function in ATPG (automatic test pattern generation) leads to significant improvements in implication, unique sensitization, and multiple backtrace. Motivated by this observation and the necessity of covering all faults inside HLPs, the authors present the extension of the ATPG system SOCRATES to hierarchical test pattern generation, which is based upon HLPs and the strategy of dynamically expanding the HLPs to their gate-level realization, at most one at a time. Experimental results have substantiated that the proposed approach performs significantly better in terms of CPU time, elapsed time, fault coverage, and memory requirements than a gate-level ATPG algorithm. It is expected that the extended SOCRATES algorithm will be capable of coping with circuits consisting of 100000 gates and more within reasonable times, even in a workstation environment.< >

关键词： Test pattern generators Circuit faults Multiplexing Circuit testing Combinational circuits design methodology Logic arrays Very large scale integration Complexity theory Transistors

来源：评论

学校读者我要写书评

暂无评论

Hierarchical fault simulation in combinational circuits

Hierarchical fault simulation in combinational circuits

引用

European Test Conference

作者： M.H. Schulz B.H. Seiss F. Brglez Institute of Computer Aided Design Department of Electrical Engineering Technical University Munich Munich Germany Bell-Northern Research Inc. NC USA

A method is presented for speeding up fault simulation in combinational circuits by taking advantage of a hierarchical circuit description. The parallel-pattern single-fault-propagation technique is combined with the concept of fanout-free regions, and this approach is then extended to exploit hierarchy. A number of illustrative experiments demonstrate the efficiency of the proposed method and substantiate the gains in simulation speed. Besides the savings in CPU time, the method results in a significant reduction in the memory requirements for creating and maintaining the computational model of the circuit to be simulated.< >

关键词： Circuit faults Circuit simulation Combinational circuits computational modeling Very large scale integration Circuit testing Costs Automatic test pattern generation Artificial intelligence Acceleration

来源：评论

学校读者我要写书评

暂无评论

ESTIMATION OF STRUCTURAL SERVICE LIFE OF SHIPS

引用

NAVAL ENGINEERS JOURNAL 1989年第3期101卷 156-166页

作者： AYYUB, BM WHITE, GJ PURCELL, ES P.E. Bilal M. Ayyub:is currently an associate professor of civil engineering at the University of Maryland. He received his B.S. degree in civil engineering from the University of Kuwait in 1980. He completed both his M.S. (1981) and Ph.D. (1983) in civil engineering at the Georgia Institute of Technology. Dr. Ayyub has an extensive background in risk-based analysis and design simulation and construction engineering. He is engaged in research work involving structural reliability bridges marine structures and mathematical modeling using the theories of probability statistics and fuzzy sets. His research work is sponsored by the National Transportation Safety Board the National Science Foundation the U.S. Coast Guard the State of Maryland and the University of Maryland. Dr. Ayyub is a member of ASNE the American Society of Civil Engineers (ASCE) the American Concrete Institute (ACI) the Committee on Forensic Engineering of ASCE and the Committee on Structural Safety of ACI. He is the author of more than three dozen publications in national and international journals conference proceedings and reports. Dr. Ayyub received the ASNE “Jimmie” Hamilton Award for 1985 and the ASCE “Outstanding Research Oriented Paper” in the Journal of Water Resources Planning and Management for 1987. Gregory J. White:is an associate professor of naval architecture at the U.S. Naval Academy. He received his B.S. degree in engineering mechanics from Vanderbilt University in 1975 an M.E. degree in naval architecture from the University of California Berkeley in 1981 and a Ph.D. in civil engineering (structures) from the University of Maryland in 1986. Dr. White served on active duty with the U.S. Navy from 1975 to 1979 as a junior officer in the engineering and operations departments of Pacific Fleet destroyers. Prior to coming to the Naval Academy he worked at Mare Island Naval Shipyard in the scientific code and in the R&D division of Exxon International Company's Tanker Department. Dr. White is a lieutenant commande

A methodology for the structural life assessment of a ship's structure is suggested. The methodology is based on probabilistic analysis using reliability concepts and the statistics of extremes. In this approach, the estimation of structural life expectancy is based on selected failure modes. All possible failure modes of the ship must be investigated and the most likely paths to structural failure identified. For the purpose of illustration two failure modes are considered in this study. They are plate plastic deformation and fatigue cracking. Structural life based on these two failure modes is determined for an example vessel. The methodology determines the probability of failure of the ship's structural components according to the identified failure modes as a function of time. The results can be interpreted as the cumulative probability distribution function (CDF) of structural life. Due to the unknown level of statistical correlation between failure modes, limits or bounds on the CDF of the structural life are established. The limits correspond to the extreme cases of fully correlated and independent failure modes. The CDFs of structural life are determined for two inspection strategies; namely, inspection every year and inspection every two years with a warranty inspection at the end of the first year. The meaning of the results for the case investigated in this study is that, for example, given an inspection strategy of two years and a desired life of 15 years, there is a 72% chance that the vessel will not experience enough partial damage‘ in the failure modes identified to constitute reaching the “end of structural life” as defined.

关键词： Ships

来源：评论

学校读者我要写书评

暂无评论

HYDRODYNAMIC EVALUATION OF HULL FORMS WITH PODDED PROPULSORS

引用

NAVAL ENGINEERS JOURNAL 1989年第3期101卷 197-206页

作者： CHENG, BH DEAN, JS MILLER, RW CAVE, WL Bill H. Cheng:is a physical scientist in the Numerical Fluid Dynamics Branch Computation Mathematics and Logistics Department David Taylor Research Center (DTRC) Bethesda MD. Since joining DTRC in 1981 he has been the project leader for the XYZ Free Surface (XYZFS) Program. He received a B.S. in mechanical engineering from the National Taiwan University and a M.A.Sc. in mechanical engineering from the University of British Columbia and a S.M. degree in oceanography and meteorology from Harvard University. Mr. Cheng is a registered professional engineer in the Commonwealth of Virginia and a member of American Society of Mechanical Engineers and Sigma Xi. His experience in fluid dynamics has included theory experiments and computations. He has been the author and coauthor of numerous technical reports and papers. Janet S. Dean:is a mathematician in the Numerical Fluid Dynamics Branch DTRC. She attended the College of William and Mary and received her B.S. degree in mathematics from The George Washington University. Mrs. Dean assisted Charles Dawson in the development of the original XYZFS Program. She has worked on improving and extending the capabilities of XYZFS and on the application of supercomputers to fluid dynamics problems. Ronald W. Miller:is a mechanical engineer in the Numerical Fluid Dynamics Branch DTRC. He received his B.A. degree in mathematics from the University of Maryland—Baltimore County Campus in 1984 and his M.S. in ocean and marine engineering from The George Washington University in 1988. Mr. Miller is responsible for the preparation of hull geometry data used in ship hydrodynamic analysis computer codes and the graphical visualization of output from such codes. William L. Cave III:graduated from Stevens Institute of Technology in 1986 with a B.E. degree in ocean engineering. He is currently a naval architect in the Design Evaluation Branch Ship Hydromechanics Department DTRC. He has been involved with model testing and evaluation of the CV-41 FFG-7 class USNSHayesCG-47 class

A computational capability has been developed to predict and visualize the flow about podded propulsors appended to the 154-foot transom stern research vessel, R/V Athena . The computer generation of a complex geometric model for the hull and appendages is an important part of this new capability. The flow field is computed using a free surface potential flow method. The steady flow induced by the propulsor is simulated by an idealized propeller model (actuator disk). The upstream effects of an actuator disk are examined and results are compared to the case without an actuator disk. Computed results for the inflow to the propeller disk are presented as velocity vector plots and contour plots. Harmonic analyses are performed on the computed velocity components. The numerical results can be used in conjunction with experiments performed at DTRC to aid in the design of podded propulsors. These flow studies are used to examine the proper alignment of the pod/strut system with the aim of obtaining the optimal flow into the propeller. The combined numerical and experimental approach is shown to be an efficient way to evaluate complex hull forms with podded propulsors. This powerful design approach can be used for future Navy ship designs.

关键词： Ships

来源：评论

学校读者我要写书评

暂无评论

STATISTICAL CONTROL OF VLSI FABRICATION PROCESSES - A SOFTWARE SYSTEM

引用

IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING 1988年第2期1卷 72-82页

作者： SHYAMSUNDAR, CR MOZUMDER, PK STROJWAS, AJ SRC-CMU Center for Computer-Aided Design Department of Electrical and Computer Engineering Carnegie Mellon University Pittsburgh PA USA

For pt.I see ibid., vol.1, no.2, p.62-71, 1988. The algorithms used to implement the CMU-CAM statistical control system for VLSI integrated circuit fabrication are presented. The CMU-CAM system performs three major operations: modeling; quality control; and feed-forward control. In order to increase the efficiency of modeling and control, the problem is decomposed using statistical factorization techniques. Algorithms for process modeling and algorithms used in quality control and feed-forward control are described. The CMU-CAM system performs profit maximization through statistical process control. Its capabilities are illustrated by a number of computational examples.< >

关键词： Very large scale integration Fabrication Software systems Process control Control systems Software algorithms Quality control Feeds Clustering algorithms Software performance

来源：评论

学校读者我要写书评

暂无评论

STATISTICAL CONTROL OF VLSI FABRICATION PROCESSES - A FRAMEWORK

引用

IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING 1988年第2期1卷 62-71页

作者： MOZUMDER, PK SHYAMSUNDAR, CR STROJWAS, AJ SRC-CMU Center for Computer-Aided Design Department of Electrical and Computer Engineering Carnegie Mellon University Pittsburgh PA USA

A general framework for statistical control of VLSI (very large-scale integration) fabrication processes is given along with the architectural description of a software system that can be used for monitoring, diagnosis, and quality/quantity control of computer-aided integrated circuit manufacture. The task of process control is formulated as one of profit maximization, and the associated objective function and the constraints are developed for a number of manufacturing scenarios. The IC fabrication process is modeled as a stochastic system and the necessary conditions for efficient statistical control of VLSI fabrication processes are described.< >

关键词： Very large scale integration Fabrication Control systems Integrated circuit modeling Large scale integration Software systems computerized monitoring computer aided manufacturing Integrated circuit manufacture Process control

来源：评论

学校读者我要写书评

暂无评论

SOCRATES - A HIGHLY EFFICIENT AUTOMATIC TEST PATTERN GENERATION SYSTEM

引用

IEEE TRANSACTIONS ON computer-aided design OF INTEGRATED CIRCUITS AND SYSTEMS 1988年第1期7卷 126-137页

作者： SCHULZ, MH TRISCHLER, E SARFERT, TM Institute of Computer Aided Design Department of Electrical Engineering Technical University Munich Munich Germany Department E STE 4 CAD/CAT Siemens AG Munich Germany

An automatic test pattern generation system, SOCRATES, is presented. SOCRATES includes several novel concepts and techniques that significantly improve and accelerate the automatic test pattern generation process for combinational and scan-based circuits. Based on the FAN algorithm, improved implication, sensitization, and multiple backtrace procedures are described. The application of these techniques leads to a considerable reduction of the number of backtrackings and an earlier recognition of conflicts and redundancies. Several experiments using a set of combinational benchmark circuits demonstrate the efficiency of SOCRATES and its cost-effectiveness, even in a workstation environment.< >

关键词： Automatic test pattern generation Circuit testing Test pattern generators Circuit faults Automatic testing Costs Benchmark testing Workstations Very large scale integration design for testability

来源：评论

学校读者我要写书评

暂无评论

GORDIAN: a new global optimization/rectangle dissection method for cell placement

GORDIAN: a new global optimization/rectangle dissection meth...

引用

IEEE International Conference on computer-aided design

作者： J.M. Kleinhans G. Sigl F.M. Johannes Institute of Computer-Aided Design Department of Electrical Engineering Technical University Munich Munich Germany

A placement method for cell-based layout styles composed of alternating and interacting global optimization and partitioning phases is presented. In contrast to other methods using the divide-and-conquer paradigm, it maintains the simultaneous treatment of all cells during optimization over all levels of partitioning. In the global optimization phases, constrained quadratic optimization problems with unique global minima are solved. Their solutions induce the assignment of cells to regions during the partitioning phases. For general-cell circuits, a highly efficient exhaustive slicing procedure is applied to small subsets of cells. The designer may choose a configuration from a menu to meet his requirements on chip area, chip aspect ratio and wire length. Placements with high area utilization are obtained within short computation times. The method has been applied to general-cell and standard-cell circuits with up to 3000 cells and nets.< >

关键词： Optimization methods Constraint optimization Circuits Partitioning algorithms Iterative algorithms design optimization design automation Wire Very large scale integration

来源：评论

学校读者我要写书评

暂无评论

Advanced automatic test pattern generation and redundancy identification techniques

Advanced automatic test pattern generation and redundancy id...

引用

International Symposium on Fault-Tolerant Computing (FTCS)

作者： M.H. Schulz E. Auth Institute of Computer Aided Design Department of Electrical Engineering Technical University Munich Munich Germany

Based on the sophisticated strategies used in the automatic test pattern generation system SOCRATES, the authors present several concepts aiming at a further improvement and acceleration of the deterministic test pattern generation and redundancy identification process. In particular, they describe an improved implication procedure and an improved unique sensitization procedure. Both procedures significantly advance the deterministic test pattern generation and redundancy identification especially for those faults, for which it is difficult to generate a test pattern or to prove them to be redundant, respectively. As a result of the application of the proposed techniques, SOCRATES is capable of successfully generating a test pattern for all testable faults in a set of combinational benchmark circuits, and of identifying all redundant faults with less than 10 backtrackings.< >

关键词： Automatic test pattern generation Circuit faults Circuit testing Test pattern generators Redundancy Fault diagnosis Combinational circuits Life estimation Benchmark testing Very large scale integration

来源：评论

学校读者我要写书评

暂无评论

D/sup 3/FS: a demand driven deductive fault simulator

D/sup 3/FS: a demand driven deductive fault simulator

引用

IEEE International Test Conference

作者： S.P. Smith M.R. Mercer B. Underwood Computer Aided Design Program Microelectronics and Computer Technology Corporation Austin TX USA Department of Electrical and Computer Engineering University of Texas Austin Austin TX USA

A high-speed fault simulator is presented that combines demand-driven simulation techniques with a bit-encoded deductive fault simulation scheme. The simulator uses an efficient approach to the management of signal value and fault list structures intended to minimize disk thrashing during execution. Input cone analysis is used during preprocessing to identify gates with independent inputs so that optimized evaluation routines that include early cutoff can be used. Results are given for the demand-driven deductive fault simulator and contrasted with an earlier demand-driven parallel fault simulator.< >

关键词： Circuit faults computational modeling Circuit simulation computer simulation Circuit testing Automatic test pattern generation Microelectronics Vectors Automatic testing Sequential analysis

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：