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Orion: A Technique to Prune State Space Search Directions for Guidance-Based Formal Verification

Orion: A Technique to Prune State Space Search Directions fo...

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Asian Test Symposium (ATS)

作者： V.S. Vineesh Binod Kumar Rushikesh Shinde Akshay Jaiswal Harsh Bhargava Virendra Singh Computer Architecture and Dependable Systems Lab IIT Bombay Qualcomm India Private Limited Bengaluru

ISBN: (数字)9781728126951

ISBN: (纸本)9781728126968

Model checking of large designs is a challenging task because of different scalability issues. In this paper, we aim to utilize guided state space traversal to address this issue. However, providing guidance for state space traversal of complex designs is also an equally challenging problem. We adopt a simulation-based strategy combined with Bayesian modelling approach for finding effective guidance hints for state space traversal. A heuristic-based structural dependency of the design yields ineffective guidance hints which need further of filtering. To prune out the ineffective guidance hints, we first generate module-level sub-properties from static analysis of the design. These sub-properties and structural dependency-based guidance hints are analyzed in simulation traces generated from the constrained-random test benches. These conditional occurrence of sub-properties and guidance hints are inputs to a Bayesian model which can then provide us the guidance hints with the highest profitability. With the proposed methodology, we succeed in pruning out the set of unprofitable guidance hints and obtain effective search directions which are then used to assist the model checking procedure. Experiments on two complex designs for different properties show the effectiveness of the proposed methodology in reducing CPU time during model checking.

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Achieving full functional coverage for the forwarding unit of pipelined processors

Achieving full functional coverage for the forwarding unit o...

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2017 IEEE East-West Design and Test Symposium, EWDTS 2017

作者： Vineesh, V.S. Hage, Nihar Karthik, B Singh, Virendra Computer Architecture and Dependable Systems Lab Department of Electrical Engineering Indian Institute of Technology Bombay India

ISBN: (纸本)9781538632994

Generic instruction based testing methods do not always give good fault coverage for the complex units like Forwarding unit. Hence it becomes important to carefully craft the test which are best for different parts of these units. In this paper we have identified two different test generation methods for different sections of the forwarding unit, namely muxes and comparators which offers better coverage independently: template based test instruction generation and test instruction generation from constrained test vectors. A wrapper designed using the functional constraints of the forwarding unit, is used for test generation. Both methods combined delivers fault coverage of 97.33%. A detailed analysis of the non-detected faults revealed the fact that they cannot be tested using the instruction set of the processor (MIPS 5-stage pipelined processor). This proves that the proposed method achieved 100% functional coverage for stuck-at faults in the forwarding unit. © 2017 IEEE.

关键词： Testing

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PHP: Power hungry pattern generation at higher abstraction level

PHP: Power hungry pattern generation at higher abstraction l...

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East-West Design & Test Symposium (EWDTS)

作者： Rohini Gulve Anshu Goel Virendra Singh Computer Architecture and Dependable Systems Lab Electrical Engineering Indian Institute of Technology Bombay India

The Performance, area, and power are most essential factors to be considered and optimize at every step in the design cycle. Design engineers often need to learn about these factors in order make right decisions on design strategies. Power analysis at lower levels of abstraction can provide more accurate analysis than higher levels. Worst case power can be estimated through high activity pattern generation. However, generation of such power hungry patterns (PHP) become challenging as the number of modules or design components increases. This process can be accelerated at higher abstraction levels by utilizing the available information. In this paper, we generate PHP by at higher abstraction level with significant speed up. A genetic algorithm is implemented to find out the global maximum power of designs. An experiment indicates that the process implemented is much faster and it finds about 10 % more power demanding PHP than random samples generated.

关键词： Mathematical model Genetic algorithms Integrated circuit modeling Logic gates Power demand Optimization Libraries

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REMO: Redundant execution with minimum area, power, performance overhead fault tolerant architecture

REMO: Redundant execution with minimum area, power, performa...

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IEEE Symposium on On-Line Testing (IOLTS)

作者： Shoba Gopalakrishnan Virendra Singh Computer Architecture & Dependable Systems Lab Indian Institute of Technology Bombay India

ISBN: (纸本)9781509015085

Relentless scaling in CMOS fabrication technology has made contemporary integrated circuits continue to evolve and grow in functionality with high clock frequencies and exponentially increasing transistor counts. However, it also makes them more susceptible to transient faults effectively decreasing their reliability. Therefore, ensuring correct and reliable operation of these microprocessors at low cost has become a challenging task. This paper proposes a light weight error detection method called REMO which aims to incorporate simple fault tolerance mechanisms as part of the basic architecture. It dynamically verifies the execution results of the instructions by exploiting spatial and temporal redundancy and detects soft errors. REMO shows that with minimal area, power and performance overhead, and a very low detection latency, a very high degree of fault coverage can be achieved. Our simulation results shows an increase in area is about 0.4%, power overhead near to 9% and a negligible performance penalty during fault free run.

关键词： Redundancy Out of order Pipelines Hardware Fault tolerant systems

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A trace signal selection algorithm for improved post-silicon debug

A trace signal selection algorithm for improved post-silicon...

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East-West Design & Test Symposium (EWDTS)

作者： Binod Kumar Ankit Jindal Virendra Singh Computer Architecture and Dependable Systems Lab (CADSL) Indian Institute of Technology Bombay India

ISBN: (纸本)9781509006946

Enhancing observability is a key challenge in post-silicon validation. On-chip trace buffers store real time data which can be used for analyzing and debugging. Appropriate selection of these signals is crucial for storing useful debug data. This paper proposes a methodology for identifying trace signals so as to maximize detection of erroneous behavior of the failing chip which helps in improving quality of information available for debugging. Different quantitative measures are proposed to assess utility of debug data. Experimental results on benchmark circuits indicate that the methodology is useful for selecting trace signals which maximize debug data effectiveness.

关键词： computer bugs Clocks Logic gates Buffer storage Algorithm design and analysis Silicon Debugging

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A technique for low power, stuck-at fault diagnosable and reconfigurable scan architecture

A technique for low power, stuck-at fault diagnosable and re...

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East-West Design & Test Symposium (EWDTS)

作者： Binod Kumar Boda Nehru Brajesh Pandey Virendra Singh Jaynarayan Tudu Computer Architecture and Dependable Systems Lab (CADSL) Indian Institute of Technology Bombay India Dept. of Computer Science and Automation Indian Institute of Science Bangalore

ISBN: (纸本)9781509006946

Power dissipation is a major issue with testing of designs having full scan architectures. The proposed scan technique minimizes toggle activity while scanning in test patterns. The method uses bit inversion technique to avoid toggles in scan flip-flops. The setup is dynamically configurable to one among the logic reversal structure and traditional scan while shift-in/shift-out of test patterns. Experimental results indicate that the average toggle activity is minimized substantially compared to California Scan architecture. It has features of full diagnosability of single stuck-at faults along the scan chain path.

关键词： computer architecture Silicon Circuit faults Testing Logic gates Inverters Clocks

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