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arXiv 2024年

作者： Elsharkawy, Amr Guo, Xiaorang Schulz, Martin Chair of Computer Architecture and Parallel Systems Technical University of Munich Munich Germany

To harness the power of quantum computing (QC) in the near future, tight and efficient integration of QC with high performance computing (HPC) infrastructure (both on the software (SW) and the hardware (HW) level) is crucial. This paper addresses the development of a unified quantum platform (UQP) and how it is being integrated into the HPC ecosystem. It builds on the concepts of hybrid high performance computing - quantum computing (HPCQC) workflows and a unified HPCQC toolchain, introduced in our previous work and makes the next needed step: it unifies the low-level interface between the existing classical HPC systems and the emerging quantum hardware technologies, including but not limited to machines based on superconducting qubits, neutral atoms or trapped ions. The UQP consists of three core components: a runtime library, an instruction set architecture (ISA) and a quantum control processor (QCP) micro-architecture. In particular, this work contributes a unified HPCQC runtime library that bridges the gap between programming systems built on quantum intermediate representation (QIR) standard with a novel, unified hybrid ISA. It then introduces the initial extension of an ISA and QCP micro-architecture to be platform and technology agnostic and enables it as an efficient execution platform. The UQP has been verified to ensure correctness. Further, our performance analysis shows that the execution time and memory requirements of the runtime library scale superlinearly with number of qubits, which is critical to support scalability efforts in QC hardware. Copyright © 2024, The Authors. All rights reserved.

关键词： Trapped ions

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Integration of Quantum Accelerators into HPC: Toward a Unified Quantum Platform

Integration of Quantum Accelerators into HPC: Toward a Unifi...

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Quantum Computing and Engineering (QCE), IEEE International Conference on

作者： Amr Elsharkawy Xiaorang Guo Martin Schulz Chair of Computer Architecture and Parallel Systems Technical University of Munich Munich Germany

ISBN: (数字)9798331541378

ISBN: (纸本)9798331541385

To harness the power of quantum computing (QC) in the near future, tight and efficient integration of QC with high performance computing (HPC) infrastructure (both on the software (SW) and the hardware (HW) level) is crucial. This paper addresses the development of a unified quantum platform (UQP) and how it is being integrated into the HPC ecosystem. It builds on the concepts of hybrid high performance computing - quantum computing (HPCQC) workflows and a unified HPCQC toolchain, introduced in our previous work and makes the next needed step: it unifies the low-level interface between the existing classical HPC systems and the emerging quantum hardware technologies, including but not limited to machines based on superconducting qubits, neutral atoms or trapped ions. The UQP consists of three core components: a runtime library, an instruction set architecture (ISA) and a quantum control processor (QCP) micro-architecture. In particular, this work contributes a unified HPCQC runtime library that bridges the gap between programming systems built on quantum intermediate representation (QIR) standard with a novel, unified hybrid ISA. It then introduces the initial extension of an ISA and QCP micro-architecture to be platform and technology agnostic and enables it as an efficient execution platform. The UQP has been verified to ensure correctness. Further, our performance analysis shows that the execution time and memory requirements of the runtime library scale super-linearly with number of qubits, which is critical to support scalability efforts in OC hardware.

关键词： Runtime library Scalability High performance computing Qubit Process control Atoms Hardware Software Performance analysis Logic

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Towards the Munich Quantum Software Stack: Enabling Efficient Access and Tool Support for Quantum computers 4

Towards the Munich Quantum Software Stack: Enabling Efficien...

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4th IEEE International Conference on Quantum Computing and Engineering, QCE 2023

作者： Schulz, Martin Schulz, Laura Ruefenacht, Martin Wille, Robert Technical University of Munich Computer Architecture and Parallel Systems Munich Germany Leibniz Supercomputing Centre Qct Department Garching Germany Technical University of Munich Design Automation Munich Germany

ISBN: (纸本)9798350343236

As quantum computing systems mature and move from laboratories to production computing environments, corresponding software stacks are becoming key for their successful utilization. In particular, the expected use of quantum systems as HPC accelerators requires a deep integration with the existing and widely deployed HPC software stacks. Additionally, new requirements such as dynamic compilation and new challenges for tools and programming models must be considered. We tackle these challenges by developing the Munich Quantum Software Stack - a comprehensive initiative by the Munich Quantum Valley to offer a flexible, efficient, and user-oriented software environment. In this poster, we describe the core components and workflows, and how they will enable this transformation from quantum experiments to quantum accelerators. © 2023 IEEE.

关键词： Quantum optics

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FaST-GShare: Enabling Efficient Spatio-Temporal GPU Sharing in Serverless Computing for Deep Learning Inference

arXiv

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arXiv 2023年

作者： Gu, Jianfeng Zhu, Yichao Wang, Puxuan Chadha, Mohak Gerndt, Michael Computer Architecture & Parallel Systems Technical University of Munich Munich Germany

Serverless computing (FaaS) has been extensively utilized for deep learning (DL) inference due to the ease of deployment and pay-per-use benefits. However, existing FaaS platforms utilize GPUs in a coarse manner for DL inferences, without taking into account spatio-temporal resource multiplexing and isolation, which results in severe GPU under-utilization, high usage expenses, and SLO (Service Level Objectives) violation. There is an imperative need to enable an efficient and SLO-aware GPU-sharing mechanism in serverless computing to facilitate cost-effective DL inferences. In this paper, we propose FaST-GShare, an efficient FaaS-oriented Spatio-Temporal GPU Sharing architecture for deep learning inferences. In the architecture, we introduce the FaST-Manager to limit and isolate spatio-temporal resources for GPU multiplexing. In order to realize function performance, the automatic and flexible FaST-Profiler is proposed to profile function throughput under various resource allocations. Based on the profiling data and the isolation mechanism, we introduce the FaST-Scheduler with heuristic auto-scaling and efficient resource allocation to guarantee function SLOs. Meanwhile, FaST-Scheduler schedules function with efficient GPU node selection to maximize GPU usage. Furthermore, model sharing is exploited to mitigate memory contention. Our prototype implementation on the OpenFaaS platform and experiments on MLPerf-based benchmark prove that FaST-GShare can ensure resource isolation and function SLOs. Compared to the time sharing mechanism, FaST-GShare can improve throughput by 3.15x, GPU utilization by 1.34x, and SM (Streaming Multiprocessor) occupancy by 3.13x on average. © 2023, CC BY-NC-ND.

关键词： Graphics processing unit

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LoRa-Powered Energy-Effcient Object Detection Mechanism in Edge Computing Nodes 6

LoRa-Powered Energy-Effcient Object Detection Mechanism in E...

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6th International Conference on I-SMAC (IoT in Social, Mobile, Analytics and Cloud), I-SMAC 2022

作者： Jindal, Anshul Jose, Jiby Mariya Benedict, Shajulin Gerndt, Michael Technical University Munich Computer Architecture and Parallel Systems Germany Indian Institute of Information Technology Kottayam Department of Computer Science and Engg. India

ISBN: (数字)9781665469418

ISBN: (纸本)9781665469418

The ongoing accomplishments in the decades-long realization of computer vision have infused new dimensions in various research areas such as smart mobility, smart healthcare, education, finance, and so forth. Research works relating to automated object detection, deep learning-assisted data pipelines, and energy-efficient end-to-end solutions have enabled newer perceptions among researchers, albeit the existence of challenges. This paper proposes an object detection system using energy-efficient Long Range (LoRA) communication media on edge nodes such as Raspberry Pi, Coral DevBoard, and Nvidia Jetson Nano. The proposed approach utilized energy-efficient methods to collaboratively offload object detection-related tasks such as capturing images, training images, and inferring objects across a compendium of computing nodes using LoRA. In addition, this research study has attempted to reveal the inference capabilities of images on three different edge nodes. The proposed work has achieved a power difference of at least 1.2 watts during the inference period of the deep learning models without challenging the prediction accuracy with respect to the base model. © 2022 IEEE.

关键词： Object detection

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Large Language Model-Based Optimization for System-Level Test Program Generation 37

Large Language Model-Based Optimization for System-Level Tes...

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37th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology systems, DFT 2024

作者： Schwachhofer, Denis Domanski, Peter Becker, Steffen Wagner, Stefan Sauer, Matthias Pfluger, Dirk Polian, Ilia Institute of Computer Engineering and Computer Architecture University of Stuttgart Stuttgart Germany Institute of Software Engineering University of Stuttgart Stuttgart Germany Institute for Parallel and Distributed Systems University of Stuttgart Stuttgart Germany Technical University of Munich Heilbronn Germany Advantest Europe Boeblingen Germany

ISBN: (纸本)9798350366884

System-Level Test (SLT) is essential for testing integrated circuits, focusing on functional and non-functional properties of the Device under Test (DUT). Traditionally, test engineers manually create tests with commercial software to simulate the DUT's end-user environment. This process is both time-consuming and offers limited control over non-functional properties. This paper proposes Large Language Models (LLMs) enhanced by Structural Chain of Thought (SCoT) prompting, a temperature schedule, and a pool of previously generated snippets to generate high-quality code snippets for SLT. We repeatedly query the LLM for a better snippet using previously generated snippets as examples, thus creating an iterative optimization loop. This approach can automatically generate snippets for SLT that target specific non-functional properties, reducing time and effort. Our findings show that this approach improves the quality of the generated snippets compared to unstructured prompts containing only a task description. © 2024 IEEE.

关键词： Functional Test Large Language Models Optimization System-Level Test Test Generation

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A Scalable and Cross-Technology Quantum Control Processor

A Scalable and Cross-Technology Quantum Control Processor

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International Conference on Field Programmable Logic and Applications

作者： Xiaorang Guo Martin Schulz Chair of Computer Architecture and Parallel Systems Technical University of Munich Garching Germany

Quantum control processors (QCPs) bridge the gap between the quantum software and the hardware backend to construct full-stack quantum computers. In this study, the quantum backend interface is responsible for generating pulses to control qubits, where commercial waveform generators or specific converters are typically needed. A radio frequency system-on-chip (RFSoC)-based QCP supports a direct control pulse synthesis without additional components. Therefore, in this work, we propose an RFSoC-based QCP that integrates the processor and pulse generation logic onto a single board. With the help of the proposed instruction set and efficient microarchitecture implementation, the QCP offers large scalability for controllable qubits, while supporting different physical platforms.

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gFaaS: Enabling Generic Functions in Serverless Computing

gFaaS: Enabling Generic Functions in Serverless Computing

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IEEE International Conference on Software Analysis, Evolution and Reengineering (SANER)

作者： Mohak Chadha Paul Wieland Michael Gerndt Chair of Computer Architecture and Parallel Systems Technische Universität München Garching (near Munich) Germany

ISBN: (数字)9798350330663

ISBN: (纸本)9798350330670

With the advent of AWS Lambda in 2014, Serverless Computing, particularly Function-as-a-Service (FaaS), has witnessed growing popularity across various application domains. FaaS enables an application to be decomposed into fine-grained functions that are executed on a FaaS platform. It offers several advantages such as no infrastructure management, a pay-per-use billing policy, and on-demand fine-grained autoscaling. However, despite its advantages, developers today encounter various challenges while adopting FaaS solutions that reduce productivity. These include FaaS platform lock-in, support for diverse function deployment parameters, and diverse interfaces for interacting with FaaS platforms. To address these challenges, we present gFaaS, a novel framework that facilitates the holistic development and management of functions across diverse FaaS platforms. Our framework enables the development of generic functions in multiple programming languages that can be seamlessly deployed across different platforms without modifications. Results from our experiments demonstrate that gFaaS functions perform similarly to native platform-specific functions across various scenarios. A video demonstrating the functioning of gFaaS is available from https://***/STbb6ykJFf0.

关键词： Productivity computer languages Serverless computing Software

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iCheck: Leveraging RDMA and Malleability for Application-Level Checkpointing in HPC systems

iCheck: Leveraging RDMA and Malleability for Application-Lev...

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International Conference on parallel and Distributed systems (ICPADS)

作者： Jophin John Isaac David Núñez Araya Michael Gerndt Chair of Computer Architecture and Parallel Systems Technische Universität München Germany

The estimate that the mean time between failures will be in minutes in exascale supercomputers should be alarming for application developers. The inherent system’s complexity, millions of components, and susceptibility to failures make checkpointing more relevant than ever. Since most high performance scientific applications contain an in-house checkpoint restart mechanism, their performance can be impacted by the contention of parallel file system resources. A shift in checkpointing strategies is needed to thwart this behavior. With iCheck, we present a novel checkpointing framework that supports malleable multilevel application-level checkpointing. We employ an RDMA enabled configurable multi-agent-based checkpoint transfer mechanism where minimal application resources are utilized for checkpointing. The high-level API of iCheck facilitates easy integration and malleability. We have added the iCheck library into the Is1 mardyn application providing performance improvement up to five thousand times over the in-house checkpointing mechanism. LULESH, Jacobi 2D heat simulation, and a synthetic application were also used for extensive analysis.

关键词： Checkpointing Jacobian matrices Heating systems Fault tolerance File systems Fault tolerant systems Supercomputers

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Real-Time Capability of DLR’S Beamforming Synthetic Aperture Radar Processing architecture

Real-Time Capability of DLR’S Beamforming Synthetic Apertur...

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Acoustics, Speech, and Signal Processing Workshops (ICASSPW), IEEE International Conference on

作者： Maron Schlemon Martin Schulz Rolf Scheiber Marc Jäger Joel Amao Oliva German Aerospace Center (DLR) Microwaves and Radar Institute Germany Chair of Computer Architecture and Parallel Systems Technical University of Munich Germany

ISBN: (数字)9798350374513

ISBN: (纸本)9798350374520

Synthetic Aperture Radar (SAR) enables the generation of realistic and high-resolution 2D or 3D representations of landscapes. Typically, radar instruments are deployed in specially equipped, low-flying aircraft that capture a significant amount of raw data, necessitating image reconstruction processing. However, the aircraft’s limited onboard processing capabilities (power, size, weight, cooling, and communication bandwidth to ground stations) and the need to generate multiple SAR products, such as slant-range and geo-coded images during a single flight, require efficient onboard processing and transmission to the ground station. This paper outlines the processing architecture of the digital beamforming SAR (DBFSAR) employed by the German Aerospace Center (DLR) and the specific measures implemented to enable onboard processing. We elucidate the essential software optimizations and their integration into the SAR onboard routines, facilitating (near) real-time capability under certain conditions. Furthermore, we share the insights gained from our work and discuss their applicability to other processing scenarios with limited resource availability.

关键词： Three-dimensional displays Array signal processing Instruments computer architecture Radar imaging Real-time systems Software

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