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International Conference on Field Programmable Logic and Applications

作者： Xiaorang Guo Martin Schulz Chair of Computer Architecture and Parallel Systems Technical University of Munich Garching Germany

Quantum control processors (QCPs) bridge the gap between the quantum software and the hardware backend to construct full-stack quantum computers. In this study, the quantum backend interface is responsible for generating pulses to control qubits, where commercial waveform generators or specific converters are typically needed. A radio frequency system-on-chip (RFSoC)-based QCP supports a direct control pulse synthesis without additional components. Therefore, in this work, we propose an RFSoC-based QCP that integrates the processor and pulse generation logic onto a single board. With the help of the proposed instruction set and efficient microarchitecture implementation, the QCP offers large scalability for controllable qubits, while supporting different physical platforms.

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Document replacement policies dedicated to Web caching

Document replacement policies dedicated to Web caching

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IEEE International Symposium on Intelligent Control (ISIC)

作者： A. Belloum L.O. Hertzberger Computer Architecture and Parallel Systems Group Department of Computer Science Universiteit van Amsterdam Amsterdam Netherlands

Web caching has been considered as a powerful solution to deal with the growth of Web traffic. Several studies have shown that caching documents throughout the Internet can save network bandwidth and reduce document access latency. However, this technique has introduced new problems such as maintaining the document coherency and selecting the next document to be removed. With the continuous increase in demand for documents, the Web cache servers are becoming the new bottleneck. A need for better resource management is becoming urgent in order to reduce the overhead sustained by Web cache servers. In this paper, a number of Web replacement policies are discussed and compared on the basis of trace-driven simulations. The impact of the Web cache server configuration is pointed out through a set of experiments that use the cache size as a tuning parameter.

关键词： Delay computer architecture computer science Telecommunication traffic Bandwidth Network servers Resource management Topology Joining processes Cache storage

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Dealing with one-timer-documents in Web caching

Dealing with one-timer-documents in Web caching

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EUROMICRO Conference

作者： A. Belloum L.O. Hertzberger Computer Architecture and Parallel Systems Group Department of Computer Science Universiteit van Amsterdam Amsterdam Netherlands

A proper initialization requires starting the process in a state close to the expected steady state. In Web caching, the initialization problem is faced each time a new document enters the cache. Independently of the method used to sort the documents into the cache, the newly referenced document is inserted in a so called "removal-list", from which documents are removed when storage space is needed. Often, undesirable documents are assigned a high priority, consequently these documents remain for quite a long time in the cache, leading to a decrease in cache server performances. We investigate one category of undesirable documents, which pass the filters commonly used to control the cache processing.

关键词： Internet Telecommunication traffic Web server Cache storage computer architecture computer science Steady-state Pattern analysis IP networks

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iCheck: Leveraging RDMA and Malleability for Application-Level Checkpointing in HPC systems

iCheck: Leveraging RDMA and Malleability for Application-Lev...

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International Conference on parallel and Distributed systems (ICPADS)

作者： Jophin John Isaac David Núñez Araya Michael Gerndt Chair of Computer Architecture and Parallel Systems Technische Universität München Germany

The estimate that the mean time between failures will be in minutes in exascale supercomputers should be alarming for application developers. The inherent system’s complexity, millions of components, and susceptibility to failures make checkpointing more relevant than ever. Since most high performance scientific applications contain an in-house checkpoint restart mechanism, their performance can be impacted by the contention of parallel file system resources. A shift in checkpointing strategies is needed to thwart this behavior. With iCheck, we present a novel checkpointing framework that supports malleable multilevel application-level checkpointing. We employ an RDMA enabled configurable multi-agent-based checkpoint transfer mechanism where minimal application resources are utilized for checkpointing. The high-level API of iCheck facilitates easy integration and malleability. We have added the iCheck library into the Is1 mardyn application providing performance improvement up to five thousand times over the in-house checkpointing mechanism. LULESH, Jacobi 2D heat simulation, and a synthetic application were also used for extensive analysis.

关键词： Checkpointing Jacobian matrices Heating systems Fault tolerance File systems Fault tolerant systems Supercomputers

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Migrating from Microservices to Serverless: An IoT Platform Case Study

arXiv

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arXiv 2022年

作者： Chadha, Mohak Pacyna, Victor Jindal, Anshul Gu, Jianfeng Gerndt, Michael Computer Architecture and Parallel Systems Technische Universität München Garching Munich Germany

Microservice architecture is the common choice for developing cloud applications these days since each individual microservice can be independently modified, replaced, and scaled. As a result, application development and operating cloud infrastructure were bundled together into what is now commonly called DevOps. However, with the increasing popularity of the serverless computing paradigm and its several advantages such as no infrastructure management, a pay-per-use billing policy, and on-demand fine-grained autoscaling, there is a growing interest in utilizing FaaS and serverless CaaS technologies for refactoring microservices-based applications. Towards this, we migrate a complex IoT platform application onto OpenWhisk (OW) and Google Cloud Run (GCR). We comprehensively evaluate the performance of the different deployment strategies, i.e., Google Kubernetes Engine (GKE)-Standard, OW, and GCR for the IoT platform using different load testing scenarios. Results from our experiments show that while GKE standard performs best for most scenarios, GCR is always cheaper wrt costs. Copyright © 2022, The Authors. All rights reserved.

关键词： Internet of things

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Codelet Scheduling by Genetic Algorithm

Codelet Scheduling by Genetic Algorithm

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IEEE International Conference on Trust, Security and Privacy in Computing and Communications (TrustCom)

作者： Songwen Pei Jinkai Wang Wenyang Cui Linhua Jiang Tongsheng Geng Jean-Luc Gaudiot Stéphane Zuckerman Shanghai Key Lab of Modern Optical Systems University of Shanghai for Science and Technology Shanghai China Parallel Systems and Computer Architecture Lab University of California Irvine CA USA Computer Architecture & Parallel Systems Laboratory University of Delaware Newark DE

ISBN: (纸本)9781509032068

Codelet model is a fine-grained, event-driven hybrid parallel model inspired by dataflow, whose performance depends on the scheduling policy. How to design optimal codelet scheduling policy based on the features of tasks is important to the codelet-based system performance. In this paper, we propose an adaptive codelet scheduling policy by combing "pure" genetic algorithm for tasks with complex dependencies. It is verified that the policy is effective based on bunches of experimental results.

关键词： Computational modeling Schedules Genetic algorithms Scheduling Runtime Optimal scheduling Sociology

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Designing an Adaptive Application-Level Checkpoint Management System for Malleable MPI Applications

arXiv

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arXiv 2022年

作者： John, Jophin Gerndt, Michael Computer Architecture and Parallel Systems Technische Universität München Garching Munich Germany

Dynamic resource management opens up numerous opportunities in High Performance Computing. It improves the system-level services as well as application performance. Checkpointing can also be deemed as a system-level service and can reap the benefits offered by dynamism. A checkpointing system can have better resource availability by integrating with a malleable resource management system. In addition to fault tolerance, the checkpointing system can cater to the data redistribution demand of malleable applications during resource change. Therefore, we propose iCheck, an adaptive application-level checkpoint management system that can efficiently utilize the system and application level dynamism to provide better checkpointing and data redistribution services to applications. © 2022, CC BY.

关键词： Fault tolerance

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IaaS Reactive Autoscaling Performance Challenges

IaaS Reactive Autoscaling Performance Challenges

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IEEE International Conference on Cloud Computing, CLOUD

作者： Vladimir Podolskiy Anshul Jindal Michael Gerndt Chair for Computer Architecture and Parallel Systems Technical University of Munich Garching (near Munich) Germany

The main feature of a cloud application is its scalability. Major IaaS cloud services providers (CSP) employ autoscaling on the level of virtual machines (VM). Other virtualization solutions (e.g. containers, pods) can also scale. An application scales in response to change in observed metrics, e.g. in CPU utilization. Occasionally, cloud applications exhibit the inability to meet the Quality of Service (QoS) requirements during the scaling caused by the reactivity of autoscaling solutions. This paper provides the results of the autoscaling performance evaluation for two-layered virtualization (VMs and Kubernetes pods) conducted in the public clouds of AWS, Microsoft and Google using the approach and the Autoscaling Performance Measurement Tool developed by the authors.

关键词： Cloud computing Quality of service Measurement Virtualization Google Tools Scalability

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Large Language Model-Based Optimization for System-Level Test Program Generation 37

Large Language Model-Based Optimization for System-Level Tes...

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37th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology systems, DFT 2024

作者： Schwachhofer, Denis Domanski, Peter Becker, Steffen Wagner, Stefan Sauer, Matthias Pfluger, Dirk Polian, Ilia Institute of Computer Engineering and Computer Architecture University of Stuttgart Stuttgart Germany Institute of Software Engineering University of Stuttgart Stuttgart Germany Institute for Parallel and Distributed Systems University of Stuttgart Stuttgart Germany Technical University of Munich Heilbronn Germany Advantest Europe Boeblingen Germany

ISBN: (纸本)9798350366884

System-Level Test (SLT) is essential for testing integrated circuits, focusing on functional and non-functional properties of the Device under Test (DUT). Traditionally, test engineers manually create tests with commercial software to simulate the DUT's end-user environment. This process is both time-consuming and offers limited control over non-functional properties. This paper proposes Large Language Models (LLMs) enhanced by Structural Chain of Thought (SCoT) prompting, a temperature schedule, and a pool of previously generated snippets to generate high-quality code snippets for SLT. We repeatedly query the LLM for a better snippet using previously generated snippets as examples, thus creating an iterative optimization loop. This approach can automatically generate snippets for SLT that target specific non-functional properties, reducing time and effort. Our findings show that this approach improves the quality of the generated snippets compared to unstructured prompts containing only a task description. © 2024 IEEE.

关键词： Functional Test Large Language Models Optimization System-Level Test Test Generation

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An Accurate and Hardware-Efficient Dual Spike Detector for Implantable Neural Interfaces

An Accurate and Hardware-Efficient Dual Spike Detector for I...

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2022 IEEE Biomedical Circuits and systems Conference, BioCAS 2022

作者： Guo, Xiaorang Shaeri, MohammadAli Shoaran, Mahsa Institute of Electrical and Micro Engineering Center for Neuroprosthetics Epfl Geneva1202 Switzerland Faculty of Electrical and Computer Engineering Technische Universität Dresden Dresden01069 Germany Chair of Computer Architecture and Parallel Systems Technische Universität München Garching85748 Germany

ISBN: (数字)9781665469173

ISBN: (纸本)9781665469173

Spike detection plays a central role in neural data processing and brain-machine interfaces (BMIs). A challenge for future-generation implantable BMIs is to build a spike detector that features both low hardware cost and high performance. In this work, we propose a novel hardware-efficient and high-performance spike detector for implantable BMIs. The proposed design is based on a dual-detector architecture with adaptive threshold estimation. The dual-detector comprises two separate TEO-based detectors that distinguish a spike occurrence based on its discriminating features in both high and low noise scenarios. We evaluated the proposed spike detection algorithm on the Wave Clus dataset. It achieved an average detection accuracy of 98.9%, and over 95% in high-noise scenarios, ensuring the reliability of our method. When realized in hardware with a sampling rate of 16kHz and 7-bits resolution, the detection accuracy is 97.4%. Designed in 65nm TSMC process, a 256-channel detector based on this architecture occupies only 682μm2/Channel and consumes 0.07μW/Channel, improving over the state-of-the-art spike detectors by 39.7% in power consumption and 78.8% in area, while maintaining a high accuracy. © 2022 IEEE.

关键词： Data handling

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