Technology probes are low-fidelity devices that can be used to understand research participant’s lived experiences, but they are not usually subject to iterative design. There are opportunities in human-computer inte...
详细信息
ISBN:
(纸本)9781450395984
Technology probes are low-fidelity devices that can be used to understand research participant’s lived experiences, but they are not usually subject to iterative design. There are opportunities in human-computer interaction to develop technology probes through co-design, by including diverse perspectives during probe development. To explore this opportunity, five design researchers with different disciplinary and cultural backgrounds engaged with a technology probe to support daily reflections, discussed new directions in a co-design workshop and developed narratives to negotiate possibilities of the probe. This paper presents observations described by each of the researchers using the probe, and insights from the process we followed. We discuss how the the designers’ postitionalities are reflected in the processes, and how they brought value by shaping narratives of the different roles a technology probe might take. We also discuss how we may use co-design of technology probes as a generative method, highlight the importance of open-endedness in the process, and reflect on lessons learned.
We address the problem of CMOS cell width minimization in the general two-dimensional (2-D) layout style and propose a novel technique based on integer linear programming (ILP) to solve it exactly. We formulate a 0-1 ...
详细信息
ISBN:
(纸本)9780818675973
We address the problem of CMOS cell width minimization in the general two-dimensional (2-D) layout style and propose a novel technique based on integer linear programming (ILP) to solve it exactly. We formulate a 0-1 ILP model whose solution minimizes cell width along with the routing complexity across the diffusion rows. We present experimental results that evaluate the performance of two ILP solvers that have very different solution methods, and assess the effect of the number of rows on cell width. Run-times for optimal layouts are in seconds for cells with up to 20 transistors. For larger cells, we propose a practical circuit pre-processing scheme that dramatically reduces the run time with little or no loss in optimality.
We present a hierarchical technique HCLIP to generate near-optimum layouts of CMOS cells in the two-dimensional (2-D) style. HCLIP is based on integer-linear programming and extends our previously published CLIP techn...
详细信息
We present a hierarchical technique HCLIP to generate near-optimum layouts of CMOS cells in the two-dimensional (2-D) style. HCLIP is based on integer-linear programming and extends our previously published CLIP technique to much larger cells and to 2-D cell-arrays. HCLIP partitions the circuit into clusters, generates minimum-width 1-D placements (chain covers) for each cluster and then selects one cover for each cluster such that the overall 2-D cell width and height is minimized. In doing so, HCLIP explores all diffusion sharing between transistor chains belonging to the selected covers. For width minimization, HCLIP yields 2-D layouts that have minimum width with respect to the given set of covers. For both width and height minimization, since HCLIP is approximate and can overestimate cell height, we analyze the theoretical worst-case approximation. Experimental results demonstrate that HCLIP still yields near-optimal layouts in most cases.
The combination of thermographic and geometric recording has always been an issue for architectural heritage diagnostic investigations. Multidisciplinary projects often require integrating multi-sensor information—in...
详细信息
To provide different services to smart cities, many new approaches were used, including the strategic approach and the techno-human-centric approach. When it combines both the human aspect through its sensitivities an...
详细信息
As microprocessors become more complex, early design space exploration plays an essential role in reducing the time to market and post-silicon surprises. The trend toward multi-/many- core processors will result in so...
详细信息
ISBN:
(纸本)9781424449279
As microprocessors become more complex, early design space exploration plays an essential role in reducing the time to market and post-silicon surprises. The trend toward multi-/many- core processors will result in sophisticated large-scale architecture substrates (e.g. non-uniformly accessed caches interconnected by network-on-chip) that exhibit increasingly complex and heterogeneous behavior. While conventional analytical modeling techniques can be used to efficiently explore the characteristics (e.g. IPC and power) of monolithic architecturedesign, existing methods lack the ability to accurately and informatively forecast the complex behavior of large and distributed architecture substrates across the design space. This limitation will only be exacerbated with the rapidly increased integration scale (e.g. number of cores per chip). In this paper, we propose novel, multi-scale 2D predictive models which can efficiently reason the characteristics of large and sophisticated multi-core oriented architectures during the design space exploration stage without using detailed cycle-level simulations. Our proposed techniques employ 2D wavelet multiresolution analysis and neural network regression modeling. We extensively evaluate the efficiency of our predictive models in forecasting the complex and heterogeneous characteristics of large and distributed shared cache interconnected by a network on chip in multi-core designs using both multi-programmed and multithreaded workloads. Experimental results show that the models achieve high accuracy while maintaining low complexity and computation overhead. Through case studies, we demonstrate that the proposed techniques can be used to informatively explore and accurately evaluate global, cooperative multi-core resource allocation and thermal-aware designs that cannot be achieved using conventional design exploration methods.
Novel space-time-frequency processing schemes for OFDM mobile communication systems are implemented using antenna arrays, tap delay lines and Doppler branches to exploit angular spread, delay spread and Doppler spread...
详细信息
ISBN:
(纸本)0780377575
Novel space-time-frequency processing schemes for OFDM mobile communication systems are implemented using antenna arrays, tap delay lines and Doppler branches to exploit angular spread, delay spread and Doppler spread, respectively.
暂无评论