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WallBots: Interactive wall-crawling robots in the hands of public artists and political activists 10

WallBots: Interactive wall-crawling robots in the hands of p...

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Proceedings of the 8th ACM Conference on designing Interactive Systems

作者： Kuznetsov, Stacey Paulos, Eric Gross, Mark D. Human-Computer Interaction Institute Carnegie Mellon University 5000 Forbes Avenue Pittsburgh PA United States Computational Design Lab. School of Architecture Carnegie Mellon University 5000 Forbes Avenue Pittsburgh PA United States

ISBN: (纸本)9781450301039

Street art and political activism have a rich history of shaping urban landscapes. Our work explores the processes by which public artists and political activists contribute to public spaces, introducing opportunities for HCI researchers to engage with the people who shape the aesthetic feel of our cities. We present WallBots-autonomous, wall-crawling robots as a research probe for public expression across a wide range of surfaces and hard-to-reach places, including bus stops, whiteboards, streetpoles, trashcans, moving vehicles and building walls. We evaluate WallBots as a low-cost DIY authoring tool for public artists and activists. Our study of six individuals who extensively contribute to public spaces offers insights into the materials and practices behind grassroots public expression. We then leverage feedback from participants, among them a graffiti artist, light painter, political activists, and street musician, to evaluate interaction techniques for manipulating WallBots as a medium for public expression across a range of surfaces. Our findings expose a research space for technological interventions in the context of street art, and we conclude with design insights for magnetic kinetic systems as an approach for supporting engagement, expression and creativity in public spaces. © 2010 ACM.

关键词： Autonomous agents

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Accurate, scalable and informative design space exploration for large and sophisticated multi-core oriented architectures

Accurate, scalable and informative design space exploration ...

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International Symposium on Modeling, Analysis and Simulation of computer and Telecommunication Systems (MASCOTS)

作者： Chang-Burm Cho James Poe Tao Li Jingling Yuan Intelligent Design of Efficient Architecture Lab IDEAL Department of ECE University of Florida Gainesville FL USA Computer Science and Technology School Wuhan University of Technology Wuhan China

ISBN: (纸本)9781424449279

As microprocessors become more complex, early design space exploration plays an essential role in reducing the time to market and post-silicon surprises. The trend toward multi-/many- core processors will result in sophisticated large-scale architecture substrates (e.g. non-uniformly accessed caches interconnected by network-on-chip) that exhibit increasingly complex and heterogeneous behavior. While conventional analytical modeling techniques can be used to efficiently explore the characteristics (e.g. IPC and power) of monolithic architecture design, existing methods lack the ability to accurately and informatively forecast the complex behavior of large and distributed architecture substrates across the design space. This limitation will only be exacerbated with the rapidly increased integration scale (e.g. number of cores per chip). In this paper, we propose novel, multi-scale 2D predictive models which can efficiently reason the characteristics of large and sophisticated multi-core oriented architectures during the design space exploration stage without using detailed cycle-level simulations. Our proposed techniques employ 2D wavelet multiresolution analysis and neural network regression modeling. We extensively evaluate the efficiency of our predictive models in forecasting the complex and heterogeneous characteristics of large and distributed shared cache interconnected by a network on chip in multi-core designs using both multi-programmed and multithreaded workloads. Experimental results show that the models achieve high accuracy while maintaining low complexity and computation overhead. Through case studies, we demonstrate that the proposed techniques can be used to informatively explore and accurately evaluate global, cooperative multi-core resource allocation and thermal-aware designs that cannot be achieved using conventional design exploration methods.

关键词： Space exploration Predictive models Network-on-a-chip design methodology Microprocessors Time to market Large-scale systems Analytical models Wavelet analysis Multiresolution analysis

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Using Analytical Models to Efficiently Explore Hardware Transactional Memory and Multi-Core Co-design

Using Analytical Models to Efficiently Explore Hardware Tran...

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International Symposium on computer architecture and High Performance Computing (SBAC-PAD)

作者： James Poe Chang-Burm Cho Tao Li Intelligent Design of Efficient Architecture Lab (IDEAL) Department of Electrical and Computer Engineering University of Florida USA

Transactional memory is emerging as a parallel programming paradigm for multi-core processors. Despite the recent interest in transactional memory, there has been no study to characterize the interaction between hardware transactional memory (HTM) design dimensions and multi-core microarchitecture configuration. In this paper, we investigate the use of analytical modeling techniques to build application-specific performance models for understanding the interaction between HTM and multi-core configurations across large design points and for efficiently exploring the co-design space between the two. A key feature of our modeling technique is the ability to simultaneously capture the individual and combinatorial effects of important HTM design dimensions and core microarchitectural parameters. We show that analytical models can be effective tools for assisting architects in identifying these key effects and the interactions between HTM and multi-core microarchitecture that have a high impact on the performance of transactional memory workloads. The models also enable accurate performance prediction across the joint TM/multi-core design space. By analyzing the regression trees generated from our neural network model building methods, we further reveal heterogeneous interaction between TM workloads, core microarchitectures and TM mechanisms.

关键词： Analytical models Hardware Microarchitecture Space exploration Parallel programming Multicore processing Performance analysis Predictive models Regression tree analysis Neural networks

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Reports of the AAAI 2008 Spring Symposia

Reports of the AAAI 2008 Spring Symposia

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作者： Balduccini, Marcello Baral, Chitta Brodaric, Boyan Colton, Simon Fox, Peter Gutelius, David Hinkelman, Knut Horswill, Ian Huberman, Bernardo Hudlicka, Eva Lerman, Kristina Lisetti, Christine McGuinness, Deborah Maher, Mary Lou Musen, Mark A. Sahami, Mehran Sleeman, Derek Thönssen, Barbara Velasquez, Juan Ventura, Dan Eastman Kodak Company Arizona State University Tempe AZ United States Geological Survey of Canada Department of Computing Imperial College London United Kingdom National Center for Atmospheric Research Artificial Intelligence Center SRI International Menlo Park CA United States University of Applied Sciences Zurich Switzerland Department of Computer Science Northwestern University Evanston IL United States Social Computing Lab. Hewlett-Packard Laboratories Psychometric Associates USC Information Sciences Institute University of Southern California Los Angeles CA United States Computer Science Department University of Southern California Los Angeles CA United States School of Computing and Information Sciences Florida International University Miami FL United States Rensselaer Polytechnic Institute Information and Intelligent Systems Division National Science Foundation University of Sydney Sydney NSW Australia Faculty of Architecture Design and Planning University of Sydney Sydney NSW Australia Department of Medicine Biomedica Informatics Research Department Stanford University Stanford CA United States Computer Science Department Stanford University Stanford CA United States Department of Computing Science University of Aberdeen Aberdeen United Kingdom MIT CSAIL Department of Computer Science Brigham Young University Provo UT United States

The Association for the Advancement of Artificial Intelligence (AAAI) was pleased to present the AAAI 2008 Spring Symposium Series, held Wednesday through Friday, March 26-28, 2008, at Stanford University, California. The eight symposia were titled (1) AI Meets Business Rules and Process Management, (2) architectures for Intelligent Theory-Based Agents, (3) Creative Intelligent Systems, (4) Emotion, Personality, and Social Behavior, (5) Semantic Scientific Knowledge Integration, (6) Social Information Processing, (7) Symbiotic Relationships between Semantic Web and Knowledge Engineering, (8) Using Al to Motivate Greater Participation in computer Science. The goal of the AI Meets Business Rules and Process Management AAAI symposium was to investigate the various approaches and standards to represent business rules, business process management, and the semantic web with respect to expressiveness and reasoning capabilities. The focus of the architectures ror Intelligent Theory-Based Agents AAAI symposium was the definition or architectures for intelligent theory-based agents, comprising languages, knowledge representation methodologies, reasoning algorithms, and control loops. The Creative Intelligent Systems symposium included five major discussion sessions and a general poster session (in which all contributing papers were presented). The purpose of this symposium was to explore the synergies between creative cognition and intelligent systems. The goal of the Emotion, Personality, and Social Behavior symposium was to examine fundamental issues in affect and personality in both biological and artificial agents, focusing on the roles of these factors in mediating social behavior. The Semantic Scientific Knowledge Integration symposium brought together the semantic technologies community with the scientific information technology community in an effort to build the general semantic science information community. The Social Information Processing symposium's goal was to

关键词： Knowledge representation

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'Smart' housing for the elderly: Understanding perceptions and biases of rural America

'Smart' housing for the elderly: Understanding perceptions a...

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ACADIA 2007 Conference on Expanding Bodies: Art, Cities and Environment

作者： Satpathy, Lalatendu Mathew, Anijo Punnen Human-Computer Interaction Institute Carnegie Mellon University United States Design Research and Informatics Lab. College of Architecture Art and Design Mississippi State University United States

ISBN: (纸本)9780978097868

It is commonly acknowledged that 'smart' environments, interactive architecture and 'smart' homes will defi ne the next cutting edge in architectural research. Most critics agree that one of the fi rst problems that 'smart' homes will help to address is that of spiraling costs of healthcare and aging-in-place. This may be true for urban settings where there is the fi nancial feasibility for such technologies but what about rural America? It has been conclusively proven that rural America suffers from a lack of healthcare (delivery and access). Prior research (Mathew 2005) has also established that a rural home is different from an urban home. Will technologies designed for the urban home work in a rural setting? And do rural people carry the same attitudes and biases towards technology? This paper continues our research in the design of 'smart' rural environments. It summarizes fi ndings from focus group studies conducted in rural communities that help us to understand attitudes of people towards 'smart' technology. We will use these fi ndings to examine the feasibility of ubiquitous computing and 'smart' spaces in rural areas. In conclusion, we will present guidelines to help designers in the creation of technology to augment healthy aging in rural home settings.

关键词： Smart homes

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Space-time-frequency processing for OFDM wireless mobile communications

Space-time-frequency processing for OFDM wireless mobile com...

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IEEE Conference on Vehicular Technology (VTC)

作者： Byung-Chul Kim I-Tai Lu System Architecture Design Lab TN Business Samsung Electronics Company Limited Suwon Gyeonggi South Korea Department of Electrical and Computer Engineering Polytechnic University Melville NY USA

Novel space-time-frequency processing schemes for OFDM mobile communication systems are implemented using antenna arrays, tap delay lines and Doppler branches to exploit angular spread, delay spread and Doppler spread... 详细信息

ISBN: (纸本)0780377575

关键词： OFDM Wireless communication Mobile communication Fading Delay effects Antenna arrays Sampling methods Degradation Bit error rate Aperture antennas

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Doppler diversity for OFDM wireless mobile communications. Part II: time-frequency processing

Doppler diversity for OFDM wireless mobile communications. P...

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IEEE Conference on Vehicular Technology (VTC)

A novel time-frequency processing scheme is developed to exploit Doppler diversity of time varying multipath channel for OFDM mobile communication systems. Extensive simulations show that the proposed time-frequency M... 详细信息

ISBN: (纸本)0780377575

关键词： OFDM Wireless communication Mobile communication Time frequency analysis Fading Frequency diversity Finite impulse response filter Statistics Bit error rate Signal generators

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Circuit partitioning for efficient logic BIST synthesis

Circuit partitioning for efficient logic BIST synthesis

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design, Automation and Test in Europe Conference and Exhibition

作者： A. Irion G. Kiefer H. Vranken H.-J. Wunderlich Computer Architecture Lab University of Stuttgart Stuttgart Germany IC Design - Digital Design & Test Philips Research Laboratories Eindhoven AA The Netherlands

ISBN: (纸本)0769509932

A divide-and-conquer approach using circuit partitioning is presented, which can be used to accelerate logic BIST synthesis procedures. Many BIST synthesis algorithms contain steps with a time complexity which increases more than linearly with the circuit size. By extracting sub-circuits which are almost constant in size, BIST synthesis for very large designs may be possible within linear time. The partitioning approach does nor require any physical modifications of the circuit under test. Experiments show that significant performance improvements can be obtained at the cost of a longer test application time or a slight increase in silicon area for the BIST hardware.

关键词： Logic circuits Built-in self-test Circuit synthesis Circuit testing Logic testing Costs Integrated circuit testing Silicon Hardware Logic design

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Circuit partitioning for efficient logic BIST synthesis 01

Circuit partitioning for efficient logic BIST synthesis

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Proceedings of the conference on design, automation and test in Europe

作者： A. Irion G. Kiefer H. Vranken H. Wunderlich Computer Architecture Lab University of Stuttgart Breitwiesenstr. 20/22 70565 Stuttgart Germany Philips Research Laboratories IC Design - Digital Design & Test Prof. Holstlaan 4 5656 AA Eindhoven The Netherlands

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Near-optimum hierarchical layout synthesis of two-dimensional CMOS cells

Near-optimum hierarchical layout synthesis of two-dimensiona...

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International Conference on VLSI design

作者： A. Gupta J.P. Hayes Cadence Design Systems Inc. San Jose CA USA Advanced Computer Architecture Lab Dept of EECS University of Michigan Ann Arbor MI USA

We present a hierarchical technique HCLIP to generate near-optimum layouts of CMOS cells in the two-dimensional (2-D) style. HCLIP is based on integer-linear programming and extends our previously published CLIP technique to much larger cells and to 2-D cell-arrays. HCLIP partitions the circuit into clusters, generates minimum-width 1-D placements (chain covers) for each cluster and then selects one cover for each cluster such that the overall 2-D cell width and height is minimized. In doing so, HCLIP explores all diffusion sharing between transistor chains belonging to the selected covers. For width minimization, HCLIP yields 2-D layouts that have minimum width with respect to the given set of covers. For both width and height minimization, since HCLIP is approximate and can overestimate cell height, we analyze the theoretical worst-case approximation. Experimental results demonstrate that HCLIP still yields near-optimal layouts in most cases.

关键词： Minimization Wires Bridge circuits computer architecture Inverters

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