Distributed synchronization for parallel simulation is generally classified as being either optimistic or conservative. While considerable investigations have been conducted to analyze and optimize each of these synch...
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Distributed synchronization for parallel simulation is generally classified as being either optimistic or conservative. While considerable investigations have been conducted to analyze and optimize each of these synchronization strategies, very little study on the definition and strictness of causality have been conducted. Do we really need to preserve causality in all types of simulations? This paper attempts to answer this question. We argue that significant performance gains can be made by reconsidering this definition to decide if the parallel simulation needs to preserve causality. We investigate the feasibility of unsynchronized parallel simulation through the use of several queuing model simulations and present a comparative analysis between unsynchronized and Time Warp simulation.
The SAVANT, QUEST II, and HEPE research programs at the University of Cincinnati include the development and distribution of VHDL analysis and simulation capabilities. These capabilities are being freely distributed f...
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The SAVANT, QUEST II, and HEPE research programs at the University of Cincinnati include the development and distribution of VHDL analysis and simulation capabilities. These capabilities are being freely distributed for non-commercial use. The SAVANT project is underway specifically to develop a VHDL analyzer with a well-documented, extensible intermediate form;the main objective is to smooth the integration of VHDL technology into university and industrial research programs. The SAVANT project is funded through the Air Force SBIR program and is a joint activity between the University of Cincinnati and MTL Systems, Inc. The QUEST II program is investigating parallel algorithms and architectures for simulation, behavioral synthesis, and ATPG. The HEPE program is investigating (in part) novel strategies for relaxing causal orders in the parallel simulation of active networks. As part of the QUEST II/HEPE simulation activities, a VHDL simulation kernel is being developed that will operate with the SAVANT intermediate form for sequential or parallel execution of VHDL models (a C++ code generator from the SAVANT intermediate is being jointly developed by the SAVANT and QUEST II programs). All of the software from the QUEST and HEPE simulation programs is freely available for use (commercial or otherwise).
A framework for performance analysis of parallel discrete event simulators is presented. The center-piece of this framework is a platform-independent Workload Specification Language (WSL). WSL is a language that allow...
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A framework for performance analysis of parallel discrete event simulators is presented. The center-piece of this framework is a platform-independent Workload Specification Language (WSL). WSL is a language that allows the characterization of simulation models using a set of fundamental performance-critical parameters. WSL also implements a facility for representing real models. For each simulator to be tested, a WSL translator is used to generate synthetic platform-specific simulation models that conform to the performance characteristics captured by the WSL description. Accordingly, sets of portable simulation models that explore the effects of the different parameters, individually or collectively, on the performance can be constructed. The construction of the workload simulation models is assisted using a Synthetic Workload Generator (SWG). The utility of the system is demonstrated with the generation of a representative set of experiments. The described framework can be used to create a standard benchmark suite that consists of a mixture of real simulation models, selected from different application domains, and synthetic models generated by SWG.
We address the problem of CMOS cell width minimization in the general two-dimensional (2-D) layout style and propose a novel technique based on integer linear programming (ILP) to solve it exactly. We formulate a 0-1 ...
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ISBN:
(纸本)9780818675973
We address the problem of CMOS cell width minimization in the general two-dimensional (2-D) layout style and propose a novel technique based on integer linear programming (ILP) to solve it exactly. We formulate a 0-1 ILP model whose solution minimizes cell width along with the routing complexity across the diffusion rows. We present experimental results that evaluate the performance of two ILP solvers that have very different solution methods, and assess the effect of the number of rows on cell width. Run-times for optimal layouts are in seconds for cells with up to 20 transistors. For larger cells, we propose a practical circuit pre-processing scheme that dramatically reduces the run time with little or no loss in optimality.
This paper presents a formal model of the dynamic semantics of VHD Lusing interval temporal logic. The model uses a declarative style that provides a semantic definition of VHDL independent of the VHDL simulation cycl...
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Besides a formal syntax definition, few formal semantic models for HDLs are ever constructed. This paper reports our efforts to construct formal models for the hardware description language VHDL. In particular, a stat...
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Besides a formal syntax definition, few formal semantic models for HDLs are ever constructed. This paper reports our efforts to construct formal models for the hardware description language VHDL. In particular, a static model for VHDL that addresses well-formedness, static equivalences, and static rewriting is presented. A rewriting algebra is presented that defines a set of transforms that allow the rewriting of VHDL descriptions into a reduced form. The dynamic semantics is under development and the reductions attained by the rewriting algebra have greatly simplified the language constructs that the dynamic semantics have to characterize.
‘Inclusive designing’ presents the proceedings of the seventh Cambridge Workshop on Universal Access and Assistive Technology (CWUAAT '14). It represents a unique multi-disciplinary workshop for the Inclusive De...
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ISBN:
(数字)9783319050959
ISBN:
(纸本)9783319050942;9783319357386
‘Inclusive designing’ presents the proceedings of the seventh Cambridge Workshop on Universal Access and Assistive Technology (CWUAAT '14). It represents a unique multi-disciplinary workshop for the Inclusive design Research community where designers, computer scientists, engineers, architects, ergonomists, policymakers and user communities can exchange ideas. The research presented at CWUAAT '14 develops methods, technologies, tools and guidance that support product designers and architects to design for the widest possible population for a given range of capabilities, within a contemporary social and economic context. In the context of developing demographic changes leading to greater numbers of older people and people with disabilities, the general field of Inclusive design Research strives to relate the capabilities of the population to the design of products. Inclusive populations of older people contain a greater variation in sensory, cognitive and physical user capabilities. These variations may be co-occurring and rapidly changing leading to a demanding design environment. Recent research developments have addressed these issues in the context of: governance and policy; daily living activities; the workplace; the built environment, Interactive Digital TV and Mobile communications. Increasingly, a need has been identified for a multidisciplinary approach that reconciles the diverse and sometimes conflicting demands of design for Ageing and Impairment, Usability and Accessibility and Universal Access. CWUAAT provides a platform for such a need. This book is intended for researchers, postgraduates, design practitioners, clinical practitioners, and design teachers.
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