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CLIP: an optimizing layout generator for two-dimensional CMOS cells 97

CLIP: an optimizing layout generator for two-dimensional CMO...

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Proceedings of the 34th annual design Automation Conference

作者： Avaneendra Gupta John P. Hayes Advanced Computer Architecture Laboratory Dept. of EECS University of Michigan Ann Arbor MI and Design Technology Intel Corporation 2200 Mission College Blvd. Santa Clara CA Advanced Computer Architecture Laboratory Dept. of EECS University of Michigan Ann Arbor MI

ISBN: (纸本)9780897919203

We present a novel technique CLIP for optimizing both theheight and width of CMOS cell layouts in the two-dimensional (2-D) style. CLIP is based on integer-linear programming (ILP) and proceeds in two stages: First, an ILP model is used to determine a 2-D layout of minimum width W cell . Then, another model generatesa 2-D layout that has width W cell and requires a minimumnumber of routing tracks. Run times are in seconds for circuitswith up to 16 transistors. For larger circuits, we extend CLIP to ahierarchical method HCLIP that places series-connected transistorscontiguously. This reduces run times by up to three orders ofmagnitude, and still yields optimal results in over 80% of cases.

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A hierarchical technique for minimum-width layout of two-dimensional CMOS cells

A hierarchical technique for minimum-width layout of two-dim...

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International Conference on VLSI design

作者： A. Gupta J.P. Hayes Advanced Computer Architecture Laboratory Department of EECS University of Michigan Ann Arbor MI USA Design Technology Intel Corporation Santa Clara CA USA

We present a hierarchical technique, based on integer linear programming (ILP), to generate area-efficient layouts of relatively large complex CMOS cells in the two-dimensional (2-D or multi-row) style. First, the CMOS circuit is partitioned into subcircuits called clusters. Next, the set of all minimum-width 1-D placements (chain covers) are generated for each cluster and form the input to the ILP model. The model aims at selecting exactly one cover for each cluster such that the overall 2-D cell width is minimized. In the process, all possible diffusion sharing between transistor chains belonging to clusters are considered; the inter-row connections that contribute to the overall cell width are also reduced. Experimental results demonstrate that the technique reduces run times by several orders of magnitude over non-hierarchical methods, and yields optimal or near-optimal layouts in most cases.

关键词： Circuits Integer linear programming Semiconductor device modeling Minimization computer architecture Productivity Optimization methods Educational institutions Logic gates Very large scale integration

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Optimistic fossil collection for time warp simulation 29

Optimistic fossil collection for time warp simulation

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29th Hawaii International Conference on System Sciences, HICSS 1996

作者： Young, Christopher H. Wilsey, Philip A. Computer Architecture Design Laboratory Dept. of ECECS PO Box 210030 CincinnatiOH45221-0030 United States

ISBN: (纸本)0818673249

Optimistic Fossil Collection is a fully distributed mechanism to reclaim memory from the state and event histories of a Time Warp simulation. Each fossil collector executes with a Logical Process (LP) and operates independently of other fossil collectors. More precisely, each fossil collector examines event arrival times and creates a statistical model of the expected variance from LVT. From this model, it is possible to determine the probability that the LP will, in the future, rollback distance X from LVT. Thus, the fossil collector can examine the time-stamps of items in the state and event histories to find the probability that they will be needed in the future. Comparing this probability against a user-specified risk factor, the fossil collector decides if the item can be marked as a fossil and scavenged. Optimistic fossil collection does, however, allow for the possibility for simulation jail-ure. Consequently, it may be desirable to periodically have complete checkpoints taken and archived during the simulation for possible restart with a smaller risk factor specified. This method of memory management assumes that there is an underlying stationary distribution for the rollback lengths during a time interval t. This is a reasonable assumption since empiricalstudies have shown that rollback lengths in Time Warp are relatively constant in length. This assumption can, however, also be relaxed and models that operate without an underlying assumption about the distribution of rollback lengths. This paper reviews the design and implementation of two rollback models for optimistic fossil collection. The first assumes a geometrically distributed rollback length;the second assumes an arbitrary distribution of rollback lengths with fixed mean and variance. An implementation of the mechanism is also reported that describes our experiences with one im- © 1996 IEEE

关键词： Probability

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Formal specification and verification of the pGVT algorithm 3rd

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3rd International Symposium of Formal Methods Europe, FME 1996

作者： Kannikeswaran, Balakrishnan Radhakrishnan, Radharamanan Frey, Peter Alexander, Perry Wilsey, Philip A. Computer Architecture Design Laboratory Dept of ECECS University of Cincinnati PO Box 210030 CincinnatiOH45221-0030 United States

ISBN: (纸本)9783540609735

The time warp mechanism is a technique for optimistically synchronizing Parallel and distributed Discrete Event-driven Simulators (PDES). Within this synchronization paradigm lie numerous parallel algorithms, chief among them being an estimation of the Global Virtual Time (GVT) value for fossil collection and output commit. Because the optimistic synchronization strategy allows for temporary violations of causal relations in the system being simulated, developing algorithms that correctly estimate GVT can prove extremely difficult. Testing and debugging can also prove difficult as error situations are frequently not repeatable due to varying load conditions and processing orders. Consequently, the application of formal methods to develop and analyze such algorithms are of extreme importance. This paper addresses the application of formal methods for the development of GVT estimation algorithms. More precisely, the paper presents a formal specification for and verification of one specific GVT estimation algorithm, the pGVT algorithm. The specifications are presented in the Larch Shared Language and verification completed using the Larch Proof Assistant. The ultimate goal of this work is to develop a reusable infrastructure for GVT proof development that can be used by developers of new GVT estimation algorithms. © Springer-Verlag Berlin Heidelberg 1996.

关键词： Formal specification

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Optimistic fossil collection for time warp simulation

Optimistic fossil collection for time warp simulation

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Annual Hawaii International Conference on System Sciences (HICSS)

作者： C.H. Young P.A. Wilsey Department of ECECS Computer Architecture Design Laboratory Cincinnati OH USA

Optimistic fossil collection (OFC) is a fully-distributed mechanism to reclaim memory from the state and event histories of a time warp simulation. Each fossil collector executes with a logical process (LP) and operates independently of other fossil collectors. Each one examines event arrival times and creates a statistical model of the expected variance from local virtual time (LVT). From this, it is possible to determine the probability that the LP will, in the future, rollback a distance X from LVT. Thus, the fossil collector can examine the time-stamps of items in the state and event histories to find the probability that they will be needed in the future. Comparing this probability against a user-specified risk factor, the fossil collector decides if the item can be marked as a fossil and scavenged. OFC allows for the possibility for simulation failure, so it may be desirable to periodically have complete checkpoints taken and archived during the simulation for a possible restart with a smaller risk factor specified. This method of memory management assumes there is an underlying stationary distribution for the rollback lengths during a time interval t. This is reasonable, since rollback lengths in time warp are relatively constant in length. This assumption can be relaxed for models that operate without an underlying assumption about the distribution of rollback lengths. This paper reviews the design and implementation of two rollback models for OFC. One assumes a geometrically distributed rollback length; the other assumes an arbitrary distribution of rollback lengths with fixed mean and variance.

关键词： Time warp simulation History Discrete event simulation Probability design optimization computer architecture Laboratories Memory management Contracts Sorting

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A comparative analysis of various Time Warp algorithms implemented in the WARPED simulation kernel

A comparative analysis of various Time Warp algorithms imple...

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Annual Symposium on Simulation

作者： R. Radhakrishnan T.J. McBrayer K. Subramani M. Chetlur V. Balakrishnan P.A. Wilsey Department of Ececs Computer Architecture Design Laboratory Cincinnati OH USA

The Time Warp mechanism conceptually has the potential to speedup discrete event simulations on parallel platforms. However, practical implementations of optimistic mechanism have been hindered by several drawbacks, such as large memory usage, excessive rollbacks (instability), and wasted lookahead computation. Several optimizations and variations to the original Time Warp algorithm have been presented in the literature to optimistically synchronize parallel discrete event simulation. This paper uses a common simulation environment to present comparative performance results of several Time Warp optimizations in two different application domains, namely queuing model simulation and digital system simulation. The particular optimizations considered are: lowest-timestamp-first (LTSF) scheduling, periodic (fixed period) checkpointing, dynamic checkpointing, lazy cancellation and dynamic cancellation.

关键词： Algorithm design and analysis Analytical models Time warp simulation Kernel Discrete event simulation Computational modeling Digital systems Checkpointing Project management computer simulation

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High-level test generation using symbolic scheduling

High-level test generation using symbolic scheduling

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IEEE International Test Conference

作者： M.C. Hansen J.P. Hayes Design Automation Operations Integrated Circuit Design Center Delco Electronics Corporation Kokomo IN USA Advanced Computer Architecture Laboratory Advanced Computer Architecture Laborator University of Michigan Ann Arbor MI USA

A high-level test generation algorithm SWIFT is proposed which incorporates a symbolic scheduling procedure, derived from high-level synthesis applications, to resolve decision conflicts during test generation. SWIFT uses the induced fault model to generate functional tests that guarantee detection of low-level structural faults. When applied to functional models of representative 74 X-series, ISCAS-85 and ISCAS-89 circuits. SWIFT produces test sequences that cover all gate-level stuck-at-faults. Surprisingly, although they are derived from a high-level functional description of the circuit under test, most of these test sequences are of provably minimal or near-minimal size.

关键词： Circuit testing Circuit faults Integrated circuit modeling Electronic equipment testing Logic testing Integrated circuit testing Automatic test pattern generation Sequential analysis Sequential circuits Clocks

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System modeling, performance analysis, and evolutionary prototyping with hardware description languages 3

System modeling, performance analysis, and evolutionary prot...

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3rd International Workshop on Modeling, Analysis, and Simulation of computer and Telecommunication Systems, MASCOTS 1995

作者： Mohanty, S. Krishnaswamy, V. Wilsey, P.A. Dept. of Electr. and Comput. Eng. Computer Architecture Design Laboratory Department of ECE Univ. of Cincinnati PO Box 210030 CincinnatiOH45221-0030 United States University of Illinois UrbanaIL United States

ISBN: (纸本)0818669020

Performance modeling, simulation and analysis of the system behavior through virtual prototyping, form the core steps of the system design process. Past CAD support to link the high level conceptual modeling phase with the implementation phase has been virtually non-existent. In this paper, we describe our work to use VHDL to build design libraries that support conceptual modeling. These library components can be instantiated for rapid prototyping, simulation, and performance analysis. They include high level structures to allow construction of system models containing both interpreted and uninterpreted components. This helps in creating a strong design environment in VHDL which can support the entire design cycle. In addition, the design libraries have been linked with a graphical design environment. This graphical environment provides a single framework in which the designer can (i) build the design, (ii) simulate the design for correctness, and (iii) visualize performance results and capacity measures. © 1995 IEEE.

关键词： computer hardware description languages

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System modeling, performance analysis, and evolutionary prototyping with hardware description languages

System modeling, performance analysis, and evolutionary prot...

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International Symposium on Modeling, Analysis and Simulation of computer and Telecommunication Systems (MASCOTS)

作者： S. Mohanty V. Krishnaswamy P.A. Wilsey Computer Architecture Design Laboratory Department of ECE University of Cincinnati Cincinnati OH USA University of Illinois Urbana IL USA

关键词： Performance analysis Prototypes Hardware design languages Virtual prototyping Libraries Analytical models Power system modeling Switches Joining processes Queueing analysis

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Rapid system prototyping, system modeling, and analysis in a hardware-software codesign environment

Rapid system prototyping, system modeling, and analysis in a...

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International Workshop on Rapid System Prototyping (RSP)

作者： S. Mohanty P.A. Wilsey AT and T Bell Laboratories Inc. Allentown PA USA Department of ECECS Computer Architecture Design Laboratory Cincinnati OH USA

A hardware-software codesign environment provides the designer with an environment in which the designer can concurrently develop the hardware and software components of the system to satisfy a given set of performance and design constraints. As a design evolves from the conceptual level model of the hardware-software system, to the final implementation, the design progresses through a number of design steps and design environments. There exists a need for a single uniform design environment for specifying design information as it develops. In this paper, we describe our work to use VHDL to build design libraries that support rapid system prototyping and conceptual modeling as software components. Furthermore, the design libraries have been linked with a graphical codesign environment. This graphical environment provides a single framework in which the designer can (i) build the design, (ii) simulate the design for correctness, and (iii) visualize performance results and capacity measures.

关键词： Software prototyping Modeling Hardware Software libraries Software performance Prototypes computer architecture Process design Monitoring Contracts

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