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International Symposium on Modeling, Analysis and Simulation of computer and Telecommunication Systems (MASCOTS)

作者： S. Mohanty V. Krishnaswamy P.A. Wilsey Computer Architecture Design Laboratory Department of ECE University of Cincinnati Cincinnati OH USA University of Illinois Urbana IL USA

Performance modeling, simulation and analysis of the system behavior through virtual prototyping, form the core steps of the system design process. Past CAD support to link the high level conceptual modeling phase with the implementation phase has been virtually non-existent. In this paper, we describe our work to use VHDL to build design libraries that support conceptual modeling. These library components can be instantiated for rapid prototyping, simulation, and performance analysis. They include high level structures to allow construction of system models containing both interpreted and uninterpreted components. This helps in creating a strong design environment in VHDL which can support the entire design cycle. In addition, the design libraries have been linked with a graphical design environment. This graphical environment provides a single framework in which the designer can (i) build the design, (ii) simulate the design for correctness, and (iii) visualize performance results and capacity measures.< >

关键词： Performance analysis Prototypes Hardware design languages Virtual prototyping Libraries Analytical models Power system modeling Switches Joining processes Queueing analysis

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Rapid system prototyping, system modeling, and analysis in a hardware-software codesign environment

Rapid system prototyping, system modeling, and analysis in a...

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International Workshop on Rapid System Prototyping (RSP)

作者： S. Mohanty P.A. Wilsey AT and T Bell Laboratories Inc. Allentown PA USA Department of ECECS Computer Architecture Design Laboratory Cincinnati OH USA

A hardware-software codesign environment provides the designer with an environment in which the designer can concurrently develop the hardware and software components of the system to satisfy a given set of performance and design constraints. As a design evolves from the conceptual level model of the hardware-software system, to the final implementation, the design progresses through a number of design steps and design environments. There exists a need for a single uniform design environment for specifying design information as it develops. In this paper, we describe our work to use VHDL to build design libraries that support rapid system prototyping and conceptual modeling as software components. Furthermore, the design libraries have been linked with a graphical codesign environment. This graphical environment provides a single framework in which the designer can (i) build the design, (ii) simulate the design for correctness, and (iii) visualize performance results and capacity measures.

关键词： Software prototyping Modeling Hardware Software libraries Software performance Prototypes computer architecture Process design Monitoring Contracts

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POST-CONFERENCE REPORT - 1994 SIMULATION MULTICONFERENCE

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SIMULATION 1994年第6期62卷 392-393页

作者： WILSEY, PA Computer Architecture Design Laboratory University of Cincinnati Cincinnati Ohio 45221-0030

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Composing functional unit blocks for efficient interpretation of MIMD code sequences on SIMD processors 3rd

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3rd Joint International Conference on Vector and Parallel Processing, CONPAR 1994 - VAPP VI

作者： Bagley, Ross A. Wilsey, Philip A. Abu-Ghazaleh, Nael B. Computer Architecture Design Laboratory Dept of ECE University of Cincinnati PO Box 210030 CincinnatiOH United States

ISBN: (纸本)9783540584308

The branching regions of data-parallel programs can lead to serial execution on a SIMD processor. However, recent investigations show that these branching regions can be compiled into instruction se-quences that are placed in the Processing Element (PE) memories for interpretation. Thus, when the branching region is reached, the control unit of the SIMD processor executes an instruction interpreter that causes the concurrent execution (through interpretation) of the branch-ing code at each PE. Interpretation incurs some overhead and therefore, it is necessary to carefully design the instruction set to be interpreted. In this paper, we present a software architecture called Compose with 9 functional units and show that these functional units can be composed together to realize (at least) 42 distinct useful instructions. Thus, each iteration of the interpreter loop pays only the overhead of broadcasting execution orders for a few operations and yet manages to interpret (in parallel) a much larger set of operations. © Springer-Verlag Berlin Heidelberg 1994.

关键词： Concurrency control

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Predicting the drape of woven cloth using interacting particles 94

Predicting the drape of woven cloth using interacting partic...

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21st Annual Conference on computer Graphics and Interactive Techniques, SIGGRAPH 1994

作者： Breen, David E. House, Donald H. Wozny, Michael J. European Computer-Industry Research Centre Design Research Center Rensselaer Polytechnic Institute Arabellastrasse 17 MunichD-81925 Germany Visualization Laboratory Texas A and M University Department of Computer Science Williams College College of Architecture College StationTX77843-3137 United States National Institute of Standards and Technology Design Research Center Rensselaer Polytechnic Institute MEL 220/B322 GaithersburgMD20899 United States

ISBN: (纸本)0897916670

We demonstrate a physically-based technique for predicting the drape of a wide variety of woven fabrics. The approach exploits a theoretical model that explicitly represents the microstructure of woven cloth with interacting particles, rather than utilizing a continuum approximation. By testing a cloth sample in a Kawabata fabric testing device, we obtain data that is used to tune the model's energy functions, so that it reproduces the draping behavior of the original material. Photographs, comparing the drape of actual cloth with visualizations of simulation results, show that we are able to reliably model the unique large-scale draping characteristics of distinctly different fabric types. © ACM 1994.

关键词： Weaving

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POST-CONFERENCE REPORT - 1993 WESTERN MULTICONFERENCE ON computer-SIMULATION

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ROBOTICA 1993年第5期11卷 483-483页

作者： WILSEY, PA Computer Architecture Design Laboratory University of Cincinnati Cincinnati Ohio 45221–0030 USA

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The impact of abstract data types on the digital system description and simulation environments

The impact of abstract data types on the digital system desc...

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European Conference on design Automation

作者： N.E. Mause P.A. Wilsey Computer Architecture Design Laboratory Department of Electrical and Computer Engineering University of Cincinnati Cincinnati OH USA NCR Corporation Fort Collins CO USA

Over the years, many features of programming languages have been adopted in the design of hardware description languages (HDLs). The incorporation of facilities to support building abstract data types in HDLs is examined. In particular, the use of abstract data types in VHDL is considered in the description and simulation of digital systems. Furthermore, the user-interface of a VHDL simulator is considered and the question 'are the benefits of abstract data types defeated by a primitive simulator user interface?' is asked. Finally, an extended VHDL package is shown that provides the designer with a mechanism for extending the user interface of an interactive simulator.< >

关键词： Digital systems Hardware design languages User interfaces computer languages Computational modeling Packaging machines computer simulation computer architecture Functional programming Contracts

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computer-SYSTEM architecture CONCEPTS FOR FUTURE COMBAT SYSTEMS

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NAVAL ENGINEERS JOURNAL 1990年第3期102卷 43-62页

作者： ZITZMAN, LH FALATKO, SM PAPACH, JL Dr. Lewis H. Zitzman:is the group supervisor of the Advanced Systems Design Group Fleet Systems Department The Johns Hopkins University Applied Physics Laboratory (JHU/APL). He has been employed at JHU/APL since 1972 performing applied research in computer science and in investigating and applying advanced computer technologies to Navy shipboard systems. He is currently chairman of Aegis Computer Architecture Data Bus and Fiber Optics Working Group from which many concepts for this paper were generated. Dr. Zitzman received his B.S. degree in physics from Brigham Young University in 1963 and his M.S. and Ph.D. degrees in physics from the University of Illinois in 1967 and 1972 respectively. Stephen M. Falatko:was a senior engineering analyst in the Combat Systems Engineering Department Comptek Research Incorporated for the majority of this effort. He is currently employed at ManTech Services Corporation. During his eight-year career first at The Johns Hopkins University Applied Physics Laboratory and currently with ManTech Mr. Falatko's work has centered around the development of requirements and specifications for future Navy systems and the application of advanced technology to Navy command and control systems. He is a member of both the Computer Architecture Fiber Optics and Data Bus Working Group and the Aegis Fiber Optics Working Group. Mr. Falatko received his B.S. degree in aerospace engineering with high distinction from the University of Virginia in 1982 and his M.S. degree in applied physics from The Johns Hopkins University in 1985. Mr. Falatko is a member of Tau Beta Pi Sigma Gamma Tau the American Society of Naval Engineers and the U.S. Naval Institute. Janet L. Papach:is a section leader and senior engineering analyst in the Combat Systems Engineering Department Comptek Research Incorporated. She has ten years' experience as an analyst supporting NavSea Spa War and the U.S. Department of State. She currently participates in working group efforts under Aegis Combat System Doctrin

This paper sets forth computer systems architecture concepts for the combat system of the 2010–2030 timeframe that satisfy the needs of the next generation of surface combatants. It builds upon the current Aegis computer systems architecture, expanding that architecture while preserving, and adhering to, the Aegis fundamental principle of thorough systems engineering, dedicated to maintaining a well integrated, highly reliable, and easily operable combat system. The implementation of these proposed computer systems concepts in a coherent architecture would support the future battle force capable combat system and allow the expansion necessary to accommodate evolutionary changes in both the threat environment and the technology then available to effectively counter that threat. Changes to the current Aegis computer architecture must be carefully and effectively managed such that the fleet will retain its combat readiness capability at all times. This paper describes a possible transition approach for evolving the current Aegis computer architecture to a general architecture for the future. The proposed computer systems architecture concepts encompass the use of combinations of physically distributed, microprocessor-based computers, collocated with the equipment they support or embedded within the equipment itself. They draw heavily on widely used and available industry standards, including instruction set architectures (ISAs), backplane busses, microprocessors, computer programming languages and development environments, and local area networks (LANs). In this proposal, LANs, based on fiber optics, will provide the interconnection to support system expandability, redundancy, and higher data throughput rates. A system of cross connected LANs will support a high level of combat system integration, spanning the major warfare areas, and will facilitate the coordination and development of a coherent multi-warfare tactical picture supporting the future combatant command st

关键词： computer architecture

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THE HYBRID EDGE - A TOPOLOGICAL DATA STRUCTURE FOR VERTICALLY INTEGRATED GEOMETRIC MODELING

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computer-AIDED design 1989年第3期21卷 130-140页

作者： KALAY, YE Computer-Aided Design and Graphics Laboratory School of Architecture and Environmental Design State University of New York at Buffalo 235 Hayes Hall Buffalo NY 14214 USA

Generalizing the computational geometric support for the representation of designed artefacts over multiple different levels of symbolic abstractions (e.g. sketches, solid modelling, and drafting) is discussed. First, the need for integrating the representation and manipulation of points, lines, polygons, and solids to facilitate design of artefacts at many levels of design abstraction is established. Second, a vertically integrated model that supports the representation and manipulation of points, lines, polygons, and solids without redundancy is presented. The particular roles of the operators and the operands are discussed, along with their hierarchical integration. The utility of the model is demonstrated in performing operations that involve multiple levels of data abstraction, such as splitting solids at a polygon inscribed on their boundary. Finally, a particular implementation of the integrated model is presented. This implementation is based on the hybrid edge, a derivative of Baumgart's winged edge and Eastman's split edge models. The hybrid edge distinguishes between the role of edges as carriers of topological adjacency information and their role as carriers of directionality information. This distinction permits the hybrid edge to handle the different combinations of adjacency and directionality requirements posed by the different abstraction levels in the integrated model.

关键词： geometric modelling data representation hybrid edge

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Fault simulation and test pattern generation at the multiple-valued switch level

Fault simulation and test pattern generation at the multiple...

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IEEE International Test Conference

作者： J.-P. Caisso B. Courtois VLSI Design Laboratory of the Electrical Engineering Dpt. McGill University Montreal Canada IMAG/TIM3-Computer Architecture Group Grenoble France

A fault simulation and test-pattern-generation environment is specified. It includes a multiple-valued algebra, allows the natural treatment of loops and bidirectional devices, and models the physical failures. The authors' main idea is to define what is possible when no extraction to gate level and no creation of transistor groups are performed. Two fault groups are distinguished: the faults which can be modelled in a downward layout, and the faults which can be modelled in an upward verification. This distinction induces difference in the switch network obtained, as the second group allows to model the line resistances.< >

关键词： Switches Test pattern generators Circuit faults Circuit simulation Circuit testing Computational modeling Algebra Semiconductor device modeling Switching circuits computer architecture

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