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APMS 2008 Conference on Innovations in Networks

作者： Huhta, Esko Pöyry-Lassila, Päivi Teräväinen, Helena Staffans, Aija Smeds, Riitta Helsinki University of Technology Department of Computer Science and Engineering SimLab. Finland Department of Architecture Laboratory of Urban Planning and Design Finland

ISBN: (纸本)9789512295470

The purpose of this paper is to explore the collaborative planning and design process of an innovative future school. Our case study examined, modeled, and further developed this planning and design process aiming to create a more wide-ranging place and space for learning than a mere school building We wanted to find out what kind of collaboration and network management would support the participatory planning and design process, and how it would be possible to make children's and youth's opinions visible and to accomplish collaboration in the design process. The case data was collected from a SimLab™ simulation project and architecture workshops. Our findings indicate that that the process of planning and designing innovative future schools require seamless collaboration between various actors and stakeholders, such as architects, pedagogy experts, future school users, and municipal decision makers. Furthermore, the network management aspect should be taken into account to make the collaborative design process more fruitful. Especially, the role of boundary objects was observed to be important both for supporting collaboration and participation in the design process, and for making children 's and youth's opinions visible.

关键词： Network management

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An efficient 0(1) priority queue for large fpga-based discrete event simulations of molecular dynamics

An efficient 0(1) priority queue for large fpga-based discre...

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16th IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM'08

作者： Herbordt, Martin C. Kosie, Francois Model, Josh Computer Architecture and Automated Design Laboratory Department of Electrical and Computer Engineering Boston University Boston MA 02215 United States Teradyne Inc. United States MIT Lincoln Laboratory United States

ISBN: (纸本)9780769533070

Molecular dynamics simulation based on discrete event simulation (DMD) is emerging as an alternative to time-step driven molecular dynamics (MD). Although DMD improves performance by several orders of magnitude, it is still compute bound. In previous work, we found that FPGAs are extremely well suited to accelerating DMD, with speed-ups of 200 to 400 being achieved. Large models, however, are problematic because they require that most predicted events be stored in off-chip memory, rather than on the FPGA. Here we present a solution that allows the priority queue to be extended seamlessly into off-chip memory, resulting in a throughput equal to the hardware-only priority queue, or about 30 faster than the best software-only algorithm. The solution is based on the observation that-when an event is predicted to occur far in the future-not only can its processing be imprecise, but the time when the processing itself occurs can also be substantially delayed. This allows numerous optimizations and restructurings. We demonstrate the resulting design on standard hardware and present the experimental results used to tune the data structures. © 2008 IEEE.

关键词： Dynamic mode decomposition

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architecture of timing synchronization for MIMO-OFDM WLAN systems

Architecture of timing synchronization for MIMO-OFDM WLAN sy...

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2008 4th IEEE International Conference on Circuits and Systems for Communications, ICCSC

作者： Cho, Jongmin Huynh, Trong Anh Kim, Jinsang Cho, Won-Kyung Computer System Architecture and VLSI Design Laboratory Department of Electronics and Radio Engineering Kyung Hee University 1 Seocheon Kihung Yongin Kyungki 449-701 Korea Republic of

ISBN: (纸本)9781424417087

In this paper, we present a timing synchronization scheme of the next generation IEEE 802.11n wireless LAN standard which is based on MIMO-OFDM technique. The proposed timing synchronization method takes two steps which consist of two modified auto-correlators. For coarse timing synchronization, a sliding window differentiator is used after a conventional auto-correlation in order to avoid plateau problem. The conjugate symmetry property of L-LTS is used for fine timing synchronization. Since cross-correlation based methods are not required, the computational complexity and the number of multiplier can be reduced. In order to reduce the hardware complexity, we have used sign comparators (SC) instead of using multipliers. Based on simulation results, the proposed method outperforms a conventional method. The proposed scheme can be applied to IEEE 802.11n systems and can easily be expanded to frequency synchronization scheme. ©2008 IEEE.

关键词： Orthogonal frequency division multiplexing

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Acceleration of a production rigid molecule docking code

Acceleration of a production rigid molecule docking code

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International Conference on Field Programmable Logic and Applications

作者： Bharat Sukhwani Martin C. Herbordt Department of Electrical and Computer Engineering Computer Architecture and Automated Design Laboratory Boston University Boston MA USA

ISBN: (纸本)9781424419609

Modeling the interactions of biological molecules, or docking is critical to both understanding basic life processes and to designing new drugs. Here we describe the FPGA-based acceleration of a recently developed, complex, production docking code. We find that it is necessary to extend our previous 3D correlation structure in several ways, most significantly to support simultaneous computation of several correlation functions. The result is a hundred-fold speed-up of a section of the code that represents over 92% of the original run-time. An additional 4% is accelerated through a previously described method, yielding a total acceleration of almost 25times for typical protein-ligand combinations.

关键词： Correlation Field programmable gate arrays Three dimensional displays Random access memory Electrostatics Arrays Proteins

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An Efficient O(1) Priority Queue for Large FPGA-Based Discrete Event Simulations of Molecular Dynamics

An Efficient O(1) Priority Queue for Large FPGA-Based Discre...

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Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Martin C. Herbordt Francois Kosie Josh Model Computer Architecture and Automated Design Laboratory Department of Electrical and Computer Engineering Boston University Boston MA USA

Molecular dynamics simulation based on discrete event simulation (DMD) is emerging as an alternative to time-step driven molecular dynamics (MD). Although DMD improves performance by several orders of magnitude, it is still compute bound. In previous work, we found that FPGAs are extremely well suited to accelerating DMD, with speed-ups of 200× to 400× being achieved. Large models, however, are problematic because they require that most predicted events be stored in off-chip memory, rather than on the FPGA. Here we present a solution that allows the priority queue to be extended seamlessly into off-chip memory, resulting in a throughput equal to the hardware-only priority queue, or about 30× faster than the best software-only algorithm. The solution is based on the observation that--when an event is predicted to occur far in the future--not only can its processing be imprecise, but the time when the processing itself occurs can also be substantially delayed. This allows numerous optimizations and restructurings. We demonstrate the resulting design on standard hardware and present the experimental results used to tune the data structures.

关键词： Discrete event simulation

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Accelerating multi-core processor design space evaluation using automatic multi-threaded workload synthesis

Accelerating multi-core processor design space evaluation us...

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IEEE International Workshop/Symposium on Workload Characterization

作者： Clay Hughes Tao Li Intelligent Design of Efficient Architecture Laboratory Department of Electrical and Computer Engineering University of Florida USA

The design and evaluation of microprocessor architectures is a difficult and time-consuming task. Although small, hand-coded microbenchmarks can be used to accelerate performance evaluation, these programs lack the complexity to stress increasingly complex architecture designs. Larger and more complex real-world workloads should be employed to measure the performance of a given design or to evaluate the efficiency of various design alternatives. These applications can take days or weeks if run to completion on a detailed architecture simulator. In the past, researchers have applied machine learning and statistical sampling methods to reduce the average number of instructions required for detailed simulation. Others have proposed statistical simulation and workload synthesis techniques, which can produce programs that emulate the execution characteristics of the application from which they are derived but have a much shorter execution period than the original. However, these existing methods are difficult to apply to multi-threaded programs and can result in simplifications that miss the complex interactions between multiple, concurrently running threads. This study focuses on developing new techniques for accurate and effective multi-threaded workload synthesis, which can significantly accelerate architecture design evaluation of multi-core processors. We propose to construct synchronized statistical flow graphs that incorporate inter-thread synchronization and sharing behavior to capture the complex characteristics and interactions of multiple threads. Moreover, we develop thread-aware data reference models and wavelet-based branching models to generate accurate memory access and dynamic branch statistics. Experimental results show that a framework integrated with the aforementioned models can automatically generate synthetic programs that maintain characteristics of original workloads but have significantly reduced runtime.

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Managing multi-core soft-error reliability through utility-driven cross domain optimization

Managing multi-core soft-error reliability through utility-d...

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International Conference on Application Specific Systems (ASAP), architectures and Processors

作者： Wangyuan Zhang Tao Li Intelligent Design of Efficient Architecture Laboratory (IDEAL) Department of Electrical and Computer Engineering University of Florida USA

As semiconductor processing technology continues to scale down, managing reliability becomes an increasingly difficult challenge in high-performance microprocessor design. Transient faults, also known as soft errors, corrupt program data at the circuit level and cause incorrect program execution and system crashes. Future processors will consist of billions of transistors organized as multicore microarchitectures. Packaging multiple cores (and hence more transistors) onto the same die exposes more devices to soft error strikes. This paper explores utility-function-driven (benefit driven) cross domain optimization for both performance and reliability. We propose the use of utility-based resource management for individual cores while applying utility-based shared cache partitioning across multiple cores. Moreover, we coordinate the optimization of multiple resources based on their cross domain utility information to achieve attractive performance and reliability tradeoffs. Extensive experimental results show that, on average, our utility-driven cross domain optimization reduces the soft error rate of the most vulnerable core in a chip multiprocessor (CMP) by up to 35% and improves the CMPpsilas overall reliability by 22% with less than 3% performance degradation across 15 investigated workloads.

关键词： Magnetic cores Reliability Pipelines Resource management Optimization Throughput Joints

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architecture of Timing Synchronization for MIMO-OFDM WLAN Systems

Architecture of Timing Synchronization for MIMO-OFDM WLAN Sy...

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IEEE International Conference on Circuits and Systems for Communications (ICCSC)

作者： Jongmin Cho Huynh Trong Anh Jinsang Kim Won-Kyung Cho Computer System Architecture & VLSI Design Laboratory Department of Electronics and Radio Engineering Kyung Hee University Yongin si Kyunggi South Korea

In this paper, we present a timing synchronization scheme of the next generation IEEE *** wireless LAN standard which is based on MIMO-OFDM technique. The proposed timing synchronization method takes two steps which consist of two modified auto-correlators. For coarse timing synchronization, a sliding window differentiator is used after a conventional auto-correlation in order to avoid plateau problem. The conjugate symmetry property of L-LTS is used for fine timing synchronization. Since cross-correlation based methods are not required, the computational complexity and the number of multiplier can be reduced. In order to reduce the hardware complexity, we have used sign comparators (SC) instead of using multipliers. Based on simulation results, the proposed method outperforms a conventional method. The proposed scheme can be applied to IEEE 802.1 In systems and can easily be expanded to frequency synchronization scheme.

关键词： Timing Wireless LAN Frequency synchronization OFDM Autocorrelation Hardware MIMO computer architecture Very large scale integration Laboratories

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Editorial: Dependability and security

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IEEE Transactions on Dependable and Secure Computing 2008年第1期5卷 1-3页

作者： Iyer, Ravishankar K. Gligor, Virgil D. Kalbarczyk, Zbigniew T. Kanoun, Karama Katzenbeisser, Stefan Mukherjee, Shubu Shieh, Shiuhpyng Zorian, Yervant Department of Electrical and Computer Engineering Carnegie Mellon University Microsoft's Trusted Computing Academic Advisory Board Center for Reliable and High-Performance Computing Coordinated Science Laboratory University of Illinois Urbana-Champaign United States IEEE IEEE Computer Society LAAS CNRS IFIP Working Group 10.4 on Dependable Computing and Fault Tolerance Special Interest Group on Dependability Benchmarking IFIP Working Group 10.4 French SEE Technical Committee on Trustworthy Computer Systems SEE Working Group Design and Validation for Dependability Technical University Munich Germany Darmstadt University of Technology ACM IACR Intel's SER Tech Council Intel's Architecture Patent Committee Taiwan Information Security Center NCTU IEEE Reliability Society Taipei and Tainan IACR United States Virage Logic Corp. AT and T Bell Laboratories Logic Vision Inc. University of British Columbia IEEE Test Technology Technical Council

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Effect of a Magnetic Field on the Preparation of Silver Nanowires Using Solid Electrolyte Thin Films

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Journal of Materials Science & Technology 2007年第1期23卷 39-42页

作者： Haifei YAO Jialin SUN Wei LIU Hongsan SUN Laboratory of Advanced Materials Department of Materials Science and Engineering Tsinghua University Beijing 100084 China Key Laboratory of Atomic and Molecular Nanosciences of Education Ministry and Department of Physics Tsinghua University Beijing 100084 China Computer Aided Architecture Design Laboratory Tsinghua University Beijing 100084 China

The effect of an external magnetic field on the preparation of silver nanowires was studied. The silver nanowires were synthesized using solid electrolyte RbAg4I5 thin films by applying both a direct current （DC） electric field and a magnetic field. The RbAg4I5 thin films, which were prepared by deposition at room temperature and atmospheric pressure on a NaCI substrate, were used for the transfer of Ag^＋ ions between two Ag electrodes during the preparation process. When only the DC electric field is applied, the silver ions migrate toward the cathode. On the edge of the silver film at the cathode the Ag^＋ ions congregate to form aligned nanowires. If the magnetic field is also applied perpendicular to the DC electric field, the morphology of the nanowires can be controlled by rotating the sample in the magnetic field. Experimental results show that the growth of the silver nanowires is determined by the Ag^＋ ionic flux.

关键词： Silver nanowires Solid electrolyte Magnetic field

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