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Workload characterization of biometric applications on Pentium 4 microarchitecture

Workload characterization of biometric applications on Penti...

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IEEE International Workshop/Symposium on Workload Characterization

作者： Chang-Burm Cho A.V. Chande Yue Li Tao Li Intelligent Design of Efficient Architecture Laboratory Department of Electrical and Computer Engineering University of Florida USA

Biometric computing is a technique that uses physiological and behavioral characteristics of persons to identify and authenticate individuals. Due to the increasing demand on security, privacy and anti-terrorism, biometric applications represent the rapidly growing computing workloads. However, very few results on the execution characteristics of these applications on the state-of-the-art microprocessor and memory systems have been published so far. This paper proposes a suite of biometric applications and reports the results of a biometric workload characterization effort, focusing on various architecture features. To understand the impacts and implications of biometric workloads on the processor and memory architecture design, we contrast the characteristics of biometric workloads and the widely used SPEC 2000 integer benchmarks. Our experiments show that biometric applications typically show small instruction footprint that can fit in the L1 instruction cache. The loads and stores account for more than 50% of the dynamic instructions. This indicates that biometric applications are data-centric in nature. Although biometric applications work across large-scale datasets to identify matched patterns, the active working sets of these workloads are usually small. As a result, prefetching and large L2 cache effectively handle the data footprints of a majority of the studied benchmarks. Branch misprediction rate is less than 4% on all studied workloads. The IPC of the studied benchmarks ranges from 0.13 to 0.77 indicates that out-of-order superscalar execution is not quite efficient. The developed biometric benchmark suite (BMW) and input data sets are freely available and can be downloaded from http://***/BMW.

关键词： Biometrics Microarchitecture Security Privacy Microprocessors computer architecture Memory architecture Large-scale systems Pattern matching Prefetching

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Cache scrubbing in microprocessors: myth or necessity?

Cache scrubbing in microprocessors: myth or necessity?

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Pacific Rim International Symposium on Dependable Computing

作者： S.S. Mukherjee J. Emer T. Fossum S.K. Reinhardt Massachusetts Microprocessor Design Center Intel Corporation Shrewsbury MA USA Advanced Computer Architecture Laboratory EECS Department University of Michigan Ann Arbor MI USA

Transient faults from neutron and alpha particle strikes in large SRAM caches have become a major problem for microprocessor designers. To protect these caches, designers often use error correcting codes (ECC), which typically provide single-bit error correction and double-bit error detection (SECDED). Unfortunately, two separate strikes could still flip two different bits in the same ECC-protected word. This we call a temporal double-bit error. SECDED ECC can only detect, not correct such errors. We show how to compute the mean time to failure for temporal double-bit errors. Additionally, we show how fixed-interval scrubbing - in which error checkers periodically access cache blocks and remove single-bit errors - can mitigate such errors in processor caches. Our analysis using current soft error rates shows that only very large caches (e.g., hundreds of megabytes to gigabytes) need scrubbing to reduce the temporal double-bit error rate to a tolerable range.

关键词： Microprocessors Error correction codes Error correction Hardware computer architecture Protection Writing Bandwidth Error analysis Multiprocessing systems

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Techniques to reduce the soft error rate of a high-performance microprocessor

Techniques to reduce the soft error rate of a high-performan...

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Annual International Symposium on computer architecture, ISCA

作者： C. Weaver J. Emer S.S. Mukherjee S.K. Reinhardt Massachusetts Microprocessor Design Center Intel Corporation Ann Arbor MI USA Massachusetts Microprocessor Design Center Intel Corporation Hudson MA USA EECS Department Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA

Transient faults due to neutron and alpha particle strikes pose a significant obstacle to increasing processor transistor counts in future technologies. Although fault rates of individual transistors may not rise significantly, incorporating more transistors into a device makes that device more likely to encounter a fault. Hence, maintaining processor error rates at acceptable levels will require increasing design effort. This paper proposes two simple approaches to reduce error rates and evaluates their application to a microprocessor instruction queue. The first technique reduces the time instructions sit in vulnerable storage structures by selectively squashing instructions when long delays are encountered. A fault is less likely to cause an error if the structure it affects does not contain valid instructions. We introduce a new metric, MITF (Mean Instructions To Failure), to capture the trade-off between performance and reliability introduced by this approach. The second technique addresses false detected errors. In the absence of a fault detection mechanism, such errors would not have affected the final outcome of a program. For example, a fault affecting the result of a dynamically dead instruction would not change the final program output, but could still be flagged by the hardware as an error. To avoid signalling such false errors, we modify a pipeline's error detection logic to mark affected instructions and data as possibly incorrect rather than immediately signaling an error. Then, we signal an error only if we determine later that the possibly incorrect value could have affected the program's output.

关键词： Error analysis Microprocessors Circuit faults computer errors Error correction computer architecture Protection Delay Performance loss Hardware

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Development of computer programme for the description of plastic deformation by slip 7

Development of computer programme for the description of pla...

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7th Korea-Russia International Symposium on Science and Technology, KORUS 2003

作者： Semenov, M.E. Kolupaeva, S.N. Laboratory of Computer Aided Design of Advanced Materials Institute of Strength Physics and Materials Science Akademichesky pr. 2/1 Tomsk634021 Russia Department of Applied Mathematics Tomsk State University of Architecture and Building Solyanaya sq. 2 Tomsk634003 Russia

ISBN: (纸本)8978686184

The interface and structure of a package of applied programs for the description of plastic deformation by slip in f.c.c. materials are developed. The mathematical model used for calculations is based on the set of differential equations of balance of deformation defects in f.c.c. materials. The processes of generation and annihilation of deformation defects have essentially different rates, and the system of ODE (ordinary differential equations) is stiff. Application of implicit absolutely steady methods is necessary in this situation, because classical Runge-Kutta's methods can require much time for calculations. In this case the use of implicit multistep Gear's method of the variable order for decision the system of ODE is more effective. The applied programs for the description of plastic deformation are oriented for the users who have different qualification in programming and are not require an experience of decision of ODE. © 2003 7th Korea-Russia Intl Sym on Science.

关键词： Ordinary differential equations

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Doppler diversity for OFDM wireless mobile communications. Part I: frequency domain approach

Doppler diversity for OFDM wireless mobile communications. P...

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IEEE Conference on Vehicular Technology (VTC)

作者： Byung-Chul Kim I-Tai Lu System Architecture Design Laboratory TN Business Samsung Electronics Company Limited Suwon Gyeonggi South Korea Department of Electrical and Computer Engineering Polytechnic University Melville NY USA

ISBN: (纸本)0780377575

A novel frequency domain Doppler diversity technique for OFDM systems is proposed. The received OFDM signal is first frequency shifted to generate various diversity branches. After demodulation, branch outputs are individually weighted and added together. For Doppler spread signal, it alters fading statistics and improves the bit error rate. Extensive simulations show that combining three diversity branches with proper frequency shifts reduces BER by an order when the normalized Doppler spread is larger than 0.3.

关键词： OFDM Wireless communication Mobile communication Frequency domain analysis Diversity reception Frequency diversity Bit error rate Signal generators Demodulation Fading

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Combining deterministic logic BIST with test point insertion

Combining deterministic logic BIST with test point insertion

引用

IEEE European Test Symposium (ETS)

作者： H. Vranken F. Meister H.-J. Wunderlich IC Design-Digital Design & Test Philips Research Laboratories Eindhoven Netherlands Computer Architecture Laboratory University of Stuttgart Stuttgart Germany

This paper presents a logic BIST approach which combines deterministic logic BIST with test point insertion. Test points are inserted to obtain a first testability improvement, and next a deterministic pattern generator is added to increase the fault efficiency up to 100%. The silicon cell area for the combined approach is smaller than for approaches that apply a deterministic pattern generator or test points only. The combined approach also removes the classical limitations and drawbacks of test point insertion, such as failing to achieve complete fault coverage and a complicated design flow. The benefits of the combined approach are demonstrated in experimental results on a large number of ISCAS and industrial circuits.

关键词： Logic testing Built-in self-test Circuit testing Circuit faults Integrated circuit testing Automatic test pattern generation Test pattern generators Automatic testing Silicon Manufacturing

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Application of deterministic logic BIST on industrial circuits

Application of deterministic logic BIST on industrial circui...

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IEEE International Test Conference

作者： G. Kiefer H. Vranken E.J. Marinissen H.-J. Wunderlich Computer Architecture Laboratory University of Stuttgart Stuttgart Germany IC Design-Digital Design & Test Philips Research Laboratories Eindhoven Netherlands

We present the application of a deterministic logic BIST scheme on state-of-the-art industrial circuits. Experimental results show that complete fault coverage can be achieved for industrial circuits up to 100 K gates with 10000 test patterns, at a total area cost for BIST hardware of typically 5%-15%. It is demonstrated that a tradeoff is possible between test quality, test time, and silicon area. In contrast to BIST schemes based on test point insertion no modifications of the circuit under test are required, complete fault efficiency is guaranteed, and the impact on the design process is minimized.

关键词： Logic circuits Built-in self-test Circuit testing Logic testing Integrated circuit testing Circuit faults System testing Frequency Test equipment Clocks

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Addressing communication latency issues on clusters for fine grained asynchronous applications - A case study 13th

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13th International Parallel Processing Symposium, IPPS 1999 Held in Conjunction with the 10th Symposium on Parallel and Distributed Processing, SPDP 1999

作者： Rajasekaran, Umesh Kumar V. Chetlur, Malolan Sharma, Girindra D. Radhakrishnan, Radharamanan Wilsey, Philip A. Computer Architecture Design Laboratory Dept of ECECS PO Box 210030 CincinnatiOH45221-0030 United States

ISBN: (纸本)3540658319

With the advent of cheap and powerful hardware for workstations and networks, a new cluster-based architecture for parallel processing applications has been envisioned. However, fine-grained asynchronous applications that communicate frequently ate not the ideal candidates for such architectures because of their high latency communication costs. Hence, designers of fine-grained parallel applications on clusters are faced with the problem of reducing the high communication latency in such architectures. Depending on what kind of resources are available, the communication latency can be improved along the following dimensions: (a) reducing network latency by employing a higher performance network hardware (i.e., Fast Ethernet versus Myrinet);(b) reducing communication software overhead by developing more efficient communication libraries (MPICH versus TCPMPL (our TCP/IP based message passing layer) versus MPI-BIP);(c) rewriting/restructuring the application code for less frequent communication;and (d) exploiting application characteristics by deploying communication optimizations that exploit the application’s inherent communication characteristics. This paper discusses our experiences with building a communication subsystem on a cluster of workstations for a fine-grained asynchronous application (a Time Warp synchronized discrete-event simulator). Specifically, our efforts in reducing the communication latency along three of the four aforementioned dimensions are detailed and discussed. In addition, performance results from an in-depth empirical evaluation of the communication subsystem are reported in the paper. © Springer-Verlag Berlin Heidelberg 1999.

关键词： Message passing

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Optimizing message delivery in asynchronous distributed applications

Optimizing message delivery in asynchronous distributed appl...

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5th International Conference on Parallel Processing, Euro-Par 1999

作者： Sharma, Girindra D. Abu-Ghazaleh, Nael B. Rajasekaran, Umesh Kumar V. Wilsey, Philip A. Computer Architecture Design Laboratory Dept. of ECECS PO Box 210030 Cincinnati OH 45221-0030 United States

ISBN: (纸本)3540664432

Since the message delivery time of asynchronous applications is unpredictable, each asynchronous process must probe (or poll) the network for new messages regularly. If polling is carried out too aggressively, a majority of the probes will be unsuccessful. However, the cost for probing the network is similar to the cost of communication operations. Thus, optimizing the message reception behavior has a significant impact on the performance of the application. This paper studies this problem, and develops a cost model to optimize the polling frequency. We also develop strategies to optimize the message delivery behavior, and study their impact on the performance of a parallel discrete event simulator. © Springer-Verlag Berlin Heidelberg 1999.

关键词： Costs

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An object-oriented framework for parallel simulation of ultra-large communication networks 1

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3rd International Symposium on Computing in Object-Oriented Parallel Environments, ISCOPE 1999

作者： Rao, Dhananjai Madhava Wilsey, Philip A. Computer Architecture Design Laboratory Dept. Of ECECS University of Cincinnati P.O. Box 210030 CincinnatiOH45221-0030 United States

ISBN: (数字)9783540466970

ISBN: (纸本)3540668187

Communication networks have steadily increased in size and complexity to meet the growing demands of applications. Simulations have been used to model and analyze modern communication networks. Modeling and simulation of networks involving thousands of nodes is hard due to their sheer size and complexity. Complete models of the ultra- large networks need to be simulated in order to conduct in-depth studies of scalability and performance. Parallel simulation techniques need to be efficiently utilized to obtain optimal time versus resource tradeoffs. Due to the complexity of the system, it becomes critical that the design of such frameworks follow well established design principles such as object oriented (OO) design, so as to meet the diverse requirements of portability, maintainability, extensibility, and ease of use. This paper presents the issues involved in the design and implementation of an OO framework to enable parallel simulation of ultra-large communication networks. The OO techniques utilized in the design of the framework and the application program interfaces needed for model development are presented along with some experimental results. © Springer-Verlag Berlin Heidelberg 1999.

关键词： Complex networks

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