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3rd International ICST Conference on IT Revolutions, 2011

作者： García-García, Carlos Gómez-Luna, Juan Herruzo Gomez, Ezequiel Benavides Benitez, José Ignacio Computer Architecture Electronics and Electronic Technology Dept. University of Córdoba Spain

ISBN: (纸本)9783642323034

Automatic Repeat Request (ARQ) protocols are a very important functionality in computer networks, which steer information transmission between network devices. Its knowledge is essential for students in computer Science. In this way, simARQ simulator is an effective learning tool, which gives students an environment for self-training. It has Demo and Simulation modes, and a useful simulation analysis tool. simARQ has been successfully compared to other widely used ARQ simulator, through a survey among a group of students. © 2012 ICST Institute for computer Science, Social Informatics and Telecommunications Engineering.

关键词： Simulators

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Dual-core motion estimation processor

Dual-core motion estimation processor

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22nd International Conference on Field Programmable Logic and Applications, FPL 2012

作者： Olivares, Joaquín Palomares, Jose M. Dept. of Computer Architecture Electronics and Electronic Technology University of Córdoba Córdoba Spain

ISBN: (纸本)9781467322560

This paper presents a motion estimation processor based on a dual-core architecture. Both cores are based on bit-serial adder trees. Memory structures are also described. This architecture is bit-precision reconfigurable. Performance results for several smartphones and tablets are presented. Furthermore, hardware results and comparison with other works are included. Real-time processing is achieved for all devices studied. © 2012 IEEE.

关键词： Motion estimation

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Dual-core motion estimation processor

Dual-core motion estimation processor

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International Conference on Field Programmable Logic and Applications

作者： Joaquín Olivares Jose M. Palomares Department of Computer Architecture Electronics and Electronic Technology University of Córdoba Cordoba Spain

关键词： Table lookup Logic gates Abstracts

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Convolution computation in FPGA based on carry-save adders and circular buffers

Convolution computation in FPGA based on carry-save adders a...

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3rd International ICST Conference on IT Revolutions, 2011

作者： Moreno, Carlos D. Martínez, Pilar Bellido, Francisco J. Hormigo, Javier Ortiz, Manuel A. Quiles, Francisco J. Computer Architecture Electronics and Electronic Technology Department University of Córdoba Spain Applied Physics Department EPS University of Córdoba Spain Computer Architecture Department University of Málaga Spain Campus Universitario de Rabanales 14071 Córdoba Spain Campus Universitario de Teatinos 29080 Málaga Spain

ISBN: (纸本)9783642323034

In this article, we present some architectures to carry out the convolution computation based on carry-save adders and circular buffers implemented on FPGAs. Carry-save adders are not frequent in the implementation in FPGA devices, since these have a fast carry propagation path. We make use of the specific structure of the FPGA to design an optimized accumulator which is able to deal with carry-save additions as well as carry-propagate additions using the same hardware. On the other hand, this structure of circular buffers allows the convolution computation of two signals with two algorithms of calculation: the input side algorithm and the output side algorithm, in a more efficient way. © 2012 ICST Institute for computer Science, Social Informatics and Telecommunications Engineering.

关键词： Field programmable gate arrays (FPGA)

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A parallel Ray Tracing architecture suitable for application-specific hardware and GPGPU implementations

A parallel Ray Tracing architecture suitable for application...

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2011 14th Euromicro Conference on Digital System Design: architectures, Methods and Tools, DSD 2011

作者： Nery, Alexandre S. Nedjah, Nadia Franca, Felipe M.G. Jozwiak, Lech LAM - Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal Rio de Janeiro Brazil Department of Electronics Engineering and Telecommunications Faculty of Engineering Universidade do Estado Rio de Janeiro Brazil Department of Electrical Engineering - Electronic Systems Eindhoven University of Technology Netherlands

ISBN: (纸本)9780769544946

The Ray Tracing rendering algorithm can produce high-fidelity images of 3-D scenes, including shadow effects, as well as reflections and transparencies. This is currently done at a processing speed of at most 30 frames per second. Therefore, actual implementations of the algorithm are not yet suitable for interactive real-time rendering, which is required in games and virtual reality based applications. Fortunately, the algorithm allows for massive parallelization of its computations. In this paper, we present a parallel architecture for ray tracing based on a uniform spatial subdivision of the scene and exploiting an embedded computation of ray-triangle intersections. This approach allows for a significant acceleration of intersection computations, as well as, a reduction of the total number of the required intersections checks. Furthermore, it allows for these checks to be performed in parallel and in advance for each ray. In this paper we discuss and analyze an ASIP-based implementation using FPGAs and a GPGPU-based parallel implementation of the proposed architecture. The performance of both implementations are reported and compared." © 2011 IEEE.

关键词： Ray tracing

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Histograms for fuzzy color spaces

Advances in Intelligent and Soft Computing

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Advances in Intelligent and Soft Computing 2011年 107卷 339-350页

作者： Chamorro-Martínez, J. Sánchez, D. Soto-Hidalgo, J.M. Martínez-Jiménez, P. Dept. Computer Science and A.I. University of Granada Spain European Centre for Soft Computing Mieres Spain Department of Computer Architecture Electronics and Electronic Technology University of Córdoba Spain

ISBN: (纸本)9783642240003

In this paper we introduce two kinds of fuzzy histograms on the basis of fuzzy colors in a fuzzy color space and the notion of gradual number by Dubois and Prade. Fuzzy color spaces are a collection of fuzzy sets providing a suitable, conceptual quantization with soft boundaries of crisp color spaces. Gradual numbers assign numbers to values of a relevance scale, typically [0,1]. Contrary to convex fuzzy subsets of numbers (called fuzzy numbers, but corresponding to fuzzy intervals as an assignment of intervals to values of [0,1]), they provide a more precise representation of the cardinality of a fuzzy set. Histograms based on gradual numbers are particularly well-suited for serving as input to another process. On the contrary, they are not the best choice when showing the information to a human user. For this second case, linguistic labels represented by fuzzy numbers are a better alternative, so we define linguistic histograms as an assignment of linguistic labels to each fuzzy color. We provide a way to calculate linguistic histograms based on the compatibility between gradual numbers and linguistic labels. We illustrate our proposals with some examples. © 2011 Springer-Verlag Berlin Heidelberg.

关键词： Linguistics

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Hardware reuse in modern application-specific processors and accelerators

Hardware reuse in modern application-specific processors and...

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2011 14th Euromicro Conference on Digital System Design: architectures, Methods and Tools, DSD 2011

作者： Nery, Alexandre S. Jozwiak, Lech Lindwer, Menno Cocco, Mauro Nedjah, Nadia França, Felipe M.G. LAM - Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal do Rio de Janeiro Brazil Department of Electronics Engineering and Telecommunications Faculty of Engineering Universidade do Estado do Rio de Janeiro Brazil Department of Electrical Engineering - Electronic Systems Eindhoven University of Technology Netherlands Silicon Hive - Intel UMG Netherlands

ISBN: (纸本)9780769544946

Effective exploitation of the application-specific parallel patterns and computation operations through their direct implementation in hardware is the base for construction of high-quality application-specific (re-) configurable application specific instruction set processors (ASIPs) and hardware accelerators for modern highly-demanding applications. Although it receives a lot of attention from the researchers and practitioners, a very important problem of hardware reuse in ASIP and accelerator synthesis is clearly underestimated and does not get enough attention in the published research. This paper is an effect of an industry and academic collaborative research. It analyses the problem of hardware sharing, shows its high practical relevance, as well as a big influence of hardware sharing on the major circuit and system parameters, and its importance for the multi-objective optimization and tradeoff exploitation. It also demonstrates that the state-of-the-art synthesis tools do not sufficiently address this problem and gives several guidelines related to enhancement of the hardware reuse. © 2011 IEEE.

关键词： Multiobjective optimization

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On some fuzzy relations for color information

On some fuzzy relations for color information

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IEEE International Conference on Fuzzy Systems (FUZZ-IEEE)

作者： D. Sánchez J. M. Soto-Hidalgo J. Chamorro-Martínez P. Martínez-Jiménez European Centre for Soft Computing Micros Asturias Spain Department Computer Architecture Electronics and Electronic Technology University of Córdoba Spain Department Computer Science and A.I. University of Granada Spain

In this paper we introduce several fuzzy resemblance relations between different combinations of crisp and fuzzy colors. As a starting point, we discuss about fuzzy colors and fuzzy color spaces as a way to represent color information, providing examples of conjunctive and disjunctive use of fuzzy colors for this purpose. Then we determine different types of relations measuring the degree of matching between color information of different kinds, using well known results from fuzzy sets and possibility theories. We study the particular case in which the user considers there is no resemblance between the fuzzy colors comprising the fuzzy color space under consideration. The proposal is based on definitions of fuzzy color and fuzzy color space provided by the authors in previous works.

关键词： Color Image color analysis Semantics Copper Fuzzy sets Pragmatics Kernel

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A parallel architecture for ray-tracing with an embedded intersection algorithm

A parallel architecture for ray-tracing with an embedded int...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Alexandre S. Nery Nadia Nedjah Felipe M.G. França Lech Jozwiak LAM-Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal do Rio de Janeiro Brazil Department of Electrical Engineering-Electronic Systems Eindhovan University of Technology Netherlands Department of Electronics Engineering and Telecommunications-Faculty of Engineering Universidade do Estado do Rio de Janeiro (UERJ) Brazil

Real time rendering of three-dimensional scenes in Ray Tracing is a hard problem. However, parallel implementations have been enabling real time performance, as the algorithm can be highly parallelized. Thus, a custom parallel design in hardware is likely to achieve a good performance. In this paper, we further improve the GridRT architecture overall performance by embedding the ray-triangle intersection computation into the precessing elements that form the architecture. Low cost and high rendering performance are the main concerns in this novel design. The results show that the execution time of each intersection computation is reduced by at least 50%, while the area cost is practically unchanged or even reduced when compared to the original GridRT implementation.

关键词： Ray tracing Registers Equations USA Councils Mathematical model Parallel architectures

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Hardware Reuse in Modern Application-Specific Processors and Accelerators

Hardware Reuse in Modern Application-Specific Processors and...

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Euromicro Symposium on Digital System Design

作者： Alexandre S. Nery Lech Jozwiak Menno Lindwer Mauro Cocco Nadia Nedjah Felipe M.G. Franca LAM-Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal do Rio de Janeiro Brazil Department of Electrical Engineering-Electronic Systems Eindhoven University of Technology Netherlands Silicon Hive-Intel UMG Netherlands Department of Electronics Engineering and Telecommunications-Faculty of Engineering Universidade do Estado do Rio de Janeiro Brazil

Effective exploitation of the application-specific parallel patterns and computation operations through their direct implementation in hardware is the base for construction of high-quality application-specific (re-)configurable application specific instruction set processors (ASIPs) and hardware accelerators for modern highly-demanding applications. Although it receives a lot of attention from the researchers and practitioners, a very important problem of hardware reuse in ASIP and accelerator synthesis is clearly underestimated and does not get enough attention in the published research. This paper is an effect of an industry and academic collaborative research. It analyses the problem of hardware sharing, shows its high practical relevance, as well as a big influence of hardware sharing on the major circuit and system parameters, and its importance for the multi-objective optimization and tradeoff exploitation. It also demonstrates that the state-of-the-art synthesis tools do not sufficiently address this problem and gives several guidelines related to enhancement of the hardware reuse.

关键词： Hardware Resource management computer architecture Optimization Program processors Adders Delay

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