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Memory bandwidth optimization of SpMV on GPGPUs

Frontiers of computer Science 2015年第3期9卷 431-441页

作者： Chenggang Clarence YAN Hui YU Weizhi XU Yingping ZHANG Bochuan CHEN Zhu TIAN Yuxuan WANG Jian YIN Key Lab of Intelligent Information Processing Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Institute of Microelectronics Tsinghua University Beijing 100084 China Automation Department Tsinghua University Beijing 100084 China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China State Grid Information & Communication Company of Hunan EPC Changsha 410007 China Department of Computer Shandong University Weihai 250101 China

It is an important task to improve performance for sparse matrix vector multiplication （SpMV）, and it is a difficult task because of its irregular memory access. Gen- eral purpose GPU （GPGPU） provides high computing abil- ity and substantial bandwidth that cannot be fully exploited by SpMV due to its irregularity. In this paper, we propose two novel methods to optimize the memory bandwidth for SpMV on GPGPU. First, a new storage format is proposed to exploit memory bandwidth of GPU architecture more effi- ciently. The new storage format can ensure that there are as many non-zeros as possible in the format which is suitable to exploit the memory bandwidth of the GPU. Second, we pro- pose a cache blocking method to improve the performance of SpMV on GPU architecture. The sparse matrix is partitioned into sub-blocks that are stored in CSR format. With the block- ing method, the corresponding part of vector x can be reused in the GPU cache, so the time to access the global memory for vector x is reduced heavily. Experiments are carried out on three GPU platforms, GeForce 9800 GX2, GeForce GTX 480, and Tesla K40. Experimental results show that both new methods can efficiently improve the utilization of GPU mem- ory bandwidth and the performance of the GPU.

关键词： GPGPU performance tuning SpMV cacheblocking memory bandwidth

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Cross-Technology Communication between WiFi and ZigBee 9

Cross-Technology Communication between WiFi and ZigBee

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9th IEEE International Symposium on Microwave, Antenna, Propagation and EMC Technologies for Wireless Communications, MAPE 2022

作者： Fan, Wendong Chen, Tian Gu, Yu Li, Yang Hefei University of Technology S2AC Lab School of Computer and Information Hefei China Hefei University of Technology Institute of Affective Computing and Systems Architecture Hefei China Anhui Agricultural University School of Information & Computer Hefei China

ISBN: (数字)9781665427753

ISBN: (纸本)9781665427753

The coexistence of heterogeneous devices in the Internet of Things wireless network brings a new topic of cross-technology communication in order to improve the communication efficiency between heterogeneous devices and promote the cooperation between heterogeneous devices. WiFi and ZigBee are the two most commonly used IoT devices in IoT environments. They have the advantages of low communication delay, high speed, low cost, and easy deployment. Since the spectrum of WiFi and ZigBee overlap, ZigBee signal will affect the transmission of CSI signal. We propose a CTC technique based on machine learning and deep learning, which uses only WiFi channel state information (CSI), and can distinguish whether there is ZigBee signal transmission in WiFi signals by classifying WiFi channel state information. In this paper, machine learning classification methods and deep learning methods are used to classify CSI sequences respectively. We extract the features of 8 CSI sequences to improve the accuracy of machine learning classifier and LSTM classifier, and adopt transformer network classifier to further improve the classification accuracy. In our experimental dataset, the highest accuracy rate can reach 94.9%. The evaluation results show that the accuracy of this method is significantly higher than the existing classification methods. © 2022 IEEE.

关键词： Channel state information

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Classification of web link information and implementation of dynamic web page using link map system

Classification of web link information and implementation of...

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IEEE International Conference on Granular Computing (GRC)

作者： Yilhyeong Mun Minkyung Lee Dongsub Cho Computer Architecture Lab Department of Computer Science and Engineering Ewha Womans University Seoul South Korea

ISBN: (纸本)9781424425129

Great many Websites exist present. These Websites are developing various services to accommodate many customers. This time, several kinds of links exist to website. But, size of early service Web page increased as numbers of this service increase greatly. A lot of links give load to Web server. When several users approached for Web page, a lot of links can give decline in the service speed. We made link map system to supplement this problem. So, web page links everybody do not service and provide some service. So, this system can reduce serverpsilas load. Access users remove normal times and approach to Website similarly, but links that link map system is needless automatically and service Web page. This time, we test effect that reach to subordinate to server. Also, we test serverpsilas phase diagram by difference of service number of links.

关键词： Web pages Web server Servers Distributed databases Databases Conferences Artificial intelligence

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Users Access Discrimination and Remote Control Study of Embedded System Using Mini Web Server

Users Access Discrimination and Remote Control Study of Embe...

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International Conference on Advanced Language Processing and Web Information Technology (ALPIT)

作者： Yilhyeong Mun Dongsub Cho Computer Architecture Lab Department of Computer Science and Engineering Ewha Womans University Seoul South Korea

Embedded mini Web server is difficult access of many users like general Web server. However, if many users should access to Embedded system, this system need access certification and service management about *** this paper, we attempt RFID access that is characteristic access method that is not method that is log of general Web server. Also, many users must consider segment that manages occasion and majority embedded systems accessing to embedded system. One administrator must be able to control easily embedded equipments to manage many several embedded systems efficiently. And discrete embedded environment is important efficient remote management. When it is environment that many users use embedded system need user each differentiation vicinity and control. We study plan for security access and efficient control about embedded system resource.

关键词： Embedded system Web server Radiofrequency identification Certification Digital audio broadcasting Control systems Unicast

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Outsourcing the Computation of Plaintext Encryption for Homomorphic Encryption 8

Outsourcing the Computation of Plaintext Encryption for Homo...

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8th International Conference on computer and Communication Systems, ICCCS 2023

作者： Li, Xuelei Li, Ruyang Bai, Bing Zhao, Yaqian Liu, Guangqing Li, Rengang Electronic Information Industry Co. Ltd Department of Computer Architecture Research Beijing China Intelligent Network Research Institute Zhejiang Lab Hangzhou China Inspur Electronic Information Industry Co. Ltd Department of Computer Architecture Research Jinan China Electronic Information Industry Co. Ltd Department of Technological Innovation Beijing China

ISBN: (纸本)9781665456128

Homomorphic encryption is a promising technology for private enhanced computing. It provides a data-centric privacy-preserving method that allows computing on encrypted data by a third proxy. However, lightweight terminals lack sufficient computing resources to perform a large amount of encryption operations in stream data applications, e.g., smart devices in blockchain network, sensors and cameras in urban intelligent transport. This paper presents a blinded encryption paradigm that outsources most computations to a third proxy, e.g., cloud computing and edge computing. It helps to eliminate the encryption overhead for lightweight terminals while preserving data privacy. The proposed paradigm is composed of plaintext blinding, blinded encryption, ciphertext recovery and one round of communication. Lightweight terminals only execute efficient plaintext blinding and ciphertext recovery to guarantee data privacy. The expensive computing for plaintext encryption is delegated to a third proxy through blinded encryption. In addition, the key analysis to achieve time consuming improvement is to overlap the communication latency with computation time. Furthermore, the security analysis demonstrates the outsourced encryption is secure under the assumption of secure blinding and recovery algorithms. Finally, the experiment shows our method outperforms the original version by 2x improvement from the prospective of resource consumption. © 2023 IEEE.

关键词： Recovery

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Modeling functional dynamics of cortical gyri and sulci 1

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1st International Workshop on Simulation and Synthesis in Medical Imaging, SASHIMI 2016 held in conjunction with 19th International Conference on Medical Image Computing and computer-Assisted Intervention, MICCAI 2016

作者： Jiang, Xi Li, Xiang Lv, Jinglei Zhao, Shijie Zhang, Shu Zhang, Wei Zhang, Tuo Liu, Tianming Cortical Architecture Imaging and Discovery Lab Department of Computer Science and Bioimaging Research Center The University of Georgia AthensGA United States School of Automation Northwestern Polytechnical University Xi’an China

ISBN: (数字)9783319467207

ISBN: (纸本)9783319467191

Cortical gyrification is one of the most prominent features of human brain. A variety of studies in the brain mapping field have demonstrated the specific structural and functional differences between gyral and sulcal regions. However,previous studies of gyri/sulci function analysis based on the fMRI data assume the temporal stationarity over the entire fMRI scan,while the possible temporal dynamics of gyri/sulci function is largely unknown. We present a computational framework to model the functional dynamics of cortical gyri and sulci based on task fMRI data. Specifically,the whole-brain fMRI signals’ temporal segments are derived via the sliding time window approach. The spatial overlap patterns among functional networks (SOPFNs),which are crucial for characterizing brain functions,are then measured within each time window via a group-wise sparse representation approach. Finally,the temporal dynamics of SOPFNs distribution on gyral/sulcal regions across all time windows are assessed. Experimental results based on the publicly released Human Connectome Project task fMRI data demonstrated that the proposed framework identified meaningful temporal dynamics difference of the SOPFNs distribution between gyral and sulcal regions which are reproducible across different subjects and task fMRI datasets. Our results provide novel understanding of functional dynamics mechanisms of human cerebral cortex. © Springer International Publishing AG 2016.

关键词： Dynamics

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Co-designing a Technology Probe with Experienced Designers 33

Co-designing a Technology Probe with Experienced Designers

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33rd Australian computer-Human Interaction Conference, OzCHI 2021

作者： Gough, Phillip Kocaballi, A. Baki Naqshbandi, Khushnood Z. Cochrane, Karen Mah, Kristina Pillai, Ajit G. Yorulmaz, Yeliz Deny, Ainnoun Kornita Ahmadpour, Naseem Affective Interactions Lab School of Architecture Design and Planning The University of Sydney Australia School of Computer Science University of Technology Sydney Australia School of It Carleton University Canada Independent Artist Australia

ISBN: (纸本)9781450395984

Technology probes are low-fidelity devices that can be used to understand research participant's lived experiences, but they are not usually subject to iterative design. There are opportunities in human-computer interaction to develop technology probes through co-design, by including diverse perspectives during probe development. To explore this opportunity, five design researchers with different disciplinary and cultural backgrounds engaged with a technology probe to support daily reflections, discussed new directions in a co-design workshop and developed narratives to negotiate possibilities of the probe. This paper presents observations described by each of the researchers using the probe, and insights from the process we followed. We discuss how the the designers' postitionalities are reflected in the processes, and how they brought value by shaping narratives of the different roles a technology probe might take. We also discuss how we may use co-design of technology probes as a generative method, highlight the importance of open-endedness in the process, and reflect on lessons learned. © 2021 ACM.

关键词： Iterative methods

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StressTest: an automatic approach to test generation via activity monitors

StressTest: an automatic approach to test generation via act...

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Design Automation Conference

作者： I. Wagner V. Bertacco T. Austin Advanced Computer Architecture Lab University of Michigan Ann Arbor MI USA

The challenge of verifying a modern microprocessor design is an overwhelming one: increasingly complex micro-architectures combined with heavy time-to-market pressure have forced microprocessor vendors to employ immense verification teams in the hope of finding the most critical bugs in a timely manner. Unfortunately, too often size doesn't seem to matter for verification teams, as design schedules continue to slip and microprocessors find their way to the marketplace with design errors. In this paper, we describe a simulation-based random test generation tool, called StressTest, that provides assistance in locating hard-to-find corner-case design bugs and performance problems. StressTest is based on a Markov-model-driven random instruction generator with activity monitors. The model is generated from the user-specified template programs and is used to generate the instructions sent to the design under test (DUT). In addition, the user specifies key activity points within the design that should be stressed and monitored throughout the simulation. The StressTest engine then uses closed-loop feedback techniques to transform the Markov model into one that effectively stresses the points of interest. In parallel, StressTest monitors the correctness of the DUT response to the supplied stimuli, and if the design behaves unexpectedly, a bug and a trace that leads to it are reported. Using two micro-architectures as example testbeds, we demonstrate that StressTest finds more bugs with less effort than open-loop random instruction test generation techniques.

关键词： Automatic testing Microprocessors computer bugs Analytical models Formal verification computer displays Permission Logic testing computer architecture Processor scheduling

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Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages

Total power reduction in CMOS circuits via gate sizing and m...

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Design Automation Conference

作者： Feng Gao J.P. Hayes Advanced Computer Architecture Lab University of Michigan Ann Arbor MI USA

ISBN: (纸本)1595930582

Minimizing power consumption is one of the most important objectives in IC design. Resizing gates and assigning different V/sub t/'s are common ways to meet power and timing budgets. We propose an automatic implementation of both these techniques using a mixed-integer linear programming model called MLP-exact, which minimizes a circuit's total active-mode power consumption. Unlike previous linear programming methods which only consider local optimality, MLP-exact can find a true global optimum. An efficient, non-optimal way to solve the MLP model, called MLP-fast, is also described. We present a set of benchmark experiments which show that MLP-fast is much faster than MLP-exact, while obtaining designs with only slightly higher power consumption. Furthermore, the designs generated by MLP-fast consume 30% less power than those obtained by conventional, sensitivity-based methods.

关键词： Circuits Threshold voltage Energy consumption Linear programming Algorithm design and analysis Permission Capacitance Delay lines Piecewise linear approximation Space exploration

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Classification based scheduling in Heterogeneous ISA architectures

Classification based scheduling in Heterogeneous ISA Archite...

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International Symposium on VLSI Design and Test (VDAT)

作者： Nirmal Kumar Boran Dinesh Kumar Yadav Rishabh Iyer Computer Architecture and Dependable System Lab Indian Institute of Technology Bombay India

ISBN: (数字)9781728193694

ISBN: (纸本)9781728193700

Heterogeneous-ISA multi-core architectures are emerging as promising architectures to enhance single-threaded performance. Multiple cores in such architectures differ in their Instruction Set architectures (ISAs). To achieve maximum performance gain, the program needs to be divided into several phases and each phase should run on its best affine core. Hence, the best affined core for each phase is needed to be known dynamically apriori. In this work, we propose a classification based technique that attempts to classify the phase of the program into the class of core (in terms of microarchitecture and ISA) it is most suited to. This technique leverages several online hardware performance counters to accurately predict the most affine core for each phase. Results show that our classification based predictor achieves single thread performance average speedup of 35.7% with respect to a baseline single ISA heterogeneous architecture.

关键词： Multicore processing Hardware Benchmark testing Parallel processing Scheduling Training

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