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Proceedings of the 1998 Winter Simulation Conference, WSC. Part 1 (of 2)

作者： Rao, Dhananjai Madhava Thondugulam, Narayanan V. Radhakrishnan, Radharamanan Wilsey, Philip A. Computer Architecture Design Lab Cincinnati United States

Distributed synchronization for parallel simulation is generally classified as being either optimistic or conservative. While considerable investigations have been conducted to analyze and optimize each of these synchronization strategies, very little study on the definition and strictness of causality have been conducted. Do we really need to preserve causality in all types of simulations? This paper attempts to answer this question. We argue that significant performance gains can be made by reconsidering this definition to decide if the parallel simulation needs to preserve causality. We investigate the feasibility of unsynchronized parallel simulation through the use of several queuing model simulations and present a comparative analysis between unsynchronized and Time Warp simulation.

关键词： computer simulation

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SAVANT/TyVIS/warped: components for the analysis and simulation of VHDL

SAVANT/TyVIS/warped: components for the analysis and simulat...

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Proceedings of the 1998 International Verilog HDL Conference

作者： Wilsey, Philip A. Martin, Dale E. Subramani, Krishnan Computer Architecture Design Lab Cincinnati United States

The SAVANT, QUEST II, and HEPE research programs at the University of Cincinnati include the development and distribution of VHDL analysis and simulation capabilities. These capabilities are being freely distributed for non-commercial use. The SAVANT project is underway specifically to develop a VHDL analyzer with a well-documented, extensible intermediate form;the main objective is to smooth the integration of VHDL technology into university and industrial research programs. The SAVANT project is funded through the Air Force SBIR program and is a joint activity between the University of Cincinnati and MTL Systems, Inc. The QUEST II program is investigating parallel algorithms and architectures for simulation, behavioral synthesis, and ATPG. The HEPE program is investigating (in part) novel strategies for relaxing causal orders in the parallel simulation of active networks. As part of the QUEST II/HEPE simulation activities, a VHDL simulation kernel is being developed that will operate with the SAVANT intermediate form for sequential or parallel execution of VHDL models (a C++ code generator from the SAVANT intermediate is being jointly developed by the SAVANT and QUEST II programs). All of the software from the QUEST and HEPE simulation programs is freely available for use (commercial or otherwise).

关键词： computer hardware description languages

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Framework for performance analysis of parallel discrete event simulators

Framework for performance analysis of parallel discrete even...

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Proceedings of the 1997 Winter Simulation Conference

作者： Balakrishnan, Vijay Frey, Peter Abu-Ghazaleh, Nael B. Wilsey, Philip A. Computer Architecture Design Lab Cincinnati United States

A framework for performance analysis of parallel discrete event simulators is presented. The center-piece of this framework is a platform-independent Workload Specification Language (WSL). WSL is a language that allows the characterization of simulation models using a set of fundamental performance-critical parameters. WSL also implements a facility for representing real models. For each simulator to be tested, a WSL translator is used to generate synthetic platform-specific simulation models that conform to the performance characteristics captured by the WSL description. Accordingly, sets of portable simulation models that explore the effects of the different parameters, individually or collectively, on the performance can be constructed. The construction of the workload simulation models is assisted using a Synthetic Workload Generator (SWG). The utility of the system is demonstrated with the generation of a representative set of experiments. The described framework can be used to create a standard benchmark suite that consists of a mixture of real simulation models, selected from different application domains, and synthetic models generated by SWG.

关键词： computer simulation

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Does low-power design imply energy efficiency for data centers?

Does low-power design imply energy efficiency for data cente...

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IEEE/ACM International Symposium on Low-Power Electronics and Design

作者： Meisner, David Wenisch, Thomas F. Advanced Computer Architecture Lab University of Michigan United States

ISBN: (纸本)9781612846590

Data center efficiency has quickly become a first-class design goal. In response, many studies have emerged from the academic community and industry using low-power design to help improve the energy efficiency of server hardware. Generally, these proposals hold the assumption that low-power design is inherently better for energy efficiency;this preconception stems mostly from great success in the mobile space with building low-power, energy-efficient systems. We observe that unlike mobile devices, constraining a data center server to a low power budget is arbitrary and higher power design choices can be more energy efficient. We analyze the energy efficiency design space of past commercial server designs and find that high-power servers are generally more energy efficient than low-power ones. Furthermore, we evaluate building low- or high-power server clusters and find that the small increase in the cost of cooling high-powered servers is easily outweighed by their greater efficiency. © 2011 IEEE.

关键词： Energy efficiency

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On Disabling Prefetcher to Amplify Cache Side Channels 25

On Disabling Prefetcher to Amplify Cache Side Channels

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25th International Symposium on VLSI Design and Test, VDAT 2021

作者： Boran, Nirmal Kumar Pinto, Kenrick Menezes, Bernard IIT Bombay Computer Architecture and Dependable System Lab India

ISBN: (纸本)9781665419925

Side-channel attacks exploit the hardware implementation of processors to extract sensitive data. Attacks that target shared resources between the victim and the attacker are prominent. A shared cache (available in today's multi-core systems) between the attacker and victim has been shown to create a covert channel capable of leaking the private key. An attacker can extract the key by tracking the victim's memory access pattern through the shared cache. Prefetchers introduce noise in the attack by speculatively bringing data into the cache that the victim may not use. This paper presents a denial of service (DoS) attack on the prefetcher to prevent it from generating memory accesses that interfere with the side-channel attack. The proposed attack aims to significantly reduce the number of prefetches generated to enable faster key retrieval. Our results show that the private key can be extracted with only 21% additional time in the presence of a prefetcher when the proposed attack is run (compared to a system with no prefetcher). © 2021 IEEE.

关键词： Side channel attack

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Joint high-resolution feature learning and vessel-shape aware convolutions for efficient vessel segmentation

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computers in Biology and Medicine 2025年 191卷 109982-109982页

作者： Zhang, Xiang Zhu, Qiang Hu, Tao Guo, Song Bian, Genqing Dong, Wei Hong, Rao Lin, Xia Ling Wu, Peng Zhou, Meili Yan, Qingsen Mohi-ud-din, Ghulam Ai, Chen Li, Zhou College of Information and Control Engineering Xi'an University of Architecture and Technology Xi'an China Shaanxi Provincial Key Lab of Bigdata of Energy and Intelligence Processing School of Physics and Electronic Information Yanan University Yanan China School of Computer Science and Engineering Northwestern Polytechnical University Xi'an China School of Software Nanchang University Nanchang China School of Cyber Security Zhejiang University Hangzhou China Department of Basic Education and Research Jiangxi Police College Nanchang China Northwestern Polytechnical University China

Clear imagery of retinal vessels is one of the critical shreds of evidence in specific disease diagnosis and evaluation, including sophisticated hierarchical topology and plentiful-and-intensive capillaries. In this work, we propose a new topology- and shape-aware model named Multi-branch Vessel-shaped Convolution Network (MVCN) to adaptively learn high-resolution representations from retinal vessel imagery and thereby capture high-quality topology and shape information thereon. Two steps are involved in our pipeline. The former step is proposed as Multiple High-resolution Ensemble Module (MHEM) to enhance high-resolution characteristics of retinal vessel imagery via fusing scale-invariant hierarchical topology thereof. The latter is a novel vessel-shaped convolution that captures the retinal vessel topology to emerge from unrelated fundus structures. Moreover, our MVCN of separating such topology from the fundus is a dynamical multiple sub-label generation via using epistemic uncertainty, instead of manually separating raw labels to distinguish definitive and uncertain vessels. Compared to other existing methods, our method achieves the most advanced AUC values of 98.31%, 98.80%, 98.83%, and 98.65%, and the most advanced ACC of 95.83%, 96.82%, 97.09%,and 96.66% in DRIVE, CHASE_DB1, STARE, and HRF datasets. We also employ correctness, completeness, and quality metrics to evaluate skeletal similarity. Our method's evaluation metrics have doubled compared to previous methods, thereby demonstrating the effectiveness thereof. © 2025 Elsevier Ltd

关键词： Ophthalmology

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Peak power modeling for data center servers with switched-mode power supplies 10

Peak power modeling for data center servers with switched-mo...

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Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design

作者： Meisner, David Wenisch, Thomas F. Advanced Computer Architecture Lab University of Michigan United States

ISBN: (纸本)9781450301466

Accurately modeling server power consumption is critical in designing data center power provisioning infrastructure. However, to date, most research proposals have used average CPU utilization to infer the power consumption of clusters, typically averaging over tens of minutes per observation. We demonstrate that average CPU utilization is not sufficient to predict peak power consumption accurately. By characterizing the relationship between server utilization and power supply behavior, we can more accurately model the actual peak power consumption. Finally, we introduce a new operating system metric that can capture the needed information to design for peak power with low overhead. Copyright 2010 ACM.

关键词： Electric power utilization

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BigHouse: A simulation infrastructure for data center systems

BigHouse: A simulation infrastructure for data center system...

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2012 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2012

作者： Meisner, David Wu, Junjie Wenisch, Thomas F. Advanced Computer Architecture Lab University of Michigan United States

ISBN: (纸本)9781467311441

Recently, there has been an explosive growth in Internet services, greatly increasing the importance of data center systems. Applications served from the cloud are driving data center growth and quickly overtaking traditional workstations. Although there are a many tools for evaluating components of desktop and server architectures in detail, scalable modeling tools are noticeably missing. We describe BigHouse a simulation infrastructure for data center systems. Instead of simulating servers using detailed microarchitectural models, BigHouse raises the level of abstraction. Using a combination of queuing theory and stochastic modeling, BigHouse can simulate server systems in minutes rather than hours. BigHouse leverages statistical simulation techniques to limit simulation turnaround time to the minimum runtime needed for a desired accuracy. In this paper, we introduce BigHouse, describe its design, and present case studies for how it has already been applied to build and validate models of data center workloads and systems. Furthermore, we describe statistical techniques incorporated into BigHouse to accelerate and parallelize its simulations, and demonstrate its scalability to model large cluster systems while maintaining reasonable simulation time. © 2012 IEEE.

关键词： Stochastic systems

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Software error classification using purify

Software error classification using purify

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Proceedings of the 1996 IEEE Conference on Software Maintenance, ICSM

作者： Owens, Howard D. Womack, Baxter F. Gonzalez, Mario J. Motorola Advanced Computer Architecture Lab Austin TX United States

Perfect quality represents 100% conformance to specifications. Complex systems make it difficult and expensive to assure conformance to specifications by post production testing alone. As a result quality assurance processes are moving upstream in the life cycle, i.e., statistical process control and design for manufacturability. These processes try to avoid defects or make it easier to detect defects. In software systems this move to upstream processes for quality control is still in its early stages. As with more traditional manufacturing systems, maturity of the software design and development process will dramatically reduce the cost of attaining conformance to specifications. Even so, it is difficult to imagine a 'bug free' complex software system. Downstream processes will continue to play an important part in the efforts to achieve defect-free software. This paper presents results of a survey which used the defect detection tool Purify to examine off-the-shelf software products in order to show that software errors continue to escape testing and threaten field failures. Errors detected are compiled and presented. All data were collected on C and C++ programs running in a UNIX operating system environment.

关键词： Software engineering

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Aizu supercomputer: A massively parallel system for virtual reality problems 1

Aizu supercomputer: A massively parallel system for virtual ...

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1st Aizu International Symposium on Parallel Algorithms/architecture Synthesis, AISPAS 1995

作者： Ikedo, Tsuneo Computer Architecture Lab. Department of Computer Hardware University of Aizu Aizuwakamatsu-City Fukushima Japan

ISBN: (纸本)081867038X

The Aizu supercomputer is a massively parallel system suited to the solution of virtual reality problems and the support of multimedia applications. It employs a highly parallel MIMD architecture using a conflict-free internetwork system. The scalable communication system consists of two networks: a pyramid network and a reconfigurable network using optical links. The Aizu Supercomputer has a cluster configuration and a shared memory. Each PE includes 113 SPECmark and one cluster is organized with 8 PEs. In the trial production, the supercomputer will include 1365 PEs with more than 100 GFlops at peak performance. © 1995 IEEE.

关键词： Supercomputers

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