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Radix-2r arithmetic for FIR filter design optimization

Radix-2r arithmetic for FIR filter design optimization

International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)

作者： Ahmed Liacha Abdelkrim K. Oudjida Farid Ferguene System Architecture and Multimedia Division Centre de Développement des Technologies Avancées Algiers Algeria Faculty of Electronics and Computer Science LRPE Lab. Algiers Algeria

Finite impulse response (FIR) filtering is an ubiquitous operation in digital signal processing systems. It is generally implemented in full-custom style due to the high-speed and low-power design requirements. The hardware design of a FIR filter is mainly dominated by the multiplier block, which is generally implemented as a network of adders, subtractors and shifters for more efficiency in speed and power. In a recent work, a fully predictable and sublinear runtime heuristic for the multiplication by a constant has been developed. It is called RADIX-2 r . In this paper, RADIX-2 r is applied to the FIR filter design optimization. In comparison to the existing heuristics, RADIX-2 r exhibits the shortest adder-depth, leading therefore to the best results in speed and power.

关键词： Finite impulse response filters Adders Hardware Algorithm design and analysis Filtering algorithms Signal processing algorithms

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Hydrogels: Skin‐Inspired Multifunctional Autonomic‐Intrinsic Conductive Self‐Healing Hydrogels with Pressure Sensitivity, Stretchability, and 3D Printability (Adv. Mater. 31/2017)

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Advanced Materials 2017年第31期29卷

作者： Mohammad Ali Darabi Ali Khosrozadeh Rene Mbeleck Yuqing Liu Qiang Chang Junzi Jiang Jun Cai Quan Wang Gaoxing Luo Malcolm Xing Institute of Burn Research State Key Lab of Trauma Burns and Combined Injury Southwest Hospital Third Millitary Medical University Chongqing 400038 China Department of Mechanical Engineering University of Manitoba Winnipeg R3T 5V6 Canada Manitoba Institute for Materials Winnipeg Manitoba R3T 2N2 Canada Department of Electrical and Computer Engineering University of Manitoba Winnipeg Manitoba R3T 5V6 Canada Department of Architecture and Civil Engineering City University of Hong Kong Hong Kong

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Prevention from Soft Errors via architecture Elasticity

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Journal of computer Science & Technology 2014年第2期29卷 247-254页

作者：尹一笑陈云霁郭崎陈天石 State Key Lab of Computer Architecture and Microprocessor Research Center Institute of Computing Technology Chinese Academy of Sciences University of Chinese Academy of Sciences Loongson Technology Corporation Limited IBM Research-China

Due to the decreasing threshold voltages, shrinking feature size, as well as the exponential growth of on-chip transistors, modern processors are increasingly vulnerable to soft errors. However, traditional mechanisms of soft error mitigation take actions to deal with soft errors only after they have been detected. Instead of the passive responses, this paper proposes a novel mechanism which proactively prevents from the occurrence of soft errors via architecture elasticity. In the light of a predictive model, we adapt the processor architectures h01istically and dynamically. The predictive model provides the ability to quickly and accurately predict the simulation target across different program execution phases on any architecture configurations by leveraging an artificial neural network model. Experimental results on SPEC CPU 2000 benchmarks show that our method inherently reduces the soft error rate by 33.2% and improves the energy efficiency by 18.3% as compared with the static configuration processor.

关键词： soft error energy efficiency architecture elasticity

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Temperature-aware software-based self-testing for delay faults 15

Temperature-aware software-based self-testing for delay faul...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Ying Zhang Zebo Peng Jianhui Jiang Huawei Li Masamro Fujita School of Software Engineering Tongji University China Embedded Systems Lab Linköping University Sweden State Key Laboratory of Computer Architecture Chinese Academy of Sciences China VLSI Design and Education Center University of Tokyo Japan

ISBN: (纸本)9783981537048

Delay defects under high temperature have been one of the most critical factors to affect the reliability of computer systems, and the current test methods don't address this problem properly. In this paper, a temperature-aware software-based self-testing (SBST) technique is proposed to self-heat the processors within a high temperature range and effectively test delay faults under high temperature. First, it automatically generates high-quality test programs through automatic test instruction generation (ATIG), and avoids over-testing caused by nonfunctional patterns. Second, it exploits two effective powerintensive program transformations to self-heat up the processors internally. Third, it applies a greedy algorithm to search the optimized schedule of the test templates in order to generate the test program while making sure that the temperature of the processor under test is within the specified range. Experimental results show that the generated program is successful to guarantee delay test within the given temperature range, and achieves high test performance with functional patterns.

关键词： Delays Program processors Temperature distribution Power dissipation Circuit faults Schedules

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A red team/blue team assessment of functional analysis methods for malicious circuit identification 14

A red team/blue team assessment of functional analysis metho...

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51st Annual Design Automation Conference, DAC 2014

作者： Waksman, Adam Rajendran, Jeyavijayan Suozzo, Matthew Sethumadhavan, Simha Computer Architecture and Security Technologies Lab Department of Computer Science Columbia University New York NY United States Department of Electrical and Computer Engineering New York University New York NY United States

ISBN: (纸本)9781479930173

Recent advances in hardware security have led to the development of FANCI (Functional Analysis for Nearly-Unused Circuit Identification), an analysis algorithm that identifies stealthy, malicious circuits within hardware designs that can perform backdoor operations to compromise security. Evaluations of such methods using benchmarks and academically known attacks are not always equivalent to the dynamic attack scenarios that can arise in the real world. For this reason, we apply a red team/blue team approach to stresstest the abilities of the FANCI prototype. In the Embedded Systems Challenge (ESC) 2013, teams from research groups from multiple continents created designs with backdoors hidden in them as part of a red team effort to circumvent FANCI. Notably, these backdoors were not placed into a priori known designs. The red team was allowed to create arbitrary, unspecified designs. Two interesting results came out of this effort. The first was that FANCI was surprisingly resilient to this wide variety of attacks and was not circumvented by any of the stealthy backdoors created by the red teams. The second result is that frequentaction backdoors, which are non-stealthy backdoors, were often successful. These results emphasize the importance of combining FANCI with a reasonable degree of validation testing. The blue team efforts also exposed some areas where the FANCI prototype could be made more performant, which motivates further development of the prototype. Copyright 2014 ACM.

关键词： Functional analysis

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Parallel optimization of geometric correction algorithm based on CPU-GPU hybrid architecture

Parallel optimization of geometric correction algorithm base...

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International Conference on Vehicle and Mechanical Engineering and Information Technology, VMEIT 2014

作者： Bai, Hong Tao Li, Yu Gang Chen, Li Ying Wang, Yan Ling Beijing Lab of Intelligent Information Technology School of Computer Science Beijing Institute of Technology Beijing 100081 China Beijing Lab of Intelligent Information Technology School of Computer Science Beijing Institute of Technology Beijing China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

ISBN: (纸本)9783038350606

Geometric correction is an essential processing procedure in remote sensing image processing. The algorithms used in geometric correction are time intensive and the size of remote sensing images is very large. Meanwhile, the data to be calculated is in huge size and is accumulating rapidly every day. Hence, the fast processing of geometric correction of remote sensing image becomes an urgent research problem. Through the rapid development of GPU, the current GPU has a great advantage in processing speed and memory bandwidth over CPU. It provides a new way for high performance computing. In this paper, we present three optimization solutions based on CPU-GPU hybrid architecture and the analysis of their performances. Experiments are also given and the results are consistent with the analysis. © (2014) Trans Tech Publications, Switzerland.

关键词： Graphics processing unit

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Learning fMRI-guided predictor of video shot changes 11

Learning fMRI-guided predictor of video shot changes

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2014 IEEE 11th International Symposium on Biomedical Imaging, ISBI 2014

作者： Zhang, Shu Hu, Xintao Lv, Jinglei Tuo, Zhang Li, Xiang Jiang, Xi Guo, Lei Liu, Tianming Cortical Architecture Imaging and Discovery Lab. Department of Computer Science University of Georgia AthensGA United States School of Automation Northwestern Polytechnical University Xian China

ISBN: (纸本)9781467319591

In natural stimulus fMRI during video watching, it is natural to postulate that a human participant's attention system would respond to shot changes of the video stream. However, quantitative assessment of the relationship between the functional activities of the attention system and the dynamics of video shot changes has been rarely explored yet. This paper presents a novel framework for modeling the functional interactions and dynamics within the human attention system via natural stimulus fMRI and learning fMRI-based brain response predictors of video shot changes. The basic idea is to derive sub-networks from the attention system and correlate the functional synchronization measurements of these sub-networks with video shot changes. Then, the most relevant sub-networks are identified from training samples and a regression model is constructed as the predictor of video shot changes. In the application stage, the learned predictive models demonstrated good accuracy of estimating video shot changes in independent testing datasets. This study suggests that the fMRI-guided predictive models of functional attention network activities can potentially serve as the brain decoders of video shot changes. © 2014 IEEE.

关键词： Brain

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Multiscale and multimodal fusion of tract-tracing and DTI-derived fibers in macaque brains

Multiscale and multimodal fusion of tract-tracing and DTI-de...

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IEEE International Symposium on Biomedical Imaging

作者： Ke Jing Tuo Zhang Jianfeng Lu Hanbo Chen Xi Jiang Lei Guo Longchuan Li Xiaoping Hu Jinglei Lv Bao Ge Tianming Liu Cortical Architecture Imaging and Discovery Lab The University of Georgia Athens GA School of Computer Science and Engineering Nanjing University of Science and Technology Nanjing China School of Automation Northwestern Polytechnical University Xi'an China Biomedical Imaging Technology Center Emory University Atlanta GA School of Physics & Information Technology Shaanxi Normal University Xi'an China

ISBN: (纸本)9781467393300

Assessment of structural connectivity patterns of macaque brains may hold the key to understanding mechanism of cortical convolution and brain function. Therefore, lots of interests have been attracted to analyze axonal pathways via up-to-date techniques, such as tract-tracing data, which is taken as `gold standard' to estimate trustworthy meso-scale pathways and diffusion MRI (e.g., DTI), from which macroscale brain connectivity map can be reconstructed. In this paper, we for the first time propose a framework to take advantages of the two modalities to identify cross-validated connections and construct corresponding dMRI fiber bundle atlas. This framework is conducted on a whole-brain-connectivity base by fusing information from dMRI derived connectivity maps and tract-tracing connectivity maps derived from CoCoMac database, in which tract-tracing reports are collated across a large research community and the tract-tracing connectivity maps are inferred in a meta-analysis fashion. We demonstrate the effectiveness of the framework by a variety of experiments.

关键词： Diffusion tensor imaging Optical fiber testing Optical fiber theory Joints Indexes

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A hop-by-hop energy efficient distributed routing cheme

A hop-by-hop energy efficient distributed routing cheme

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作者： Hou, Chenying Zhang, Fa Anta, Antonio Fernández Wang, Lin Liu, Zhiyong Institute of Computing Technology CAS University of Chinese Academy of Sciences Beijing China Institute IMDEA Networks Madrid Spain Institute of Computing Technology Chinese State Key Lab for Computer Architecture CAS Beijing China

Energy inefficiencies in current networks provide both challenges and opportunities for energy saving. Recently, there are many works focusing on minimizing energy cost from the routing perspective. However, most existing work view them as optimization problems and solve them in a centralized manner such as with a solver or using approximations. In this paper, we focus on a network-wide bi-objective optimization problem, which simultaneously minimizes the total energy consumption using speed scaling and the total traffic delay. We propose a hop-by-hop dynamic distributed routing scheme for the implementation of this network-wide optimization problem. Our scheme is more practical to realize in large distributed networks compared with current centralized energy minimization methods. We can also achieve near global optimal in a distributed manner, while most used shortest path routing protocols such as OSPF cannot make it. Our routing scheme is totally distributed and maintains loop-free routes in every instant. Simulations conducted in real data sets show that the distributed loop-free routing scheme converges to near Pareto optimal values. Also, our method outperforms the widely applied shortest path routing strategy by 30% in energy saving.

关键词： Energy utilization

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Data-aware DRAM refresh to squeeze the margin of retention time in hybrid memory cube 14

Data-aware DRAM refresh to squeeze the margin of retention t...

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Proceedings of the 2014 IEEE/ACM International Conference on computer-Aided Design

作者： Yinhe Han Ying Wang Huawei Li Xiaowei Li State Key Lab of Computer Architecture Institute of Computing technology Chinese Academy of Sciences and University of Chinese Academy of Sciences

ISBN: (纸本)9781479962778

With the increase of storage density, DRAM refresh leads to higher overhead of power and bandwidth, particularly in emerging 3D stacked memory design like Hybrid Memory Cube (HMC). To exploit the hardware resources for a smarter solution, we propose a data-aware refresh control scheme, Trial and Error (Trial-n-Error), which leverages the data-pattern dependence characteristics of the cells' retention time to reduce refresh operations. Trial-n-Error is a systematic approach that employs our proposed Synergy Testing to capture the refresh bottleneck of DRAM memory: "weak" cells that have a relatively shorter retention time. By locating the dominant weak cells sensitized by applications, Trial-n-Error can avoid the worst-case refresh setting, and adjust the refresh rate under the control of our self-tuning algorithm. Thus, Trial-n-Error can gradually approach to the possible lower-bound of refresh rate for less energy and memory bandwidth consumption. In experiments of 3D-stacked DRAMs, we successfully eliminate an average of 28% refresh operations and save 21% refresh energy for a set of pre-profiled synthetic data patterns and real benchmarks.

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