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Proceedings of the 2014 IEEE/ACM International Conference on computer-Aided Design

作者： Yinhe Han Ying Wang Huawei Li Xiaowei Li State Key Lab of Computer Architecture Institute of Computing technology Chinese Academy of Sciences and University of Chinese Academy of Sciences

ISBN: (纸本)9781479962778

With the increase of storage density, DRAM refresh leads to higher overhead of power and bandwidth, particularly in emerging 3D stacked memory design like Hybrid Memory Cube (HMC). To exploit the hardware resources for a smarter solution, we propose a data-aware refresh control scheme, Trial and Error (Trial-n-Error), which leverages the data-pattern dependence characteristics of the cells' retention time to reduce refresh operations. Trial-n-Error is a systematic approach that employs our proposed Synergy Testing to capture the refresh bottleneck of DRAM memory: "weak" cells that have a relatively shorter retention time. By locating the dominant weak cells sensitized by applications, Trial-n-Error can avoid the worst-case refresh setting, and adjust the refresh rate under the control of our self-tuning algorithm. Thus, Trial-n-Error can gradually approach to the possible lower-bound of refresh rate for less energy and memory bandwidth consumption. In experiments of 3D-stacked DRAMs, we successfully eliminate an average of 28% refresh operations and save 21% refresh energy for a set of pre-profiled synthetic data patterns and real benchmarks.

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What's in the Container? Classifying Object Contents from Vision and Touch

What's in the Container? Classifying Object Contents from Vi...

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IEEE/RSJ International Conference on Intelligent Robots and Systems

作者： Puren Guler Yasemin Bekiroglu Xavi Gratal Karl Pauwels Danica Kragic Computer Vision and Active Perception Lab Center for Autonomous Systems School of Computer Science and Communication KTH Royal Institute of Technology Stockholm Sweden Computer Architecture and Technology Department University of Granada Spain

ISBN: (纸本)9781479969357

Robots operating in household environments need to interact with food containers of different types. Whether a container is filled with milk, juice, yogurt or coffee may affect the way robots grasp and manipulate the container. In this paper, we concentrate on the problem of identifying what kind of content is in a container based on tactile and/or visual feedback in combination with grasping. In particular, we investigate the benefits of using unimodal (visual or tactile) or bimodal (visual-tactile) sensory data for this purpose. We direct our study toward cardboard containers with liquid or solid content or being empty. The motivation for using grasping rather than shaking is that we want to investigate the content prior to applying manipulation actions to a container. Our results show that we achieve comparable classification rates with unimodal data and that the visual and tactile data are complimentary.

关键词： CONTAINERS Grasp Robot Food Containers dry matter content NONVOLATILE CONTENT Visualization Unimodal

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SpongeDirectory: Flexible sparse directories utilizing multi-level memristors

SpongeDirectory: Flexible sparse directories utilizing multi...

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International Conference on Parallel architecture and Compilation Techniques (PACT)

作者： Lunkai Zhang Dmitri Strukov Hebatallah Saadeldeen Dongrui Fan Mingzhe Zhang Diana Franklin Department of Computer Science ICT Chinese Academy of Sciences Electrical and Computer Engineering State Key Laboratory of Computer Architecture ICT Chinese Academy of Sciences ICT Key Lab of Intelligent Information Processing

ISBN: (纸本)9781509066070

Cache-coherent shared memory is critical for programmability in many-core systems. Several directory-based schemes have been proposed, but dynamic, non-uniform sharing make efficient directory storage challenging, with each giving up storage space, performance or energy. We introduce SpongeDirectory, a sparse directory structure that exploits multi-level memristory technology. SpongeDirectory expands directory storage in-place when needed by increasing the number of bits stored on a single memristor device, trading latency and energy for storage. We explore several SpongeDirectory configurations, finding that a provisioning rate of 0.5× with memristors optimized for low energy consumption is the most competitive. This optimal SpongeDirectory configuration has performance comparable to a conventional sparse directory, requires 18× less storage space, and consumes 8× less energy.

关键词： Memristors Coherence Resistance Benchmark testing System-on-chip Random access memory Performance evaluation

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26th Annual Computational Neuroscience Meeting (CNS*2017) of the Organization for Computational Neuroscience Antwerp, Belgium, July 15-20, 2017

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BMC NEUROSCIENCE 2017年第SUPPL 1期18卷 59-59页

作者： [Anonymous] Indiana University Purdue University Indianapolis Indianapolis IN 46032 USA Stark Neurosciences Research Institute Indiana University School of Medicine Indianapolis IN 46032 USA Department of Mathematics East Carolina University Greenville NC 27858 USA Jülich Supercomputing Centre Forschungszentrum Jülich 52425 Jülich Germany Future Systems Swiss National Supercomputing Centre 8092 Zurich Switzerland User Engagement and Support Swiss National Supercomputing Centre 6900 Lugano Switzerland Institut de Neurosciences des Systèmes Aix Marseille Univ 13005 Marseille France Simulation Lab Neuroscience Forschungszentrum Jülich Jülich Germany Department of Experimental Psychology Ghent University 9000 Ghent Belgium Donders Center for Cognitive Neuroimaging Radboud University 6525HR Nijmegen The Netherlands Department of Electrical Computer and Energy Engineering University of Colorado Boulder CO 80309 USA Department of Neurosurgery Johns Hopkins School of Medicine Baltimore MD 21287 USA Department of Neurology Johns Hopkins School of Medicine Baltimore MD 21287 USA Department of Otolaryngology Johns Hopkins School of Medicine Baltimore MD 21287 USA INSERM U968 Paris France Sorbonne Universités UPMC University Paris 06 UMR_S 968 Institut de la Vision Paris France CNRS UMR_7210 Paris France Department of Computer Architecture and Technology University of Granada (CITIC) Granada Spain Sorbonne Universités UPMC Univ Paris 06 INSERM CNRS Institut de la Vision Paris France Department of Adaptive Machine Systems Osaka University Osaka Japan Department of Computer Science University of Cergy-Pontoise Cergy-Pontoise France Department of Physics and Astronomy College of Charleston Charleston SC 29424 USA School of Physics Faculty of Science University of Sydney Sydney NSW 2006 Australia Center of Excellence for Integrative Brain Function Australian Research Council Sydney Australia Max Planck Institute for Human Cognitive and Brain Sciences Saxony Lei

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The DeSyRe Runtime Support for Fault-Tolerant Embedded MPSoCs

The DeSyRe Runtime Support for Fault-Tolerant Embedded MPSoC...

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International Symposium on Parallel and Distributed Processing with Applications, ISPA

作者： Dionisios Pnevmatikatos Stavros Tzilis Ioannis Sourdis Computer Architecture & VLSI Syst. Lab. Institute of Computer Science Foundation for Research and Technology - Hellas (FORTH) Heraklion- Crete Greece Computer Science and Engineering Dept. Chalmers University of Technology Gothenburg Sweden

Semiconductor technology scaling makes chips more sensitive to faults. This paper describes the DeSyRe design approach and its runtime management for future reliable embedded Multiprocessor Systems-on-Chip (MPSoCs). A light weight runtime system is described for shared-memory MPSoCs to support fault-tolerant execution upon detection of transient and permanent faults. The DeSyRe runtime system offers re-execution of tasks that suffer from transient faults and task-migration in cases where a worker processor is permanently faulty. In addition, a faulty worker can potentially remain usable, increasing systems fault-tolerance. This is achieved using alternative task implementations, which avoid the faulty circuit and are indicated in the application-code via pragma annotations, as well as by repairing a faulty core via hardware reconfiguration. Thereby, the system can be dynamically adapted using one or multiple of the above mechanisms to mitigate faults. The DeSyRe runtime system is evaluated using micro-benchmarks running on a Virtex-6 FPGA MPSoC. Results suggest that our enhance default-tolerant runtime system can successfully and efficiently execute all application tasks under a variety of fault cases.

关键词： Runtime Fault tolerance Fault tolerant systems Transient analysis System-on-chip Circuit faults Hardware

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YaSpMV: Yet another SpMV framework on GPUs 14

YaSpMV: Yet another SpMV framework on GPUs

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Proceedings of the 19th ACM SIGPLAN symposium on Principles and practice of parallel programming

作者： Yan, Shengen Li, Chao Zhang, Yunquan Zhou, Huiyang Institute of Software Chinese Academy of Sciences University of Chinese Academy of Sciences Beijing China North Carolina State University RaleighNC United States State Key Lab of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Institute of Software Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781450326568

SpMV is a key linear algebra algorithm and has been widely used in many important application domains. As a result, numerous attempts have been made to optimize SpMV on GPUs to leverage their massive computational throughput. Although the previous work has shown impressive progress, load imbalance and high memory bandwidth remain the critical performance bottlenecks for SpMV. In this paper, we present our novel solutions to these problems. First, we devise a new SpMV format, called blocked compressed common coordinate (BCCOO), which uses bit flags to store the row indices in a blocked common coordinate (COO) format so as to alleviate the bandwidth problem. We further improve this format by partitioning the matrix into vertical slices to enhance the cache hit rates when accessing the vector to be multiplied. Second, we revisit the segmented scan approach for SpMV to address the load imbalance problem. We propose a highly efficient matrix-based segmented sum/scan for SpMV and further improve it by eliminating global synchronization. Then, we introduce an auto-tuning framework to choose optimization parameters based on the characteristics of input sparse matrices and target hardware platforms. Our experimental results on GTX680 GPUs and GTX480 GPUs show that our proposed framework achieves significant performance improvement over the vendor tuned CUSPARSE V5.0 (up to 229% and 65% on average on GTX680 GPUs, up to 150% and 42% on average on GTX480 GPUs) and some most recently proposed schemes (e.g., up to 195% and 70% on average over clSpMV on GTX680 GPUs, up to 162% and 40% on average over clSpMV on GTX480 GPUs). Copyright © 2014 ACM.

关键词： Graphics processing unit

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Quantitative Comparison of the Power Reduction Techniques for Samsung Reconfigurable Processor

Quantitative Comparison of the Power Reduction Techniques fo...

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IEEE International Symposium on Circuits and Systems

作者： Hoyoung Kim Soojung Ryu Abhishek Sinkar Nam Sung Kim Processor Architecture Lab. SAIT Samsung Electronics Yongin Republic of Korea Department of Electrical and Computer Engineering University of Wisconsin Madison Madison WI USA

ISBN: (纸本)9781479934331

With significant growth in portable multimedia devices such as smartphones, application processors (AP) play a critical role for running various multimedia applications on these devices. By considering the power constraints of such devices, we often integrate reconfigurable processors (RPs) into APs. This is because RPs offer flexibility and good performance, thereby greatly improving the power efficiency for running these multimedia applications. Like many other processors, RPs also exploit the dynamic voltage/frequency scaling (DVFS) to improve their power efficiency. Owing to the platform cost constraints, however, these RPs are often integrated to low dropout (LDO) voltage regulators (VRs) instead of switching VRs. When compared with switching VRs, LDO VRs are very inexpensive;however, they suffer from considerable power loss when they are required to deliver a low output voltage. However, many previous studies focused on analyzing the power efficiency of various DVFS techniques only with regard to the processors and did not consider the negative impact of the VR power losses on the overall power efficiency of the platform. In this work, we quantitatively compare the power efficiency of a Samsung RP (SRP) adopting the race-to-halt technique with that of the SRP exploiting the DVFS supported by LDO VRs, by considering the effect of the VR power losses. Finally, we demonstrate that using the race-to-halt technique results in high power efficiency when compared with the DVFS in a commercial processor, by considering the VR power efficiency.

关键词： Samsung reconfigurable processor dynamic voltage frequency scaling race-to-halt low dropout voltage regulator

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BioTIME 2.0: Expanding and Improving a Database of Biodiversity Time Series

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Global Ecology and Biogeography 2025年第5期34卷

作者： Maria Dornelas Laura H. Antão Amanda E. Bates Viviana Brambilla Jonathan M. Chase Cher F. Y. Chow Ada Fontrodona-Eslava Anne E. Magurran Inês S. Martins Faye Moyes Alban Sagouis Samuel Adu-Acheampong Daniel Acquah-Lamptey Dušan Adam Penelope A. Ajani Aitor Albaina Pablo Almaraz Jeongseop An Roger Sigismund Anderson Madelaine Jean Robertson Anderson Alexsander Z. Antunes Ivan Arismendi Linda Armbrecht Pedro Aros-Mardones Sreejith Kalpuzha Ashtamoorthy Narayanan Ayyappan Gal Badihi Joseph J. Bailey Andrew H. Baird Mark Edward Baird Sreekumar Vadakkethil Balakrishnan José António L. Barão-Nóbrega Adi Barash Miguel Barbosa Jos Barlow Claus Bässler Matthieu Beaumont Natalie Beenaerts Tiago Octavio Begot Wallace Beiroz Ricardo Beldade David M. Bell Alecia Bellgrove Jonathan Belmaker Lisandro Benedetti-Cecchi Cassandra E. Benkwitt Pamela Medina-van Berkum Brandon T. Bestelmeyer Matthew G. Betts Maxwell Kelvin Billah Anne D. Bjorkman Magdalena Błażewicz Christopher P. Bloch Shane A. Blowes Antonio Bode Juliano A. Bogoni Thomas Bolger Timothy C. Bonebrake Erik Bonsdorff Roberta Bottarin Luke N. Brokensha Rob W. Brooker Andrew J. Brooks Helge Bruelheide Thiago Almeida Bueno Claire Laguionie Mariana Lopes Campagnoli James Cant Erica Pellegrini Caramaschi Alexandre Caron Tadhg Carroll Tancredi Caruso Juan Carvajal-Quintero Giuseppe Castaldelli Edward Castañeda-Moya Pedro V. Castilho Sonia Zanini Cechin Shahar Chaikin Uchangi Manjunatha Chandrashekara Tory J. Chase Chaolun Allen Chen Jorge José Cherem Sei-Woong Choi Erica M. Christensen Alexander V. Christianini Jackson Wing Four Chu Peter Coad Carl Van Colen Lise Comte Elisabeth J. Cooper J. Hans C. Cornelissen Eddy Cosson Unai Cotano Luc Crevecoeur Shannan Kyle Crow Graeme S. Cumming Vanessa S. Daga Gabriella Damasceno Gergana N. Daskalova Claire H. Davies Robert A. Davis Frank P. Day Sussy De-La-Zerda Amy Elizabeth Deacon Indradatta de Castro-Arrazola Steven Degraer Kharran Deonarinesingh Juan C. Diaz-Ricaurte Christopher R. Dickman Tara Dirilgen Ciaran John Dolan J. Emmet Centre for Biological Diversity School of Biology University of St Andrews Fife UK MARE—Centro de Ciências do Mar e do Ambiente Faculdade de Ciências Universidade de Lisboa Lisboa Portugal Research Centre for Ecological Change Organismal and Evolutionary Biology Research Programme Faculty of Biological and Environmental Sciences University of Helsinki Helsinki Finland Department of Biology University of Victoria Victoria British Columbia Canada German Centre for Integrative Biodiversity Research (iDiv) Halle-Jena-Leipzig Leipzig Germany Department of Computer Science Martin Luther University Halle-Wittenberg Halle (Saale) Germany Leverhulme Centre for Anthropocene Biodiversity Department of Biology University of York York UK Department of Animal Biology and Conservation Science University of Ghana Accra Ghana Philipps Universität Marburg Marburg Germany Department of Forest Ecology Silva Tarouca Research Institute Brno Czech Republic School of Life Sciences University of Technology Sydney Sydney New South Wales Australia Zoology and Animal Cell Biology Department University of the Basque Country (UPV/EHU) Leioa Spain Grupo de Oceanografía de Ecosistemas Instituto de Ciencias Marinas de Andalucía CSIC Campus Universitario de Puerto Real Puerto Real Spain National Institute of Ecology Seocheon Republic of Korea African Regional Postgraduate Programme in Insect Science University of Ghana Accra Ghana Département de Biologie Université de Sherbrooke Sherbrooke Quebec Canada Núcleo de Conservação da Biodiversidade Instituto de Pesquisas Ambientais Secretaria de Meio Ambiente Infraestrutura e Logística do Estado de São Paulo São Paulo Brazil Department of Fisheries Wildlife and Conservation Sciences Oregon State University Corvallis Oregon USA Institute for Marine and Antarctic Studies Ecology & Biodiversity Centre University of Tasmania Hobart Tasmania Australia Graduate Program in Oceanography Department of Oceanography Faculty of Natural Scienc

Motivation Here, we make available a second version of the BioTIME database, which compiles records of abundance estimates for species in sample events of ecological assemblages through time. The updated version expands version 1.0 of the database by doubling the number of studies and includes substantial additional curation to the taxonomic accuracy of the records, as well as the metadata. Moreover, we now provide an R package (BioTIMEr) to facilitate use of the database. Main Types of Variables Included The database is composed of one main data table containing the abundance records and 11 metadata tables. The data are organised in a hierarchy of scales where 11,989,233 records are nested in 1,603,067 sample events, from 553,253 sampling locations, which are nested in 708 studies. A study is defined as a sampling methodology applied to an assemblage for a minimum of 2 years. Spatial Location and Grain Sampling locations in BioTIME are distributed across the planet, including marine, terrestrial and freshwater realms. Spatial grain size and extent vary across studies depending on sampling methodology. We recommend gridding of sampling locations into areas of consistent size. Time Period and Grain The earliest time series in BioTIME start in 1874, and the most recent records are from 2023. Temporal grain and duration vary across studies. We recommend doing sample-level rarefaction to ensure consistent sampling effort through time before calculating any diversity metric. Major Taxa and Level of Measurement The database includes any eukaryotic taxa, with a combined total of 56,400 taxa. Software Format csv and. SQL.

关键词： assemblage biodiversity community database ecoinformatics species taxa time

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Domain-knowledge optimized simulated annealing for network-on-chip application mapping

Advances in Intelligent Systems and Computing

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Advances in Intelligent Systems and Computing 2013年 187 AISC卷 473-487页

作者： Radu, Ciprian Vinţan, Lucian Advanced Computer Architecture and Processing Systems Research Lab Lucian Blaga University of Sibiu Sibiu Romania

ISBN: (纸本)9783642325472

Network-on-Chip architectures are scalable on-chip interconnection networks. They replace the inefficient shared buses and are suitable for multicore and manycore systems. This paper presents an Optimized Simulated Annealing (OSA) algorithm for the Network-on-Chip application mapping problem. With OSA, the cores are implicitly and dynamically clustered using knowledge about communication demands. We show that OSA is a more feasible Simulated Annealing approach to NoC application mapping by comparing it with a general Simulated Annealing algorithm and a Branch and Bound algorithm, too. Using real applications we show that OSA is significantly faster than a general Simulated Annealing, without giving worse solutions. OSA proves to be feasible for Networks-on-Chip with more than 100 nodes. Also, compared to a Branch and Bound technique, it gives better solutions, as the problem size increases, while in terms of speed and memory consumption the two algorithms are comparable.

关键词： Network-on-chip

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DEER: A distributed routing scheme for achieving network energy efficiency

DEER: A distributed routing scheme for achieving network ene...

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IEEE Workshop on Local and Metropolitan Area Networks (LANMAN)

作者： Biyu Zhou Lin Wang Fa Zhang Xibo Jin Zhiyong Liu University of Chinese Academy of Sciences Beijing China Key Lab of Intelligent Information Processing CAS Beijing China State Key Laboratory for Computer Architecture CAS Beijing China

ISBN: (纸本)9781479948932

The rapid growth of Internet services has brought emergent concerns over network energy efficiency. This study aims to improve network energy efficiency using power-down technique. We propose DEER, a fully distributed routing scheme. The main concept of DEER is to dynamically allocate the traffic demands in the nodes so that some links connected to the nodes can be put into sleep mode, thus reducing the energy consumption. The special features of DEER include that it does not need global traffic matrix of the network and that it uses only the local information of link loads, making DEER be able to be implemented in a distributed manner without centralized control. We develop algorithms in DEER to dynamically change the link state (into active or sleep mode) according to link utilization and to balance the loads of links by adjusting the link weights. With the traffic load varying over time, the link state transformation is triggered when any of the pre-defined thresholds is violated. Extensive simulations with the network topology and real traffic traces from the GÉANT network confirm that by involving DEER, up to 50% of the links can be put into sleep while the frequency of chaining the state of a link stays fairly low.

关键词： Routing Telecommunication traffic Energy efficiency Routing protocols Network topology Energy consumption

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