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LUBRICK: A SILICON ASSEMBLER AND ITS APPLICATION TO DATA-PATH DESIGN FOR FISC.

LUBRICK: A SILICON ASSEMBLER AND ITS APPLICATION TO DATA-PAT...

VLSI 83: VLSI Design of Digital Systems, Proceedings of the IFIP TC 10/WG 10. 5 International Conference on Very Large Scale Integration.

作者： Schoellkopf, Jean-Pierre IMAG Lab Computer Architecture Research Group St. Martin d'Heres Fr IMAG Lab Computer Architecture Research Group St. Martin d'Heres Fr

ISBN: (纸本)0444867511

The 'Familiar Instruction Set computer' (FISC) project is an application of the CAPRI Silicon Compiler project to implement 'computer-like' VLSI chips defined by their behavior. The paper first presents a 'Silicon Assembler' LUBRICK, which allows hierarchical design of functional cells according to basic interconnection structures, to obtain a good result in terms of silicon area and correctness. The inter-connection problems are emphasized. In a second part of the paper, the data-path design for FISC is presented, to show how bit-sliced structures can be designed in a short time using the silicon assembler.

关键词： INTEGRATED CIRCUITS, VLSI

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The trading function in action 7

The trading function in action

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7th Workshop on ACM SIGOPS European Workshop: Systems Support for Worldwide Applications, EW 1996

作者： Jacob, Bruce Mudge, Trevor Advanced Computer Architecture Lab EECS Department University of Michigan United States

ISBN: (纸本)9781450373395

This paper describes a commercial software and hardware platform for telecommunications and multimedia processing. The software architecture loosely follows the CORBA and ODP standards of distributed computing and supports a number of application types on different hardware configurations. This paper is the result of lessons learned in the process of designing, building, and modifying an industrial telecommunications platform. In particular, the use of the trading function in the design of the system led to such benefits as support for the dynamic evolution of the system, the ability to dynamically add services and data types to a running system, support for heterogeneous systems, and a simple design performing well enough to handle traffic in excess of 40,000 busy-hour calls.

关键词： Commerce

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Implementation of the XY2-100 protocol on low-cost microcontroller 14

Implementation of the XY2-100 protocol on low-cost microcont...

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14th International SoC Design Conference, ISOCC 2017

作者： Van Luan, Dinh Truong, Nguyen Xuan Kim, Hyun Lee, Hyuk-Jae Computer Architecture and Parallel Processing Lab Seoul National University Korea Republic of

ISBN: (纸本)9781538622858

To communicate with a controller board, several deflection systems use the digital XY2-100 protocol which is not equipped on most microcontroller units (MCUs). This paper presents a solution to implement the XY2-100 protocol using an 8-bit low-cost AVR RISC Microcontroller. By taking full advantages of the processor and optimizing the parity bit computation code, the MCU sends the data at the speed up to 3.3 Mbits/s. The program is used to control a galvanometric scanner and this can further be used for various systems such as CNC and 3D printer machines. © 2017 IEEE.

关键词： Microcontrollers

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Prevention flow-control for low latency torus networks-on-chip 11

Prevention flow-control for low latency torus networks-on-ch...

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Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip

作者： Joshi, Arpit Mutyam, Madhu Computer Architecture and Systems Lab. Department of Computer Science and Engineering Indian Institute of Technology Madras India

ISBN: (纸本)9781450307208

The challenge for on-chip networks is to provide low latency communication in a very low power budget. To reduce the latency and keep the simplicity of a mesh network, torus network is proposed. As torus networks have inherent circular dependency, additional effort is needed to prevent deadlock, even if deadlock free routing algorithms are used. We describe a novel flow-control mechanism to address cost/performance constraints in torus networks and ensure freedom from deadlock. Flow-control is achieved using a prevention mechanism which uses virtual cut-through switching, and deadlock freedom is achieved by considering only a single packet buffer per input port. We can simplify the router design by having a simple switch allocator, which prioritizes in-flight packets, and a single packet buffer per input port, which eliminates the need for virtual channels. Experimental validation reveals that our design achieves significant improvement in throughput, as compared to the traditional design, using significantly fewer buffers. © 2011 ACM.

关键词： Flow control

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A MAPLE PACKAGE OF AUTOMATED DERIVATION OF HOMOTOPY ANALYSIS SOLUTION FOR PERIODIC NONLINEAR OSCILLATIONS

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Journal of Systems Science & Complexity 2012年第3期25卷 594-616页

作者： Yinping LIU Shijun LIAO Zhibin LI Department of Computer Science and Technology East China Normal University State Key Lab of Ocean Engineering School of Naval ArchitectureOcean and Civil EngineeringDepartment of MathematicsShanghai Jiaotong University Department of Computer Science East China Normal University

Based on the homotopy analysis method, a general analytic technique for strongly nonlinear problems, a Maple package of automated derivation （ADHO） for periodic nonlinear oscillation systems is presented. This Maple package is valid for periodic oscillation systems in rather general, and can automatically deliver the accurate approximations of the frequency co and the mean of motion δof a nonlinear periodic oscillator. Based on the homotopy analysis method which is valid even for highly nonlinear problems, this Maple package can give accurate approximate expressions even for nonlinear oscillation systems with strong nonlinearity. Besides, the package is user-friendly： One just needs to input a governing equation and initial conditions, and then gets satisfied analytic approximations in few seconds. Several different types of examples are given in this paper to illustrate the validity of this Maple package. Such kind of package provides us a helpful and easy-to-use tool in science and engineering to analyze periodic of this Maple package from the is published publicly. nonlinear oscillations. And it is free address http：//*** to download the electronic version ***/*** once the paper

关键词： Automated derivation homotopy analysis method homotopy Pade technique nonlinear oscillation Wu＇s elimination method.

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An adiabatic framework for a low energy μ-architecture and compiler 7

An adiabatic framework for a low energy μ-architecture and ...

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7th Workshop on Interaction between Compilers and computer architectures, INTERACT-7 2003

作者： Ramarao, Pramod Tyagi, Akhilesh Computer Architecture Lab Department of Electrical and Computer Engineering Iowa State University AmesIA United States

ISBN: (纸本)0769518893

Adiabatic process in thermodynamics transfers energy across zero temperature difference. The adiabatic CMOS design style attempts to switch a transistor to transfer energy across its source and drain while the voltage difference is zero. We define an adiabatic micro-architecture that pushes instructions across zero IPC gradient. The IPC gradient can be zero across time: for the same stage IPC over time does not vary, or across space: adjacent pipeline stages have zero variance. The reason to consider adiabatic micro-architectures is that the energy for a given computation can be shown to be minimum for an adiabatic micro-architecture. An adiabatic compiler, really a back-end, is defined to be a compiler to support an adiabatic micro-architecture achieve its goals. The minimal support provided by an adiabatic compiler includes a static estimation of program ILP. We add new passes to the MachineSUIF compiler, to flag instruction groups that can potentially walk through a superscalar pipeline as a group. Hence, these instruction groups offer a fairly robust model of superscalar microarchitecture ILP. A compile time scheduling analysis can also generate instruction slack values. The slack indicates the program region within which an instruction can be scheduled. We also present a dispatch stage dynamic scheduling algorithm that utilizes the compiler annotated slacks to reschedule instructions with the explicit objective of minimizing the dispatch stage IPC variance. In other words, the proposed dispatch stage is adiabatic. Preliminary experimental results demonstrate an average reduction of 4.16% in IPC variance over SPEC2000 benchmarks with the adiabatic compiler and microarchitecture. The preliminary evaluation also shows the average processor dispatch stage energy reduction of 3.9% over the same SPEC2000 benchmarks. We expect to add similar IPC smoothening control knobs at instruction fetch and issue stages as well in the future, which should result in a more signifi

关键词： computer architecture

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POSTER: STAR (Space-Time Adaptive and Reductive) Algorithms for Real-World Space-Time Optimality

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ACM SIGPLAN Notices 2017年第8期52卷 455-456页

作者： Tang, Yuan You, Ronghui School of Computer Science School of Software Fudan University Shanghai Key Lab. of Intelligent Information Processing State Key Lab. of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China

It's important to hit a space-time balance for a real-world algorithm to achieve high performance on modern shared-memory multi-core or many-core systems. However, a large class of dynamic programs with more than $O(1)$ dependency achieve optimality either in space or time, but not both. In the literature, the problem is known as the fundamental space-time tradeoff. By exploiting properly on the runtime system, we show that our STAR (Space-Time Adaptive and Reductive) technique can help these dynamic programs to achieve sublinear parallel time bounds while still maintaining work-, space-, and cache-optimality in a processor- and cache-oblivious fashion. © 2017 ACM.

关键词： Real time systems

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Optimal local register allocation for a multiple-issue machine 94

Optimal local register allocation for a multiple-issue machi...

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Proceedings of the 1994 International Conference on Supercomputing

作者： Meleis, W.M. Davidson, E.S. Advanced Computer Architecture Lab Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI

ISBN: (纸本)9780897916653

This paper presents an algorithm that allocates registers optimally for straight-line code running on a generic multi-issue computer. On such a machine, an optimal register allocation is one that minimizes the number of issue slots that the code requires. Optimal spill selection and load/store placement are used to minimize the number of additional issue slots needed, given a schedule for the non-memory reference instructions and a fixed number of available physical registers. The generic multi-issue machine model closely models the operation of vector and VLIW processors, and could be extended to model super-scalar processors. The algorithm uses dynamic programming to search the state space of feasible register allocations; implicit and explicit state pruning are used to make the problem tractable without sacrificing optimality. The optimal allocation produced by the algorithm for a substantial example is presented.

关键词： Dynamic programming

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Reliability-aware data placement for partial memory protection in embedded processors 06

Reliability-aware data placement for partial memory protecti...

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2006 ACM SIGPLAN Workshop on Memory Systems Performance and Correctness, MSPC 2006

作者： Mehrara, Mojtaba Austin, Todd Advanced Computer Architecture Lab. University of Michigan Ann Arbor MI 48109

ISBN: (纸本)1595935789

Low cost protection of embedded systems against soft errors has recently become a major concern. This issue is even more critical in memory elements that are inherently more prone to transient faults. In this paper, we propose a reliability aware data placement technique in order to partially protect embedded memory systems. We show that by adopting this method instead of traditional placement schemes with complete memory protection, an acceptable level of fault tolerance can be achieved while incurring less area and power overhead. In this approach, each variable in the program is placed in either protected or non-protected memory area according to the profile-driven liveness analysis of all memory variables. In order to measure the level of fault coverage, we inject faults into the memory during the course of program execution in a Monte Carlo simulation framework. Subsequently, we calculate the coverage of partial protection scheme based on the number of protected, failed and crashed runs during the fault injection experiment. Copyright 2006 ACM.

关键词： Program processors

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Ultra low-cost defect protection for microprocessor pipelines

Ultra low-cost defect protection for microprocessor pipeline...

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作者： Shyam, Smitha Constantinides, Kypros Phadke, Sujay Bertacco, Valeria Austin, Todd Advanced Computer Architecture Lab. University of Michigan Ann Arbor MI 48109

ISBN: (纸本)1595934510

The sustained push toward smaller and smaller technology sizes has reached a point where device reliability has moved to the forefront of concerns for next-generation designs. Silicon failure mechanisms, such as transistor wearout and manufacturing defects, are a growing challenge that threatens the yield and product lifetime of future systems. In this paper we introduce the BulletProof pipeline, the first ultra low-cost mechanism to protect a microprocessor pipeline and on-chip memory system from silicon defects. To achieve this goal we combine area-frugal on-line testing techniques and system-level checkpointing to provide the same guarantees of reliability found in traditional solutions, but at much lower cost. Our approach utilizes a microarchitectural checkpointing mechanism which creates coarse-grained epochs of execution, during which distributed on-line built in self-test (BIST) mechanisms validate the integrity of the underlying hardware. In case a failure is detected, we rely on the natural redundancy of instructionlevel parallel processors to repair the system so that it can still operate in a degraded performance mode. Using detailed circuit-level and architectural simulation, we find that our approach provides very high coverage of silicon defects (89%) with little area cost (5.8%). In addition, when a defect occurs, the subsequent degraded mode of operation was found to have only moderate performance impacts, (from 4% to 18% slowdown). Copyright © 2006 ACM.

关键词： Microprocessor chips

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