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2012 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012

作者： Perez-Pena, Fernando Morgado-Estevez, Arturo Rioja-Del-Rio, Carlos Linares-Barranco, Alejandro Jimenez-Fernandez, Angel Lopez-Coronado, Juan Munoz-Lozano, Jose Luis Applied Robotics Lab High School of Engineering University of Cadiz Spain Automatic and System Engineering Department University Polytechnics of Cartagena Spain Department of Computer Architecture and Technology ETSI Computer Science University of Seville Spain

ISBN: (纸本)9781467312615

Neuromorphic engineers aim to mimic the precise and efficient mechanisms of the nervous system to process information using spikes from sensors to actuators. There are many available works that sense and process information in a spike-based way. But there are still several gaps in the actuation and motor control field in a spike-based way. Spike-based Proportional-Integrative- Derivative controllers (PID) are present in the literature. On the other hand, neuro-inspired control models as VITE (Vector Integration To End point) and FLETE (Factorization of muscle Length and muscle Tension) are also present in the literature. This paper presents another step toward the spike implementation of those neuro-inspired models. We present a spike-based ramp multiplier. VITE algorithm generates the way to achieve a final position targeted by a mobile robotic arm. The block presented is used as a gate for the way involved and it also puts the incoming movement on speed with a variable slope profile. Only spikes for information representation were used and the process is in real time. The software simulation based on Simulink and Xilinx System Generator shows the accurate adjust to the traditional processing for short time periods and the hardware tests confirm and extend the previous simulated results for any time. We have implemented the spikes generator, the ramp multiplier and the low pass filter into the Virtex-5 FPGA and connected this with an USB-AER (Address Event Representation) board to monitor the spikes. © 2012 IEEE.

关键词： Muscle

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Optimizing sparse matrix vector multiplication using cache blocking method on Fermi GPU

Optimizing sparse matrix vector multiplication using cache b...

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13th ACIS International Conference on Software Engineering, Artificial Intelligence, Networking, and Parallel/Distributed Computing, SNPD 2012

作者： Xu, Weizhi Zhang, Hao Jiao, Shuai Wang, Da Song, Fenglong Liu, Zhiyong Key Lab. of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Graduate University Chinese Academy of Sciences Beijing China

ISBN: (纸本)9780769547619

It is an important task to tune performance for sparse matrix vector multiplication (SpMV), but it is also a difficult task because of its irregularity. In this paper, we propose a cache blocking method to improve the performance of SpMV on the emerging GPU architecture. The sparse matrix is partitioned into many sub-blocks, which are stored in CSR format. With the blocking method, the corresponding part of vector x can be reused in the GPU cache, so the time spent on accessing the global memory for vector x is reduced heavily. Experimental results on GeForce GTX 480 show that SpMV kernel with the cache blocking method is 5x faster than the unblocked CSR kernel in the best case. © 2012 IEEE.

关键词： Graphics processing unit

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Interactive exploration of geospatial network visualization

Interactive exploration of geospatial network visualization

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30th ACM Conference on Human Factors in Computing Systems, CHI 2012

作者： Nagel, Till Duval, Erik Vande Moere, Andrew Interaction Design Lab. University of Applied Sciences Potsdam 14469 Potsdam Germany Dept. Computer Science KU Leuven 3001 Leuven Belgium Dept. Architecture Urbanism and Planning KU Leuven 3001 Leuven Belgium

ISBN: (纸本)9781450310161

This paper presents a tabletop visualization of relations between geo-positioned locations. We developed an interactive visualization, which enables users to visually explore a geospatial network of actors. The multitouch tabletop, and the large size of the interactive surface invite users to explore the visualization in semi-public spaces. For a case study on scientific collaborations between institutions, we applied and improved several existing techniques for a walk-up-and-use system aimed at scientists for a social setting at a conference. We describe our iterative design approach, our two implemented prototypes, and the lessons learnt from their creation. We conducted user evaluation studies at the two on-location demonstrations, which provide evidence of the prototype usability and usefulness, and its support for understanding the distribution and connectivity in a geospatial network. © 2012 ACM.

关键词： Human computer interaction

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Energy-efficient network routing with discrete cost functions

Energy-efficient network routing with discrete cost function...

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9th Annual Conference on Theory and Applications of Models of Computation, TAMC 2012

作者： Wang, Lin Fernández Anta, Antonio Zhang, Fa Hou, Chenying Liu, Zhiyong Key Lab. of Intelligent Information Processing Institute of Computing Technology Chinese Academy of Sciences China Institute IMDEA Networks Spain China State Key Lab. for Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China Graduate University of Chinese Academy of Sciences China

ISBN: (纸本)9783642299513

Energy consumption is an important issue in the design and use of networks. In this paper, we explore energy savings in networks via a rate adaptation model. This model can be represented by a cost-minimization network routing problem with discrete cost functions. We formulate this problem as an integer program, which is proved to be NP-hard. Then a constant approximation algorithm is developed. In our proposed method, we first transform the program into a continuous-cost network routing problem, and then we approximate the optimal solution by a two-step rounding process. We show by analysis that, for uniform demands, our method provides a constant approximation for the uniform network routing problem with discrete costs. A bicriteria network routing problem is also developed so that a trade-off can be made between energy consumption and network delay. Analytical results for this latter model are also presented. © 2012 Springer-Verlag.

关键词： Network routing

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Evaluating dynamics and bottlenecks of memory collaboration in cluster systems 12

Evaluating dynamics and bottlenecks of memory collaboration ...

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12th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing, CCGrid 2012

作者： Samih, Ahmad Wang, Ren Maciocco, Christian Tai, Tsung-Yuan Charlie Duan, Ronghui Duan, Jiangang Yan, Solihin Dept. of Electical and Computer Engineering North Carolina State University Raleigh NC United States System Architecture Lab. Intel Labs. Hillsboro OR United States Software and Services Group Intel Corp. Shanghai China

ISBN: (纸本)9780769546919

With the fast development of highly-integrated distributed systems (cluster systems), designers face interesting memory hierarchy design choices while attempting to avoid the notorious disk swapping. Swapping to the free remote memory through Memory Collaboration has demonstrated its cost-effectiveness compared to over provisioning the cluster for peak load requirements. Recent memory collaboration studies propose several ways on accessing the under-utilized remote memory in static system configurations, without detailed exploration of the dynamic memory collaboration. Dynamic collaboration is an important aspect given the run-time memory usage fluctuations in clustered systems. Further, as the interest in memory collaboration grows, it is crucial to understand the existing performance bottlenecks, overheads, and potential optimization. In this paper we address these two issues. First, we propose an Autonomous Collaborative Memory System (ACMS) that manages memory resources dynamically at run time to optimize performance. We implement a prototype realizing the proposed ACMS, experiment with a wide range of real-world applications, and show up to 3x performance speedup compared to a non-collaborative memory system without perceivable performance impact on nodes that provide memory. Second, we analyze, in depth, the end-to-end memory collaboration overhead and pinpoint the corresponding bottlenecks. © 2012 IEEE.

关键词： Cost effectiveness

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Towards AER VITE: building spike gate signal

Towards AER VITE: building spike gate signal

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IEEE International Conference on Electronics, Circuits and Systems

作者： Fernando Perez-Pena Arturo Morgado-Estevez Carlos Rioja-Del-Rio Alejandro Linares-Barranco Angel Jimenez-Fernandez Juan Lopez-Coronado Jose Luis Munoz-Lozano Applied Robotics Lab High School of Engineering University of Cadiz Department of Computer Architecture and Technology ETSI Computer Science University of Seville Automatic and System Engineering Department University Polytechnics of Cartagena

ISBN: (纸本)9781467312615

Neuromorphic engineers aim to mimic the precise and efficient mechanisms of the nervous system to process information using spikes from sensors to actuators. There are many available works that sense and process information in a spike-based way. But there are still several gaps in the actuation and motor control field in a spike-based way. Spike-based Proportional-Integrative-Derivative controllers (PID) are present in the literature. On the other hand, neuro-inspired control models as VITE (Vector Integration To End point) and FLETE (Factorization of muscle Length and muscle Tension) are also present in the literature. This paper presents another step toward the spike implementation of those neuro-inspired models. We present a spike-based ramp multiplier. VITE algorithm generates the way to achieve a final position targeted by a mobile robotic arm. The block presented is used as a gate for the way involved and it also puts the incoming movement on speed with a variable slope profile. Only spikes for information representation were used and the process is in real time. The software simulation based on Simulink and Xilinx System Generator shows the accurate adjust to the traditional processing for short time periods and the hardware tests confirm and extend the previous simulated results for any time. We have implemented the spikes generator, the ramp multiplier and the low pass filter into the Virtex-5 FPGA and connected this with an USB-AER (Address Event Representation) board to monitor the spikes.

关键词： spike spikes spikes Road gates Hardware Test Information representation Processing information ANION EXCHANGE RESIN Proportional Integral Derivative Control Activation Pelvic Inflammatory Disease RAMP Ramps Multiplying circuits

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Improved cryptanalysis of the VMPC stream cipher

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Journal of Computational Information Systems 2012年第2期8卷 831-838页

作者： Li, Shunbo Hu, Yupu Zhao, Yongbin Wang, Yan Department of Mathematics Xidian University Xi'an 710071 China Key Lab. of Computer Networks and Information Security Ministry of Education Xidian University Xi'an 710071 China School of Science Xi'an University of Architecture and Technology Xi'an 710055 China

VMPC is a modified RC4 stream cipher proposed in FSE 2004, which is designed especially to resist distinguishing attacks. In this paper, we present a heuristic distinguishing attack against VMPC. By finding the weakness in the first two words of a keystream with two effective assumptions, we build a distinguisher and get a considerable bias. This attack only requires about 234.02 output bytes to distinguish VMPC from truly random sequence with success probability 0.9545. Thereby, this technique is further used to the Tsunoo's method and improve his results by a factor of about 24. 1553-9105/Copyright © 2012 Binary Information Press.

关键词： Cryptography

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Free Roll Decay Modeling of a Trimaran Based on Least Square Support Vector Machine

Free Roll Decay Modeling of a Trimaran Based on Least Square...

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OCEANS Conference

作者： Jinlong Li Songlin Yang Shuo Pang National Key Lab of AUV Technology Harbin Engineering University School of Naval Architecture and Ocean Engineering Jiangsu University of Science and Technology Dept. of Electrical Computer Software Systems Engineering Embry-Riddle Aeronautical University

ISBN: (纸本)9781467308298

A trimaran is a multihulled boat consisting of a main hull and two smaller outrigger hulls, attached to the main hull with lateral struts. There have been many studies highlighting that a trimaran takes many advantages over other types of hulls especially the roll performance, because of the greater resistance to rolling that the outrigger hulls offer. In order to study the rolling motion of a trimaran, an accurate roll motion model is needed. The rolling motion of a trimaran is inherently nonlinear due to both nonlinearities in the restoring moment and damping moment. This paper presents an estimation method to predict the linear and nonlinear roll damping parameters based on free roll decay experiments of a trimaran, whose outrigger hulls are movable both along the longitudinal and transverse direction. The estimation method is based on least square support vector regression (LS-SVR) theory. In order to verify the performance of this new estimation method, the least square (LS) estimation method is also applied to identify the parameters. Both methods show satisfying performances, however models generated by LS-SVR shows less accumulated errors than models generated by LS.

关键词： Trimaran Free roll decay Support vector regression Least square

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Does low-power design imply energy efficiency for data centers?

Does low-power design imply energy efficiency for data cente...

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IEEE/ACM International Symposium on Low-Power Electronics and Design

作者： Meisner, David Wenisch, Thomas F. Advanced Computer Architecture Lab University of Michigan United States

ISBN: (纸本)9781612846590

Data center efficiency has quickly become a first-class design goal. In response, many studies have emerged from the academic community and industry using low-power design to help improve the energy efficiency of server hardware. Generally, these proposals hold the assumption that low-power design is inherently better for energy efficiency;this preconception stems mostly from great success in the mobile space with building low-power, energy-efficient systems. We observe that unlike mobile devices, constraining a data center server to a low power budget is arbitrary and higher power design choices can be more energy efficient. We analyze the energy efficiency design space of past commercial server designs and find that high-power servers are generally more energy efficient than low-power ones. Furthermore, we evaluate building low- or high-power server clusters and find that the small increase in the cost of cooling high-powered servers is easily outweighed by their greater efficiency. © 2011 IEEE.

关键词： Energy efficiency

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Prevention flow-control for low latency torus networks-on-chip 11

Prevention flow-control for low latency torus networks-on-ch...

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Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip

作者： Joshi, Arpit Mutyam, Madhu Computer Architecture and Systems Lab. Department of Computer Science and Engineering Indian Institute of Technology Madras India

ISBN: (纸本)9781450307208

The challenge for on-chip networks is to provide low latency communication in a very low power budget. To reduce the latency and keep the simplicity of a mesh network, torus network is proposed. As torus networks have inherent circular dependency, additional effort is needed to prevent deadlock, even if deadlock free routing algorithms are used. We describe a novel flow-control mechanism to address cost/performance constraints in torus networks and ensure freedom from deadlock. Flow-control is achieved using a prevention mechanism which uses virtual cut-through switching, and deadlock freedom is achieved by considering only a single packet buffer per input port. We can simplify the router design by having a simple switch allocator, which prioritizes in-flight packets, and a single packet buffer per input port, which eliminates the need for virtual channels. Experimental validation reveals that our design achieves significant improvement in throughput, as compared to the traditional design, using significantly fewer buffers. © 2011 ACM.

关键词： Flow control

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