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检索条件"机构=Computer Architecture Lab"
497 条 记 录,以下是51-60 订阅
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Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages
Total power reduction in CMOS circuits via gate sizing and m...
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42nd Design Automation Conference, DAC 2005
作者: Gao, Feng Hayes, John P. Advanced Computer Architecture Lab. University of Michigan Ann Arbor MI 48105 United States
Minimizing power consumption is one of the most important objectives in IC design. Resizing gates and assigning different Vt's are common ways to meet power and timing budgets. We propose an automatic implementati... 详细信息
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Implementing a high-performance multithreaded microprocessor: A case study in high-level design and validation
Implementing a high-performance multithreaded microprocessor...
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2009 7th IEEE-ACM International Conference on Formal Methods and Models for Co-Design, MEMOCODE '09
作者: Chung, Eric S. Hoe, James C. Computer Architecture Lab Carnegie Mellon University Carnegie Mellon Pittsburgh PA 15213 United States
We have developed a 16-way multithreaded microprocessor called BlueSPARC. This in-order, high-throughput processor incorporates complex features such as privileged operations, memory management, and a non-blocking cac... 详细信息
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Achieving full functional coverage for the forwarding unit of pipelined processors
Achieving full functional coverage for the forwarding unit o...
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2017 IEEE East-West Design and Test Symposium, EWDTS 2017
作者: Vineesh, V.S. Hage, Nihar Karthik, B Singh, Virendra Computer Architecture and Dependable Systems Lab Department of Electrical Engineering Indian Institute of Technology Bombay India
Generic instruction based testing methods do not always give good fault coverage for the complex units like Forwarding unit. Hence it becomes important to carefully craft the test which are best for different parts of... 详细信息
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Efficient dynamic scheduling through tag elimination
Efficient dynamic scheduling through tag elimination
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29th Annual International Symposium on computer architecture
作者: Ernst, Dan Austin, Todd Advanced Computer Architecture Lab. University of Michigan Ann Arbor MI 48109 United States
An increasingly large portion of scheduler latency is derived from the monolithic content addressable memory (CAM) arrays accessed during instruction wakeup. The performance of the scheduler can be improved by decreas... 详细信息
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Web services for the integration of XML-based content into learning platforms: A three-level model
Web services for the integration of XML-based content into l...
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2nd International Symposium on Leveraging Applications of Formal Methods, Verification and Validation, ISoLA 2006
作者: Kröger, Reinhold Lucke, Ulrike Schmid, Markus Tavangarian, Djamshid University of Applied Sciences Wiesbaden Distributed Systems Lab. Germany University of Rostock Institute of Computer Science Department for Computer Architecture Germany
Along with the increasing diversity of educational markup languages there is a strong need for flexible integration of such content into learning platforms. Therefore, we have identified four basic mechanisms: plain l... 详细信息
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A fault-tolerant System-on-Programmable-Chip based on Domain-Partition and blind reconfiguration
A fault-tolerant System-on-Programmable-Chip based on Domain...
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2010 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2010
作者: Shang, Lihong Zhou, Mi Hu, Yu School of Computer Science and Engineering Beihang University China Key Lab. of Computer System and Architecture ICT Chinese Academy of Sciences China
Field programmable gate arrays (FPGAs) are widely used in building Systems-on-Programmable-Chips (SOPCs) since they contain plenty of reconfigurable heterogeneous resources providing the facility to implement various ... 详细信息
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McRT-STM: A high performance software transactional memory system for a multi-core runtime
McRT-STM: A high performance software transactional memory s...
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2006 ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP'06
作者: Saha, Bratin Adl-Tabatabai, Ali-Reza Hudson, Richard L. Chi, Cao Minh Hertzberg, Benjamin Programming System Lab. Microprocessor Technology Lab. Intel Corporation Computer Architecture Lab. Stanford University Palo Alto CA
Applications need to become more concurrent to take advantage of the increased computational power provided by chip level multiprocessing. Programmers have traditionally managed this concurrency using locks (mutex bas... 详细信息
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Smart sensor architectures for embedded biosignal analysis
Smart sensor architectures for embedded biosignal analysis
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2013 7th Conference on Design and architectures for Signal and Image Processing, DASIP 2013
作者: Pfundt, Benjamin Reichenbach, Marc Eskofier, Björn Fey, Dietmar Department Computer Science Computer Architecture Friedrich-Alexander-University Erlangen-Nuremberg Germany Department Computer Science Pattern Recognition Lab Friedrich-Alexander-University Erlangen-Nuremberg Germany
In many sports and medical applications small and wearable sensors are used that capture motion and physiological signals. Yet, commonly such sensor are only capable of acquiring raw data, which is afterwards transmit... 详细信息
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HIGHLY PARALLEL computer architecture.
Denshi Gijutsu Sogo Kenkyusho Iho/Bulletin of the Electrotec...
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Denshi Gijutsu Sogo Kenkyusho Iho/Bulletin of the Electrotechnical laboratory 1985年 第5期49卷 397-401页
作者: Furuya, Tatsumi Electrotechnical Lab Computer Architecture Section Sakura-mura Jpn Electrotechnical Lab Computer Architecture Section Sakura-mura Jpn
This paper discusses a control mechanism for highly parallel computation and its implementation. The author presents an architecture featuring a hexagonal processor array and implements the dependence-driven computati... 详细信息
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Integrated network interfaces for high-bandwidth TCP/IP
Integrated network interfaces for high-bandwidth TCP/IP
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作者: Binkert, Nathan L. Saidi, Ali G. Reinhardt, Steven K. Advanced Computer Architecture Lab. Department of Electrical Engineering and Computer Science University of Michigan Hewlett-Packard Labs. Reservoir Labs Inc.
This paper proposes new network interface controller (NIC) designs that take advantage of integration with the host CPU to provide increased flexibility for operating system kernel-based performance *** believe that t... 详细信息
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