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2009 7th IEEE-ACM International Conference on Formal Methods and Models for Co-Design, MEMOCODE '09

作者： Chung, Eric S. Hoe, James C. Computer Architecture Lab Carnegie Mellon University Carnegie Mellon Pittsburgh PA 15213 United States

ISBN: (纸本)9781424448067

We have developed a 16-way multithreaded microprocessor called BlueSPARC. This in-order, high-throughput processor incorporates complex features such as privileged operations, memory management, and a non-blocking cache subsystem. When supported by a hybrid simulation technique that handles rare, unimplemented behaviors in a software host, the BlueSPARC microprocessor runs unmodified UltraSPARC III-based commercial applications on Solaris 8 while hosted on a single Xilinx XCV2P70 FPGA clocked at 90MHz. This significant effort was achieved in under one man-year using a highlevel language and a high-level validation approach. In the first part of the paper, we describe our experience in applying the Bluespec SystemVerilog (BSV) language to develop a large hardware design that must meet specific area and performance requirements. In the second part of the paper, we present the FPGA-accelerated validation approach we employed to check the correct execution of real multithreaded programs running on the BlueSPARC processor. We discuss the challenges and our solutions to validation in the presence of fullsystem interactions and microarchitectural nondeterminism. © 2009 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Achieving full functional coverage for the forwarding unit of pipelined processors

Achieving full functional coverage for the forwarding unit o...

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2017 IEEE East-West Design and Test Symposium, EWDTS 2017

作者： Vineesh, V.S. Hage, Nihar Karthik, B Singh, Virendra Computer Architecture and Dependable Systems Lab Department of Electrical Engineering Indian Institute of Technology Bombay India

ISBN: (纸本)9781538632994

Generic instruction based testing methods do not always give good fault coverage for the complex units like Forwarding unit. Hence it becomes important to carefully craft the test which are best for different parts of these units. In this paper we have identified two different test generation methods for different sections of the forwarding unit, namely muxes and comparators which offers better coverage independently: template based test instruction generation and test instruction generation from constrained test vectors. A wrapper designed using the functional constraints of the forwarding unit, is used for test generation. Both methods combined delivers fault coverage of 97.33%. A detailed analysis of the non-detected faults revealed the fact that they cannot be tested using the instruction set of the processor (MIPS 5-stage pipelined processor). This proves that the proposed method achieved 100% functional coverage for stuck-at faults in the forwarding unit. © 2017 IEEE.

关键词： Testing

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Efficient dynamic scheduling through tag elimination

Efficient dynamic scheduling through tag elimination

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29th Annual International Symposium on computer architecture

作者： Ernst, Dan Austin, Todd Advanced Computer Architecture Lab. University of Michigan Ann Arbor MI 48109 United States

An increasingly large portion of scheduler latency is derived from the monolithic content addressable memory (CAM) arrays accessed during instruction wakeup. The performance of the scheduler can be improved by decreasing the number of tag comparisons necessary to schedule instructions. Using detailed simulation-based analyses, we find that most instructions enter the window with at least one of their input operands already available. By putting these instructions into specialized windows with fewer tag comparators, load capacitance on the scheduler critical path can be reduced, with only very small effects on program throughput. For instructions with multiple unavailable operands, we introduce a last-tag speculation mechanism that eliminates all remaining tag comparators except those for the last arriving input operand. By combining these two tag-reduction schemes, we are able to construct dynamic schedulers with approximately one quarter of the tag comparators found in conventional designs. Conservative circuit-level timing analyses indicate that the optimized designs are 20-45% faster and require 10-20% less power, depending on instruction window size.

关键词： Associative storage

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Web services for the integration of XML-based content into learning platforms: A three-level model

Web services for the integration of XML-based content into l...

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2nd International Symposium on Leveraging Applications of Formal Methods, Verification and Validation, ISoLA 2006

作者： Kröger, Reinhold Lucke, Ulrike Schmid, Markus Tavangarian, Djamshid University of Applied Sciences Wiesbaden Distributed Systems Lab. Germany University of Rostock Institute of Computer Science Department for Computer Architecture Germany

ISBN: (纸本)0769530710

Along with the increasing diversity of educational markup languages there is a strong need for flexible integration of such content into learning platforms. Therefore, we have identified four basic mechanisms: plain linking from the platform to external content, conversion of content into the platforms native format, and service-based invocation of external content as well as specific functionality related to it. Architectural principles, benefits, and drawbacks of these concepts are compared, and exemplary realizations are described. © 2007 IEEE.

关键词： E-learning

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A fault-tolerant System-on-Programmable-Chip based on Domain-Partition and blind reconfiguration

A fault-tolerant System-on-Programmable-Chip based on Domain...

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2010 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2010

作者： Shang, Lihong Zhou, Mi Hu, Yu School of Computer Science and Engineering Beihang University China Key Lab. of Computer System and Architecture ICT Chinese Academy of Sciences China

ISBN: (纸本)9781424458875

Field programmable gate arrays (FPGAs) are widely used in building Systems-on-Programmable-Chips (SOPCs) since they contain plenty of reconfigurable heterogeneous resources providing the facility to implement various intellectual property cores. However, with the shrinking device feature size and the increasing die area, nowadays FPGAs can be deeply affected by the errors induced by electromigration and radiation, which results in challenges of building reliable SOPCs. In this paper, a SOPC implementing a smart 1553B bus node is presented to investigate the challenges and illustrate a feasible approach for building a complex system aimed at high reliability and low recovery latency on a commercial FPGA. First, a general reliability model, the Domain-Partition (DP) model, is introduced to formulate the SOPCs which contain multiple alternative configurations proving the fault recovery capability. The assignment of the alternative configurations for maximizing the reliability is then determined according to a first-order optimal solution under the DP framework. Finally, the blind reconfiguration technique is used to reduce the recovery latency. The experiments based on a Monte Carlo simulation approach are carried out to evaluate the reliability and the latency. The obtained results show that higher reliability is attainable with less overhead than the generic triple-modular redundancy method. © 2010 IEEE.

关键词： Monte Carlo methods

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McRT-STM: A high performance software transactional memory system for a multi-core runtime

McRT-STM: A high performance software transactional memory s...

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2006 ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP'06

作者： Saha, Bratin Adl-Tabatabai, Ali-Reza Hudson, Richard L. Chi, Cao Minh Hertzberg, Benjamin Programming System Lab. Microprocessor Technology Lab. Intel Corporation Computer Architecture Lab. Stanford University Palo Alto CA

ISBN: (纸本)1595931899

Applications need to become more concurrent to take advantage of the increased computational power provided by chip level multiprocessing. Programmers have traditionally managed this concurrency using locks (mutex based synchronization). Unfortunately, lock based synchronization often leads to deadlocks, makes fine-grained synchronization difficult, hinders composition of atomic primitives, and provides no support for error recovery. Transactions avoid many of these problems, and therefore, promise to ease concurrent programming. We describe a software transactional memory (STM) system that is part of McRT, an experimental Multi-Core RunTime. The McRT-STM implementation uses a number of novel algorithms, and supports advanced features such as nested transactions with partial aborts, conditional signaling within a transaction, and object based conflict detection for C/C++ applications. The McRT-STM exports interfaces that can be used from C/C++ programs directly or as a target for compilers translating higher level linguistic constructs. We present a detailed performance analysis of various STM design tradeoffs such as pessimistic versus optimistic concurrency, undo logging versus write buffering, and cache line based versus object based conflict detection. We also show a MCAS implementation that works on arbitrary values, coexists with the STM, and can be used as a more efficient form of transactional memory. To provide a baseline we compare the performance of the STM with that of fine-grained and coarse-grained locking using a number of concurrent data structures on a 16-processor SMP system. We also show our STM performance on a non-synthetic workload - the Linux sendmail application. Copyright © 2006 ACM.

关键词： Data storage equipment

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Smart sensor architectures for embedded biosignal analysis

Smart sensor architectures for embedded biosignal analysis

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2013 7th Conference on Design and architectures for Signal and Image Processing, DASIP 2013

作者： Pfundt, Benjamin Reichenbach, Marc Eskofier, Björn Fey, Dietmar Department Computer Science Computer Architecture Friedrich-Alexander-University Erlangen-Nuremberg Germany Department Computer Science Pattern Recognition Lab Friedrich-Alexander-University Erlangen-Nuremberg Germany

ISBN: (纸本)9791092279016

In many sports and medical applications small and wearable sensors are used that capture motion and physiological signals. Yet, commonly such sensor are only capable of acquiring raw data, which is afterwards transmitted to a smartphone or other mobile computing device where processing and classification is carried out. This results in limited usability because another device has to be worn. Moreover, high power consumption due to continuous transmission is a main disadvantage. Therefore, we propose a smart sensor approach that can alleviate these problems by carrying out the processing on the sensor itself. To house the processing schemes in the sensor node we developed a new computer architecture utilizing an FPGA and an ASIC. To show the benefits of the in-sensor processing, we chose two representative biosensor applications: a movement and fall detection system for the elderly and a swimming style recognition system for professional athletes. Compared to conventional approaches the same classification rate can be achieved while saving space, power, weight and setup costs.

关键词： Field programmable gate arrays (FPGA)

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HIGHLY PARALLEL computer architecture.

Denshi Gijutsu Sogo Kenkyusho Iho/Bulletin of the Electrotec...

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Denshi Gijutsu Sogo Kenkyusho Iho/Bulletin of the Electrotechnical laboratory 1985年第5期49卷 397-401页

作者： Furuya, Tatsumi Electrotechnical Lab Computer Architecture Section Sakura-mura Jpn Electrotechnical Lab Computer Architecture Section Sakura-mura Jpn

This paper discusses a control mechanism for highly parallel computation and its implementation. The author presents an architecture featuring a hexagonal processor array and implements the dependence-driven computation model. The machine implements the dependence graph connecting the single assignment block (SAB) nodes. The SAB is a function which assigns data to a group of variables only once. The dependence between SAB's is implemented by an activation signal and a dynamic memory. The SAB is activated by the activation signal. The data is sent through the dynamic memory. The SAB's are synchronized by the memory. Each SAB is explained by a data-flow graph. The graph is mapped directly onto the array of the processing element. Three types of parallelism are implemented: (i) Direct mapped data-flow of SAB, (ii) Pipeline between SAB's, (iii) Parallel processing of SAB's.

关键词： computer SYSTEMS, DIGITAL

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Integrated network interfaces for high-bandwidth TCP/IP

Integrated network interfaces for high-bandwidth TCP/IP

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作者： Binkert, Nathan L. Saidi, Ali G. Reinhardt, Steven K. Advanced Computer Architecture Lab. Department of Electrical Engineering and Computer Science University of Michigan Hewlett-Packard Labs. Reservoir Labs Inc.

ISBN: (纸本)1595934510

This paper proposes new network interface controller (NIC) designs that take advantage of integration with the host CPU to provide increased flexibility for operating system kernel-based performance *** believe that this approach is more likely to meet the needs of current and future high-bandwidth TCP/IP networking on end hosts than the current trend of putting more complexity in the NIC, while avoiding the need to modify applications and protocols. This paper presents two such NICs. The first, the simple integrated NIC (SINIC), is a minimally complex design that moves the responsibility for managing the network FIFOs from the NIC to the kernel. Despite this closer interaction between the kernel and the NIC, SINIC provides performance equivalent to a conventional DMA-based NIC without increasing CPU overhead. The second design, V-SINIC, adds virtual per-packet registers to SINIC, enabling parallel packet processing while maintaining a FIFO model. V-SINIC allows the kernel to decouple examining a packet's header from copying its payload to memory. We exploit this capability to implement a true zero-copy receive optimization in the Linux 2.6 kernel, providing bandwidth improvements of over 50% on unmodified sockets-based receive-intensive benchmarks. Copyright © 2006 ACM.

关键词： Interfaces (computer)

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Estimation of hardware task reliability on partially reconfigurable FPGAs 16

Estimation of hardware task reliability on partially reconfi...

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16th European Conference on Radiation and Its Effects on Components and Systems, RADECS 2016

作者： Ramezani, Reza Clement, Juan Antonio Sedaghat, Yasser Mecha, Hortensia DDEmS Lab Department of Computer Engineering Ferdowsi University of Mashhad Mashhad Iran Computer Architecture Department Universidad Complutense de Madrid Madrid28040 Spain

ISBN: (纸本)9781509043668

This paper presents a novel statistical model to estimate the reliability and number of errors of hardware tasks running on partially reconfigurable FPGAs in harsh environments. The proposed model has been validated by means of fault injection. The obtained results endorsed by the 95% confidence interval reveal the high accuracy of the proposed reliability model. © 2016 IEEE.

关键词： Field programmable gate arrays (FPGA)

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