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16th European Conference on Radiation and Its Effects on Components and Systems, RADECS 2016

作者： Ramezani, Reza Clement, Juan Antonio Sedaghat, Yasser Mecha, Hortensia DDEmS Lab Department of Computer Engineering Ferdowsi University of Mashhad Mashhad Iran Computer Architecture Department Universidad Complutense de Madrid Madrid28040 Spain

ISBN: (纸本)9781509043668

This paper presents a novel statistical model to estimate the reliability and number of errors of hardware tasks running on partially reconfigurable FPGAs in harsh environments. The proposed model has been validated by means of fault injection. The obtained results endorsed by the 95% confidence interval reveal the high accuracy of the proposed reliability model. © 2016 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Optimal hardware pattern generation for functional BIST

Optimal hardware pattern generation for functional BIST

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Design, Automation and Test in Europe Conference and Exhibition 2000, DATE 2000

作者： Cataldo, Silvia Chiusano, Silvia Prinetto, Paolo Wunderlich, Hans-Joachim Politecnico di Torino Dipartimento di Automatica e Informatica Italy Computer Architecture Lab University of Stuttgart Germany

Functional BIST is a promising solution for self-testing complex digital systems at reduced costs in terms of area and performance degradation. The present paper addresses the computation of optimal seeds for an arbitrary sequential module to be used as a hardware test pattern generator. Up to now, only linear feedback shift registers and accumulator based structures have been used for deterministic test pattern generation by reseeding. In this paper, a method is proposed which can be applied to general finite state machines. Nevertheless the method is absolutely general, for sake of comparison with previous approaches, in this paper an accumulator based unit is assumed as pattern generator module. Experiments prove the effectiveness of the approach which outperforms previous results for accumulators, in terms of test size and test time, without sacrificing the fault detection capability. © 2000 IEEE.

关键词： Fault detection

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An automatic design space exploration framework for multicore architecture optimizations

An automatic design space exploration framework for multicor...

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作者： Calborean, Horia Vinţan, Lucian Advanced Computer Architecture and Processing Systems Research Lab. Lucian Blaga University of Sibiu Romania

ISBN: (纸本)9781424473359

During the last years, especially due to the computing systems complexity growth, the need for tools which perform automatic design space exploration becomes more and more stringent. This paper presents a new initiated project having as the main aim developing a software tool, called FADSE (Framework for Automatic Design Space Exploration), that comes to meet this need. It is intended to provide out-of-the- box algorithms capable of solving single and multiobjective optimization problems. It focuses on automatic design space exploration for multicore and manycore systems. This tool is intended to be ftexible, to provide easy development and portability.

关键词： Multiobjective optimization

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Optimizing application mapping algorithms for NoCs through a unified framework

Optimizing application mapping algorithms for NoCs through a...

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作者： Radu, Ciprian Vintan, Lucian Advanced Computer Architecture and Processing Systems Research Lab. Lucian Blaga University Sibiu Romania

ISBN: (纸本)9781424473359

This paper presents a preliminary PhD research towards developing a framework to evaluate and optimize application mapping algorithms for Network-on-Chip architectures. Several such algorithms have been proposed for mapping the threads of a parallel application on a NoC architecture. However, the performance of those algorithms is evaluated only on some specific NoC designs. A unified approach for evaluating such algorithms allows a better comparison of their performance and can potentially lead to some optimizations. The proposed framework is intended to be flexible so that the algorithms can be tested on different NoC designs. To this end, a scalable and flexible Network-on-Chip simulator is proposed. Some preliminary results obtained with this simnlator are presented, too. They show the flexibility of this simulator and that it is feasible for addressing the application mapping problem in a unified manner.

关键词： Network-on-chip

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A design space evaluation of grid processor architectures

A design space evaluation of grid processor architectures

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34th Annual International Symposium on Microarchitecture ACM/IEEE 2001

作者： Nagarajan, Ramadass Sankaralingam, Karthikeyan Burger, Doug Keckler, Stephen W. Comp. Architecture and Technol. Lab. Department of Computer Sciences University of Texas Austin TX United States

In this paper, we survey the design space of a new class of architectures called Grid Processor architectures (GPAs). These architectures are designed to scale with technology, *** clock rates than conventional architectures while providing superior instruction-level parallelism on traditional workloads and high performance across a range of application classes. A GPA consists of an array of ALUs, each with limited control, connected by a thin operand network. Programs are executed by mapping blocks of statically scheduled instructions to the ALU array and executing them dynamically in dataflow order. This organization enables the critical paths of instruction blocks to be executed on chains of ALUs without transmitting temporary values back to the register file, avoiding most of the large, unscalable structures that limit the scalability of conventional architectures. Finally, we present simulation results of a preliminary design, the GPA-1. With a half-cycle routing delay, we obtain performance roughly equal to an ideal 8-way, 512-entry window superscalar core. With no inter-ALU delay, perfect memory, and perfect branch prediction, the IPC of the GPA-1 is more than twice that of the ideal superscalar core, achieving an average of 11 IPC across nine SPEC CPU2000 and Mediabench benchmarks.

关键词： computer architecture

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Modeling communication in cache-coherent SMP systems - A case study with Xeon Phi

Modeling communication in cache-coherent SMP systems - A cas...

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22nd ACM International Symposium on High-Performance Parallel and Distributed Computing, HPDC 2013

作者： Ramos, Sabela Hoefler, Torsten Computer Architecture Group University of A Coruña A Coruña Spain Scalable Parallel Computing Lab. ETH Zurich Zurich Switzerland

ISBN: (纸本)9781450319102

Most multi-core and some many-core processors implement cache coherency protocols that heavily complicate the design of optimal parallel algorithms. Communication is performed implicitly by cache line transfers between cores, complicating the understanding of performance properties. We developed an intuitive performance model for cache-coherent architectures and demonstrate its use with the currently most scalable cache-coherent many-core architecture, Intel Xeon Phi. Using our model, we develop several optimal and optimized algorithms for complex parallel data exchanges. All algorithms that were developed with the model beat the performance of the highly-tuned vendor-specific Intel OpenMP and MPI libraries by up to a factor of 4.3. The model can be simplified to satisfy the tradeoff between complexity of algorithm design and accuracy. We expect that our model can serve as a vehicle for advanced algorithm design. © 2013 ACM.

关键词： Electronic data interchange

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Problems in image target-based color correction 27

Problems in image target-based color correction

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IS and T International Symposium on Electronic Imaging: 27th Color Imaging: Displaying, Processing, Hardcopy, and Applications, COLOR 2022

作者： Simone, Gabriele Gaiani, Marco Ballabeni, Andrea Rizzi, Alessandro MIPS Lab - Computer Science Department University of Milan Italy Department of Architecture Alma Mater Studiorum University of Bologna Italy

This paper aims at presenting some problems that everyone could experience in the process of image target-based color correction (CC). We have acquired a set of images using a color checker, here we present some measures of these image before and after the color correction and we compare them with the actual values of the color checker. Comments about the results and their departures from the scene are reported together with the changes after color correction. It is shown how real scene acquisitions are subject to many issues that makes color correction process very far from the idealized colorimetric ideas. © 2022 Society for Imaging Science and Technology. All rights reserved.

关键词： Color

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A methodological framework for estimating ambient PM_(2.5)particulate matter concentrations in the UK

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Journal of Environmental Sciences 2025年第4期150卷 676-691页

作者： David Galán-Madruga Parya Broomandi Alfrendo Satyanaga Ali Jahanbakhshi Mehdi Bagheri Aram Fathian Rasoul Sarvestan J.Cárdenas-Escudero J.O.Cáceres Prashant Kumar Jong Ryeol Kim Department of Atmospheric Pollution National Centre for Environment HealthHealth Institute Carlos III.Ctra.Majadahonda a Pozuelo km 2.2Madrid 28220Spain Department of Civil and Environmental Engineering School of Engineering and Digital SciencesNazarbayev UniversityKabanbay Batyr Ave.53Astana 010000Kazakhstan Department of Electrical and Computer Engineering School of Engineering and Digital SciencesNazarbayev UniversityKabanbay Batyr Ave.53Astana 010000Kazakhstan School of Architecture Building and Civil EngineeringLoughborough UniversityLeicestershire LE113TUUnited Kingdom Neotectonics and Natural Hazards Institute RWTH Aachen UniversityAachen 52056Germany UNESCO Chair on Coastal Geo-Hazard Analysis Research Institute for Earth SciencesTehran 13185-1494Iran Water SedimentHazardsand Earth-surface Dynamics(waterSHED)LabDepartment of GeoscienceUniversity of CalgaryCalgary Alberta T2N 1N4Canada Department of Climatology Faculty of Geography and Environmental SciencesHakim Sabzevari UniversitySabzevar ***Iran Laser Chemistry Research Group Department of Analytical ChemistryFaculty of ChemistryComplutense University of MadridPlaza de Ciencias 1Madrid 28040Spain Analytical Chemistry Department FCNETUniversity of PanamaUniversity CityUniversity MailPanama 4Panama City 3366Panama Global Centre for Clean Air Research(GCARE) School of SustainabilityCivil and Environmental EngineeringFaculty of Engineering and Physical SciencesUniversity of SurreyGuildford GU27XHUnited Kingdom Institute for Sustainability University of SurreyGuildford GU27XHUnited Kingdom

Scientific evidence sustains PM_(2.5)particles’inhalation may generate harmful impacts on human beings’health;therefore,theirmonitoring in ambient air is of paramount relevance in terms of public *** to the limited number of fixed stations within the air qualitymonitoring networks,development ofmethodological frameworks tomodel ambient air PM_(2.5)particles is primordial to providing additional information on PM_(2.5)exposure and its *** this sense,this work aims to offer a global easily-applicable tool to estimate ambient air PM_(2.5)as a function of meteorological conditions using a multivariate *** PM_(2.5)data measured by 84 fixed monitoring stations and meteorological data from ERA5(ECMWF Reanalysis v5)reanalysis daily based data between 2000 and 2021 across the United Kingdom were attended to develop the suggested *** from January 2017 to December 2020 were employed to build amathematical expression that related the dependent variable(PM_(2.5))to predictor ones(sea-level pressure,planetary boundary layer height,temperature,precipitation,wind direction and speed),while 2021 data tested the *** indicators evidenced a good performance of model(maximum values of RMSE,MAE and MAPE:1.80μg/m^(3),3.24μg/m^(3),and 20.63%,respectively),compiling the current legislation’s requirements for modelling ambient air PM_(2.5)concentrations.A retrospective analysis of meteorological features allowed estimating ambient air PM_(2.5)concentrations from 2000 to *** highest PM_(2.5)concentrations relapsed in theMid-and Southlands,while Northlands sustained the lowest concentrations.

关键词： Air quality PM_(2.5)particles Meteorological variables Prediction model Long-term trend

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Cost-efficient soft error protection for embedded microprocessors

Cost-efficient soft error protection for embedded microproce...

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CASES 2006: International Conference on Compilers, architecture and Synthesis for Embedded Systems

作者： Blome, Jason A. Gupta, Shantanu Feng, Shuguang Mahlke, Scott Bradley, Daryl Advanced Computer Architecture Lab. University of Michigan Ann Arbor MI ARM Ltd. Cambridge United Kingdom

ISBN: (纸本)1595935436

Device scaling trends dramatically increase the susceptibility of microprocessors to soft errors. Further, mounting demand for embedded microprocessors in a wide array of safety critical applications, ranging from automobiles to pacemakers, compounds the importance of addressing the soft error problem. Historically, soft error tolerance techniques have been targeted mainly at high-end server markets, leading to solutions such as coarse-grained modular redundancy and redundant multithreading. However, these techniques tend to be prohibitively expensive to implement in the embedded design space. To address this problem, we first present a thorough analysis of the effects of soft errors on a production-grade, fully synthesized implementation of an ARM926EJ-S embedded microprocessor. We then leverage this analysis in the design of two orthogonal low-costs of terror protection techniques that can be tuned to achieve variable levels of fault coverage as a function of area and power constraints. The first technique uses a small cache of live register values in order to provide nearly twice the fault coverage of a register file protected using traditional error correcting codes at little or no additional area cost. The second technique is a statistical method used to significantly reduce the overhead of deploying time-delayed shadow latches for low-latency fault detection. Copyright 2006 ACM.

关键词： Error detection

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Scalable subgraph mapping for acyclic computation accelerators

Scalable subgraph mapping for acyclic computation accelerato...

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CASES 2006: International Conference on Compilers, architecture and Synthesis for Embedded Systems

作者： Clark, Nathan Hormati, Amir Mahlke, Scott Yehia, Sami Advanced Computer Architecture Lab. University of Michigan Ann Arbor MI ARM Ltd. Cambridge United Kingdom

ISBN: (纸本)1595935436

computer architects are constantly faced with the need to improve performance and increase the efficiency of computation in their designs. To this end, it is increasingly common to see acyclic com-putation accelerators appear in embedded processor designs. One major problem with adding accelerators to a design is that it is difficult to generate high-quality code utilizing them. Hand-written assembly code is typical, and if compiler support does exist, it is implemented using only greedy algorithms. In this work, we investigate more thorough techniques for compiling to processors with acyclic accelerators. Where as greedy solutions only explore one possible solution, the techniques presented in this paper explore the entire design space, when possible. Intelligent pruning methods are employed to ensure compilation is both tractable and scalable. Overall, our new compilation algorithms produce code that performs on average 10%, and up to 32% better than standard greedy methods. These algorithms also run in less than one second for more than 98% of basic blocks tested. Copyright 2006 ACM.

关键词： Conformal mapping

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