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Block-gram:Mining knowledgeable features for efficiently smart contract vulnerability detection

Digital Communications and Networks 2025年第1期11卷 1-12页

作者： Xueshuo Xie Haolong Wang Zhaolong Jian Yaozheng Fang Zichun Wang Tao Li Tianjin Key Laboratory of Network and Data Security Technology TianjinChina College of Computer Science Nankai UniversityTianjinChina Key Laboratory of Blockchain and Cyberspace Governance of Zhejiang Province China State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of SciencesChina

Smart contracts are widely used on the blockchain to implement complex transactions,such as decentralized applications on *** vulnerability detection of large-scale smart contracts is critical,as attacks on smart contracts often cause huge economic *** it is difficult to repair and update smart contracts,it is necessary to find the vulnerabilities before they are ***,code analysis,which requires traversal paths,and learning methods,which require many features to be trained,are too time-consuming to detect large-scale on-chain ***-based methods will obtain detection models from a feature space compared to code analysis methods such as symbol *** the existing features lack the interpretability of the detection results and training model,even worse,the large-scale feature space also affects the efficiency of *** paper focuses on improving the detection efficiency by reducing the dimension of the features,combined with expert *** this paper,a feature extraction model Block-gram is proposed to form low-dimensional knowledge-based features from ***,the metadata is separated and the runtime code is converted into a sequence of opcodes,which are divided into segments based on some instructions(jumps,etc.).Then,scalable Block-gram features,including 4-dimensional block features and 8-dimensional attribute features,are mined for the learning-based model ***,feature contributions are calculated from SHAP values to measure the relationship between our features and the results of the detection *** addition,six types of vulnerability labels are made on a dataset containing 33,885 contracts,and these knowledge-based features are evaluated using seven state-of-the-art learning algorithms,which show that the average detection latency speeds up 25×to 650×,compared with the features extracted by N-gram,and also can enhance the interpretability of the detection model.

关键词： Smart contract Bytecode&opcode Knowledgeable features Vulnerability detection Feature contribution

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Pedestrian wind flow prediction using spatial-frequency generative adversarial network

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Building Simulation 2024年第2期17卷 319-334页

作者： Pengyue Wang Maozu Guo Yingeng Cao Shimeng Hao Xiaoping Zhou Lingling Zhao School of Architecture and Urban Planning Beijing University of Civil Engineering and ArchitectureBeijing100044China Beijing Key Laboratory of Intelligent Processing for Building Big Data Beijing100044China School of Electrical and Information Engineering Beijing University of Civil Engineering and ArchitectureBeijing100044China School of Computer Science and Technology Harbin Institute of TechnologyHarbin150001China

Pedestrian wind flow is a critical factor in designing livable residential environments under growing complex urban *** pedestrian wind flow during the early design stages is essential but currently suffers from inefficiencies in numerical *** learning,particularly generative adversarial networks(GAN),has been increasingly adopted as an alternative method to provide efficient prediction of pedestrian wind ***,existing GAN-based wind flow prediction schemes have limitations due to the lack of considering the spatial and frequency characteristics of wind flow *** study proposes a novel approach termed SFGAN,which embeds spatial and frequency characteristics to enhance pedestrian wind flow *** the spatial domain,Gaussian blur is employed to decompose wind flow into components containing wind speed and distinguished flow edges,which are used as the embedded spatial *** information of wind flow is obtained through discrete wavelet transformation and used as the embedded frequency *** spatial and frequency characteristics of wind flow are jointly utilized to enforce consistency between the predicted wind flow and ground truth during the training phase,thereby leading to enhanced *** results demonstrate that SFGAN clearly improves wind flow prediction,reducing Wind_MAE,Wind_RMSE and the Fréchet Inception Distance(FID)score by 5.35%,6.52%and 12.30%,compared to the previous best method,*** also analyze the effectiveness of incorporating the spatial and frequency characteristics of wind flow in predicting pedestrian wind *** reduces errors in predicting wind flow at large error intervals and performs well in wake regions and regions surrounding *** enhanced predictions provide a better understanding of performance variability,bringing insights at the early design stage to improve pedestrian wind *** proposed spatial-frequen

关键词： pedestrian wind flow prediction generative adversarial network Gaussian kernel wavelet transform objective function

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Fault Tolerance in Stochastic Circuits for Recurrent Sequential Neural Networks 33

Fault Tolerance in Stochastic Circuits for Recurrent Sequent...

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33rd IEEE Asian Test Symposium, ATS 2024

作者： Sengupta, Roshwin Polian, Ilia Hayes, John P. University of Stuttgart Institute of Computer Architecture and Computer Engineering Stuttgart Germany University of Michigan Computer Engineering Laboratory Ann ArborMI United States

ISBN: (纸本)9798331529161

Stochastic computing (SC) provides low-area, power-efficient hardware solutions suitable for edge systems, but its scalability poses challenges due to its precision limitations, especially in noisy environments. This paper investigates the fault tolerance of key SC components, such as stochastic number generators (SNGs) and activation functions (AFs), within recurrent and sequential networks like long short-term memory (LSTM) networks. We inject bit-flip faults into a network's most sensitive inputs, weights and AFs, and study fault propagation across different network layers. Our findings reveal that SC component choices significantly influence fault tolerance. For example, networks using Sobol-based SNGs with tanh AFs exhibited stronger resilience than those with LFSR-based SNGs and ReLU AFs, by maintaining higher accuracy under fault conditions. However, the accuracy of the networks declined significantly under simultaneous faults in inputs, weights and AFs. Additionally, while increasing stochastic number lengths improved fault tolerance, they also increased latency. Nevertheless, the SC networks achieved up to 54% area and 72% power savings, making them ideal for resource-constrained applications. We also found that there is a trade-off between efficiency and fault tolerance: SC designs that focus on resource efficiency may struggle in noisy environments, where fault-tolerant SC designs are more effective. This implies that fault resilience in SC architectures depend heavily on design choices and cannot be assumed inherent across all configurations. © 2024 IEEE.

关键词： Long short-term memory

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What’s Missing in Agile Hardware Design? Verification!

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Journal of computer Science & Technology 2023年第4期38卷 735-736页

作者： Babak Falsafi Parallel Systems Architecture Laboratory Institute of Computer and Communication SciencesSchool of Computer andCommunication SciencesEcole Polytechnique Fédérale de LausanneLausanneCH-1015Switzerland

Agile hardware design is an approach to developing hardware systems that draws inspiration from the principles and practices of agile software *** emphasizes collaboration,flexibility,iterative development,and quick adaptation to changing *** agile hardware design,the focus is on delivering functionalhardware systems in shorter development cycles while maintaining high-quality and customer *** particular,agile hardware design is of great interest in the open-source hardware ***-sourcehardware development—such as RISC-V—is at the forefront of initiatives to democratize hardware and drive innovation in chip design *** design is instrumental for the RISC-V community because it supportsrapid iteration,accommodates the evolving RISC-V standard and the addition of custom extensions,improvescommunity collaboration and time-to-market,and addresses the design challenges associated with complex architectural features.

关键词： hardware agile architectural

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Large-scale Graph Neural Network Services through Computational SSD and In-Storage Processing architectures

Large-scale Graph Neural Network Services through Computatio...

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2022 IEEE Hot Chips 34 Symposium, HCS 2022

作者： Kwon, Miryeong Gouk, Donghyun Lee, Sangwon Jung, Myoungsoo Computer Architecture and Memory Systems Laboratory

Demonstration Video Link: https://***/watch?v=b5fZBESH1TM

ISBN: (数字)9781665460286

ISBN: (纸本)9781665460286

Demonstration Video Link: https://***/watch?v=b5fZBESH1TM

关键词： computer architecture Inference algorithms Graph neural networks Energy efficiency

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Joint User Association,Resource Allocation and Trajectory Design for Multi-UAV-Aided NOMA Wireless Communication Systems

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China Communications 2025年第3期22卷 217-233页

作者： Yin Sixing Qu Zhaowei Yu Peng Beijing Key Laboratory of Network System Architecture and Convergence Beijing University of Posts and TelecommunicationsBeijing 100876China School of Computer Science Beijing University of Posts and TelecommunicationsBeijing 100876China

In this paper,we investigate a multi-UAV aided NOMA communication system,where multiple UAV-mounted aerial base stations are employed to serve ground users in the downlink NOMA communication,and each UAV serves its associated users on its own *** aim at maximizing the overall common throughput in a finite time *** a problem is a typical mixed integer nonlinear problem,which involves both continuous-variable and combinatorial *** efficiently solve this problem,we propose a two-layer algorithm,which separately tackles continuous-variable and combinatorial ***,in the inner layer given one user association scheme,subproblems of bandwidth allocation,power allocation and trajectory design are solved based on alternating *** the outer layer,a small number of candidate user association schemes are generated from an initial scheme and the best solution can be determined by comparing all the candidate *** particular,a clustering algorithm based on K-means is applied to produce all candidate user association schemes,the successive convex optimization technique is adopted in the power allocation subproblem and a logistic function approximation approach is employed in the trajectory design *** results show that the proposed NOMA scheme outperforms three baseline schemes in downlink common throughput,including one solution proposed in an existing literature.

关键词： NOMA resource allocation trajectory design UAV communications user association

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A study on the impact of heritage protection on urban carbon emissions

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Science China(Technological Sciences) 2024年第9期67卷 2675-2692页

作者： WANG Fang XUE PengCheng WANG ShunYi LIU YunHuai River Basin Habitats Research Center College of Architecture and Landscape ArchitecturePeking UniversityBeijing 100871China Shanxi Key Laboratory of Watershed Built Environment with Locality(Peking University) Peking UniversityBeijing 100871China College of Urban and Environmental Sciences Peking UniversityBeijing 100871China School of Computer Science Peking UniversityBeijing 100871China

A major goal of current international urban development and construction is to lower carbon *** exist between the preservation of historic cities and the development of low-carbon cities;however,the relationship between preservation of historic cities and carbon emissions remains *** study focuses on the cities in the“Yellow-Canal-Yangtze”watershed community,which includes the Yellow River Basin,Yangtze River Basin,and the Grand Canal region,and aims to verify the differences in CO_(2) emissions(CE)between historic and non-historic cities through multiple comparisons after ***,Ridge Regression was used to determine the impact and dimensions of the relevant variables associated with the preservation of historic cities on *** with national development goals,this study predicts changes in the CE of historic city preservation under different *** study found significant differences between historic and non-historic cities,as the total CE of historic cities is 2.42 times higher than that of non-historic *** dimension with the largest difference was the CE related to transportation,with aviation emissions of historic cities reaching 15.22 times higher than that of non-historic *** the preservation of historic cities has led to an overall increase in the CE,there is significant potential for CE reduction in land use,transportation infrastructure,and tourism development related to historic city *** the future,historic cities can contribute to China's carbon neutrality and the United Nation's development goals through the creation of larger historical preservation areas,more convenient public transportation,and more vibrant tourism.

关键词： CO_(2) emissions urban planning cultural heritage historic city “Yellow-Canal-Yangtze”watershed community

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BTBench: A Benchmark for Comprehensive Binary Translation Performance Evaluation

BTBench: A Benchmark for Comprehensive Binary Translation Pe...

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2024 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2024

作者： Li, Xinyu Lan, Yanzhi Niu, Gen Xue, Feng Zhang, Fuxin Institute of Computing Technology Chinese Academy of Sciences University of Chinese Academy of Sciences State Key Laboratory of Computer Architecture China

ISBN: (纸本)9798350376388

Binary translation serves as a fundamental technol-ogy for instruction set emulation, system virtualization, runtime instrumentation, and numerous other applications. Many techniques have been proposed to enhance the efficiency of binary translation systems. However, imprecise performance evaluation leads to potential performance shortcomings of binary translators in real-world applications. Previous studies primarily employ CPU benchmarks, which may overlook performance issues spe-cific to binary translators and fail to guide for optimizing binary translation. To address this issue, we propose a new benchmark suite named BTBench(Binary Translation Benchmark), which provides a convenient, portable, and comprehensive solution. BT-Bench takes into account the inherent attributes of binary trans-lators, such as translation and code-cache lookup overhead. We carefully select benchmarks that offer comprehensive coverage and align with real-world application scenarios. To validate the effectiveness of BTBench, we conducted rigorous experimentation on four widely-used binary translators. The analysis of the results reveals that, compared to existing CPU benchmarks, BTBench is better suited for identifying potential performance shortcomings, providing invaluable insights for future optimization efforts. The BTBench benchmark suite is publicly available 1 • © 2024 IEEE.

关键词： Benchmarking

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eCC++ : A Compiler Construction Framework for Embedded Domain-Specific Languages

eCC++ : A Compiler Construction Framework for Embedded Domai...

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2024 IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2024

作者： Tallada, Marc Gonzalez Denny, Joel Valero-Lara, Pedro Lee, Seyong Teranishi, Keita Vetter, Jeffrey S. UPC BarcelonaTech Dept. Computer Architecture United States Oak Ridge National Laboratory Oak Ridge United States

ISBN: (纸本)9798350364606

eCC++ is a new compiler construction framework for embedding domain-specific programming languages within C++. That is, the host language is C++, the guest language is the DSL to be embedded in C++, and eCC++ is the tool that enables the embedding. The eCC++ framework is composed of three main components: a front-end, an API for program verification based on a functional and declarative intermediate representation (IR), and a Multi-Level Intermediate Representation (MLIR) code generator. The eCC++ front-end consists of a library of C++ classes and operators that can be used to define the guest language. Guest sources are compiled with any standard C++ compiler, and when run, the resulting executable generates an eCC++ IR representation of the program, which can be verified within the eCC++ framework. Finally, eCC++ allows for high-level and domain-specific optimizations before generating MLIR. In summary, eCC++ aims to act as a generic front-end that enables embedding guest languages into C++, and provides necessary compiler technology for program verification, targeting the existing capabilities in the MLIR infrastructure. The paper evaluates the eCC++ expressiveness and usability describing the process of embedding GraphIt, a high-performance graph language in C++. © 2024 IEEE.

关键词： Embeddings

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Improving DNN Accuracy on MLC PIM via Black-box Fine-tuning

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IEEE Transactions on computer-Aided Design of Integrated Circuits and Systems 2024年第6期44卷 2277-2286页

作者： Lv, Hao Zhang, Lei Wang, Ying Institute of Computing Technology Chinese Academy of Sciences University of Chinese Academy of Sciences Beijing100089 China The State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing100089 China

Resistive random access memory (RRAM) emerges as a promising technology for developing energy-efficient deep neural network (DNN) accelerators, owing to its analog computing paradigm for matrix-vector multiplication. However, the inherent non-ideal device features of RRAM cells, such as device variation, read disturbances, and limited on/off ratio, present challenges for model deployment. Therefore, to ensure accurate storage and computing precision for RRAM-based accelerators, a widely used practice is encoding a DNN weight by multiple cells, resulting in significant memory overhead and underutilization. This challenge is further exacerbated by the rapid increases in model size witnessed in recent years. While the one-to-one weight-cell mapping strategy can improve memory utilization, it inevitably introduces deviations in the mapped DNN weight from the desired value due to RRAM variation issues, leading to model accuracy degradation. In response to this challenge, we abstract the model optimization on RRAM chips as a black-box optimization problem, aimed at optimizing model accuracy without the requirement of precise weight programming. We systematically analyze the model optimization behavior on multi-level RRAM devices by investigating the accuracy recovery process of various fine-tuning strategies in recovering model performance under the black-box setting. Based on the analysis, we propose a black-box finetune scheme to recover the model performance for multilevel RRAM under the black-box setting. Our proposed scheme leverages knowledge distillation and exploits input/output information of the model on RRAM to guide the fine-tuning process, finally restoring its accuracy. Experimental results demonstrate the efficacy of our black-box fine-tuning scheme, achieving nearly complete recovery of model performance. Our approach yields over a 3% improvement in model accuracy compared to variation-aware training approaches. © 1982-2012 IEEE.

关键词： Energy efficiency

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