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IEEE International Test Conference

作者： S. Hamdioui A.J. Van De Goor Intel Corporation Santa Clara CA USA Section Computer Architecture & Digital Technique Department of Electrical Engineering Faculty of Information Technology and Systems Delft University of Technnology Delft Netherlands

A two-port memory contains two similar ports, which can be accessed separately and independent of each other. In this paper, logical fault models are derived for the effect of shorts between the ports. The result is a... 详细信息

关键词： Interference Circuit faults Circuit testing Built-in self-test Educational institutions computer architecture Information technology Electronic mail Circuit simulation

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Industrial evaluation of DRAM tests

Industrial evaluation of DRAM tests

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Design, Automation and Test in Europe Conference and Exhibition

作者： A.J. van de Goer J. de Neef Dept. of Electr. Eng. Delft Univ. of Technol. Netherlands Faculty of Information Technology and Systems Department of Electrical Engineering Section Computer Architecture and Digital Technique Delft University of Technnology Delft Netherlands

This paper presents the results of 44 well known memory tests applied to 1896 1M*4 DRAM chips, using up to 96 different stress combinations with each test. The results show the importance of selecting the right stress combination, and that the theoretically better tests (i.e. those covering different functional faults) also have a higher fault coverage. However the currently used fault models still leave much to be explained; e.g., the used data backgrounds and address orders show an unexplainable large variation in fault coverage.

关键词： Random access memory Testing Stress Leakage current Indium phosphide Information technology computer architecture Postal services Hip Electronic switching systems

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Converting March tests for bit-oriented memories into tests for word-oriented memories

Converting March tests for bit-oriented memories into tests ...

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IEEE International Workshop on Memory Technology, Design and Testing

作者： A.J. Van De Goor I.B.S. Tlili S. Hamdioui Section of Computer Architecture and Digital Technology Delft University of Technnology Delft Netherlands

In this paper a set of fault models for coupling faults between the cells of a word has been established, together with tests for these fault models. Thereafter, a systematic way of converting tests for bit-oriented memories into tests for word-oriented memories is presented, distinguishing between inter-word and intra-word faults. This results in more efficient tests with complete coverage of the targeted faults. Because most memories have an external data path which is wider than one bit, word-oriented memory tests are very important.

关键词： System testing Satellite broadcasting Logic arrays Fault detection Information technology computer architecture Decoding Bills of materials

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March tests for word-oriented memories 98

March tests for word-oriented memories

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Design, Automation and Test in Europe Conference and Exhibition

作者： A.J. van de Goor I.B.S. Tlili Faculty of Information Technology and Systems Section Computer Architecture & Digital Technique Delft University of Technnology Delft Netherlands

ISBN: (纸本)9780818683596

Most memory test algorithms are optimized tests for a particular memory technology, and a particular set of fault models, under the assumption that the memory is bit-oriented; i.e., read and write operations affect only a single bit in the memory. Traditionally, word-oriented memories have been tested by repeated application of a test for bit-oriented memories whereby a different data background (which depends on the used intra-word fault model) is used during each iteration. This results in rime inefficiencies and limited fault coverage. A new approach for testing word-oriented memories is presented, distinguishing between inter-word and intra-word faults and allowing for a systematic way of converting tests for bit-oriented memories to rests for word-oriented memories. The conversion consists of concatenating the bit-oriented test for inter-word faults with a test for intra-word faults. This approach results in more efficient tests with complete coverage of the targeted faults. Because most memories have an external data path which is wider than one bit, word-oriented memory tests are very important.

关键词： System testing Satellite broadcasting Information technology computer architecture Electronic mail Electrical capacitance tomography Fault detection Legged locomotion Bills of materials

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Consequences of port restrictions on testing address decoder faults in two-port memories

Consequences of port restrictions on testing address decoder...

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Asian Test Symposium (ATS)

作者： S. Hamdioui A.J. van de Goor Faculty of Information Technology and Systems Department of Electrical Engineering Section of Computer Architecture & Digital Technique Delft University of Technnology Delft Netherlands

Testing two-port memories requires the use of single-port tests as well as special two-port tests; the test strategy determines which tests have to be used. Many two-port memories have ports which are read-only or write-only; this impacts the possible tests for single-port and two-port memories, as well as the test strategy. This paper discusses the consequences of the port restrictions (read-only or write-only ports) on the tests; in addition it covers the test strategy for address decoder faults in two-port memories.

关键词： Decoding System testing Read-write memory computer architecture Electronic mail Performance evaluation Random access memory Interference

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Consequences of port restrictions on testing two-port memories

Consequences of port restrictions on testing two-port memori...

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IEEE International Test Conference

作者： S. Hamdioui A.J. van de Goor Faculty of Information Technology and Systems Department o Electrical Engineering Section Computer Architecture & Digital Technique Delft University of Technnology Delft Netherlands

Testing two-port memories requires the use of single-port tests as well as special two-port tests; the test strategy determines which tests to be used. Many two-port memories have ports which are read-only or write-only; this impacts the possible fault models, the tests for single-port and two-port memories, as well as the test strategy. This paper presents a test strategy for two-port memories and covers the consequences of the port restrictions (read-only or write-only ports).

关键词： Testing Logic arrays Random access memory Read-write memory Frequency conversion Logic devices Low voltage Conductivity Resource description framework

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Address decoder faults and their tests for two-port memories

Address decoder faults and their tests for two-port memories

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IEEE International Workshop on Memory Technology, Design and Testing

作者： S. Hamdioui A.J. Van De Goer Faculty of Information Technology and Systems Section of Computer Architecture and Digital Technology Delft University of Technnology Delft Netherlands Technische Universiteit Delft Delft Zuid-Holland NL

A two-port memory contains two duplicated sets of address decoders which operate independently. In this paper the effects of interference and shorts between the address decoders of the two ports on the fault modeling ... 详细信息

关键词： Decoding Circuit faults Electronic switching systems Interference Electrical capacitance tomography Information technology computer architecture Built-in self-test Circuit testing Read-write memory

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March U: A test for unlinked memory faults

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IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS 1997年第3期144卷 155-160页

作者： vandeGoor, AJ Gaydadjiev, GN Department of Electrical Engineering Section Computer Architecture & Digital Technique Delft University of Technology Mekelweg 4 Delft 2628 CD The Netherlands

Short and efficient memory tests is the goal of every test designer. To reduce the cost of production tests, often a simple test which covers most of the faults, e.g. all simple (unlinked) faults, is desirable to eliminate most defective parts;a more costly test can be used thereafter to eliminate the remainder of the bad parts. Such a test-cost efficient approach is used by most manufacturers. In addition, system power-on tests are not allowed a long test time while a high fault coverage is desirable. The authors propose a new realistic fault model (the disturb fault model), and a set of tests for unlinked faults. These tests have the property of covering all simple (unlinked) faults at a very reasonable test time compared with existing tests.

关键词： memory tests March tests memory faults fault model simple faults disturb fault

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An analysis of (linked) address decoder faults

An analysis of (linked) address decoder faults

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IEEE International Workshop on Memory Technology, Design and Testing

作者： A.J. van de Goor G.N. Gaydadjiev Department of Electrical Engineering Section Computer Architecture & Digital Technique Delft University of Technnology Delft Netherlands

The complexity of memory tests arises when linked faults are taken into consideration. Usually only the class of linked faults in the memory cell array have been taken into consideration, while the class of linked faults involving address decoder faults has been ignored. This paper gives an overview of the most important and commonly used fault models including the disturb fault model. It derives a set of conditions march tests have to satisfy in order to detect address decoder faults (AFs) when they are not linked; these conditions are shown to be dependent on the memory technology (SRAM and DRAM). Next, a set of conditions for march tests are derived to detect linked AFs (linked with other AFs or linked with faults in the memory cell array). The paper concludes with the analysis of a set of well-known march tests for the fault coverage of unlinked and linked AFs. Many of the widely used tests are shown not to be able to detect all (linked) AFs.

关键词： Decoding Testing Fault detection computer architecture Electronic mail Random access memory Shipbuilding industry Marine vehicles Joining processes

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An open notation for memory tests

An open notation for memory tests

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IEEE International Workshop on Memory Technology, Design and Testing

作者： A. Offerman A.J. van de Goor Section Computer Architecture & Digital Technique Department of Electrical Engineering Delft University of Technnology Delft Netherlands

Historically many ways of expressing memory tests have been used, varying from the use of general purpose programming languages to special notations. A notation, originally introduced for march tests in 1990, has been adopted and extended by many researchers. This paper extends that notation, in a systematic and open way, to a memory test language which allows march tests, pseudo march tests, tests involving topological neighborhoods (to cover pattern sensitive faults), line mode tests, and pseudo random tests, to be expressed in a unified manner. The syntax and semantics facilitate the specification of memory tests in a compact and readable way. Most important, the open structure allows extensions to the notation when necessary. The notation presented in this paper is a sequel to an earlier much more confined notation.

关键词： System testing Semiconductor device testing computer architecture Semiconductor memory Fault detection Legged locomotion computer languages Operational amplifiers

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