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European Control Conference (ECC)

作者： Gehui Xu Guanpu Chen Yiguang Hong Baris Fidan Thomas Parisini Karl H. Johansson Key Laboratory of Systems and Control Academy of Mathematics and Systems Science Beijing China Division of Decision and Control Systems School of Electrical Engineering and Computer Science KTH Royal Institute of Technology Stockholm Sweden Department of Control Science and Engineering Tongji University Shanghai China Shanghai Research Institute for Intelligent Autonomous Systems Shanghai China Department of Mechanical and Mechatronics Engineering University of Waterloo Waterloo ON Canada Department of Electrical and Electronic Engineering Imperial College London London UK Department of Engineering and Architecture University of Trieste Trieste Italy

ISBN: (数字)9783907144107

ISBN: (纸本)9798331540920

Sensor network localization (SNL) problems require determining the physical coordinates of all sensors in a network. This process relies on the global coordinates of anchors and the available measurements between non-anchor and anchor nodes. Attributed to the intrinsic non-convexity, obtaining a globally optimal solution to SNL is challenging, as well as implementing corresponding algorithms. In this paper, we formulate a non-convex multi-player potential game for a generic SNL problem to investigate the identification condition of the global Nash equilibrium (NE) therein, where the global NE represents the global solution of SNL. We employ canonical duality theory to transform the non-convex game into a complementary dual problem. Then we develop a conjugation-based algorithm to compute the stationary points of the complementary dual problem. On this basis, we show an identification condition of the global NE: the stationary point of the proposed algorithm satisfies a duality relation. Finally, simulation results are provided to validate the effectiveness of the theoretical results.

关键词： Location awareness Coordinate measuring machines Simulation Current measurement Noise Europe Games

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Multi-Unit Floor Plan Recognition and Reconstruction Using Improved Semantic Segmentation of Raster-Wise Floor Plans

arXiv

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arXiv 2024年

作者： Kratochvila, Lukas de Jong, Gijs Arkesteijn, Monique Bilík, Šimon Zemčík, Tomáš Horak, Karel Rellermeyer, Jan S. Department of Control and Instrumentation Faculty of Electrical Engineering and Communication Brno University of Technology Brno Czech Republic Department of Software Technology Faculty of Electrical Engineering Mathematics and Computer Science TU Delft Delft Netherlands Department of Management in the Built Environment Faculty of Architecture and the Built Environment TU Delft Delft Netherlands Computer Vision and Pattern Recognition Laboratory Department of Computational Engineering Lappeenranta-Lahti University of Technology LUT Lappeenranta Finland Dependable and Scalable Software Systems Institute of Systems Engineering Faculty of Electrical Engineering and Computer Science Leibniz University Hannover Hannover Germany

Digital twins have a major potential to form a significant part of urban management in emergency planning, as they allow more efficient designing of the escape routes, better orientation in exceptional situations, and faster rescue intervention. Nevertheless, creating the twins still remains a largely manual effort, due to a lack of 3D-representations, which are available only in limited amounts for some new buildings. Thus, in this paper we aim to synthesize 3D information from commonly available 2D architectural floor plans. We propose two novel pixel-wise segmentation methods based on the MDA-Unet and MACU-Net architectures with improved skip connections, an attention mechanism, and a training objective together with a reconstruction part of the pipeline, which vectorizes the segmented plans to create a 3D model. The proposed methods are compared with two other state-of-the-art techniques and several benchmark datasets. On the commonly used CubiCasa benchmark dataset, our methods have achieved the mean F1 score of 0.86 over five examined classes, outperforming the other pixel-wise approaches tested. We have also made our code publicly available to support research in the field. © 2024, CC BY.

关键词： Semantic Segmentation

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Optimal Power Control Based-Metaheuristic Algorithm Based Variable Speed Wind Energy System of DFIG

Optimal Power Control Based-Metaheuristic Algorithm Based Va...

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International Smart Grid Workshop and Certificate Program (ISGWCP)

作者： Boussaid Ibrahim Harrouz Abdelkader Merahi Farid Ibrahim Yaichi Ilhami Colak Korhan Kayisli Virgil Dumbrava Electrical Engineering Department Laboratory of sustainable development and computer science (LDDI) University of Adrar Adrar Algeria Laboratory of sustainable development and computer science (LDDI) University of Adrar Adrar Algeria Electrical Engineering Department Automatic Laboratory of Setif University of Ferhat Abbas Setif1 Setif Algeria Department of Electrical Electronics Eng. Faculty of Engineering Architecture Nisantasi University Istanbul Turkey Department of Electric Power Systems Polytechnic University of Bucharest Bucharest Romania

This article presents a novel method for controlling a doubly fed induction generator (DFIG) wind energy system in the presence of variable wind speeds. In order to achieve decoupling control of the active and reactive power, the rotor-side converter (RSC) of the DFIG is controlled using field-oriented control (FOC). The system is very complicated and nonlinear, making it challenging to adjust the PI gains appropriately. The present research proposes the utilization of the Grey Wolf Optimization (GWO) algorithm as an approach to optimize the gains of a Proportional-Integral (PI) regulator. The simulation results demonstrate that the GWO-PI provides a lower criterion value and an improved response than the conventional PI.

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DC-store: eliminating noisy neighbor containers using deterministic I/O performance and resource isolation 20

DC-store: eliminating noisy neighbor containers using determ...

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Proceedings of the 18th USENIX Conference on File and Storage Technologies

作者： Miryeong Kwon Donghyun Gouk Changrim Lee Byounggeun Kim Jooyoung Hwang Myoungsoo Jung Computer Architecture and Memory Systems Laboratory Korea Advanced Institute of Science and Technology Computer Architecture and Memory Systems Laboratory Samsung

ISBN: (纸本)9781939133120

We propose DC-store, a storage framework that offers deterministic I/O performance for a multi-container execution environment. DC-store's hardware-level design implements multiple NVM sets on a shared storage pool, each providing a deterministic SSD access time by removing internal resource conflicts. In parallel, software support of DC-Store is aware of the NVM sets and enlightens Linux kernel to isolate noisy neighbor containers, performing page frame reclaiming, from peers. We prototype both hardware and software counterparts of DC-Store and evaluate them in a real system. The evaluation results demonstrate that containerized data-intensive applications on DC-Store exhibit 31% shorter average execution time, on average, compared to those on a baseline system.

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A differential public PUF design for lightweight authentication 16

A differential public PUF design for lightweight authenticat...

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2021 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2021 and 16th Conference on PhD Research in Microelectronics and Electronics, PRIME 2021

作者： Duan, Shengyu Sai, Gaole School of Computer Engineering and Science Shanghai University Shanghai200444 China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China Guangdong Provincial Key Lab of Robotics and Intelligent System Shenzhen Institutes of Advanced Technology Chinese Academy of Sciences China CAS Key Laboratory of Human-Machine Intelligence-Synergy Systems Shenzhen Institutes of Advanced Technology China

ISBN: (纸本)9783800755899

Physical Unclonable Functions (PUFs) have emerged as a promising primitive to provide a hardware keyless security mechanism for integrated circuit applications. Public PUFs (PPUFs) address the crucial PUF vulnerability of requiring databases to store the secrete reference information. This paper investigates one of the PPUF families, differential PPUF (dPPUF), which exploits complexly interacted logic to create time gap between actual execution and simulation, and to prevent simulation attacks. Conventional dPPUFs have high costs. We observe the repressers have large impact on simulation time, but take a great proportion in current dPPUF structure. We thereby present a represser network with specially designed interconnection and shared logic, to maintain a high circuit complexity and to reduce the area cost. We show the proposed dPPUF has similar resilience over simulation attacks as the conventional design. Area cost can be reduced by up to 44%, and thus the proposed design can be used for lightweight authentication. © VDE VERLAG GMBH.

关键词： Authentication

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PROV-IO+: A Cross-Platform Provenance Framework for Scientific Data on HPC systems

arXiv

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arXiv 2023年

作者： Han, Runzhou Zheng, Mai Byna, Suren Tang, Houjun Dong, Bin Dai, Dong Chen, Yong Kim, Dongkyun Hassoun, Joseph Thorsley, David Wolf, Matthew Department of Electrical and Computer Engineering Iowa State University United States Department of Computer Science and Engineering The Ohio State University United States Scientific Data Management Group Lawrence Berkeley National Laboratory United States Computer Science Department University of North Carolina Charlotte United States Systems Architecture Lab Samsung United States Samsung Advanced Institute of Technology Samsung Korea Republic of

Data provenance, or data lineage, describes the life cycle of data. In scientific workflows on HPC systems, scientists often seek diverse provenance (e.g., origins of data products, usage patterns of datasets). Unfortunately, existing provenance solutions cannot address the challenges due to their incompatible provenance models and/or system implementations. In this paper, we analyze four representative scientific workflows in collaboration with the domain scientists to identify concrete provenance needs. Based on the first-hand analysis, we propose a provenance framework called PROV-IO+, which includes an I/O-centric provenance model for describing scientific data and the associated I/O operations and environments precisely. Moreover, we build a prototype of PROV-IO+ to enable end-to-end provenance support on real HPC systems with little manual effort. The PROV-IO+ framework can support both containerized and non-containerized workflows on different HPC platforms with flexibility in selecting various classes of provenance. Our experiments with realistic workflows show that PROV-IO+ can address the provenance needs of the domain scientists effectively with reasonable performance (e.g., less than 3.5% tracking overhead for most experiments). Moreover, PROV-IO+ outperforms a state-of-the-art system (i.e., ProvLake) in our experiments. © 2023, CC BY-NC-SA.

关键词： Life cycle

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An Auto-Parallel Method for Deep Learning Models Based on Genetic Algorithm

An Auto-Parallel Method for Deep Learning Models Based on Ge...

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International Conference on Parallel and Distributed systems (ICPADS)

作者： Yan Zeng ChengChuang Huang YiJie Ni ChunBao Zhou JiLin Zhang Jue Wang MingYao Zhou MeiTing Xue YunQuan Zhang School of Computer Science and Technology Hangzhou Dianzi University Hangzhou China Key Laboratory for Modeling and Simulation of Complex Systems Ministry of Education Hangzhou China Data Security Governance Zhejiang Engineering Research Center Hangzhou China School of ITMO Joint Institute Hangzhou Dianzi University Hangzhou China Institute of Computer Network Information Center of the Chinese Academy of Sciences Beijing China HuaWei State Key Laboratory of Computer Architecture Institute of Computing Technology of the Chinese Academy of Sciences Beijing China

As the size of datasets and neural network models increases, automatic parallelization methods for models have become a research hotspot in recent years. The existing auto-parallel methods based on machine learning or graph algorithms still have issues with search efficiency and applicability. This paper proposes an automatic parallel method based on a dual-population genetic algorithm, TGA, which transforms model partitioning and placement into an integer linear programming problem and constructs a cost model to evaluate the solution. The solution space is built using the neural network’s dataflow graph and device cluster’s topology, and the dual-population genetic algorithm is used to search for the optimal model parallel strategy. Experiments with various models show that the proposed method can improve single-step execution time by up to 42% compared to the Baechi method and up to 37.7% compared to the Hierarchical method.

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A Multi-Player Potential Game Approach for Sensor Network Localization with Noisy Measurements

A Multi-Player Potential Game Approach for Sensor Network Lo...

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IEEE Conference on Decision and Control

作者： Gehui Xu Guanpu Chen Baris Fidan Yiguang Hong Hongsheng Qi Thomas Parisini Karl H. Johansson Department of Electrical and Electronic Engineering Imperial College London London UK Division of Decision and Control Systems School of Electrical Engineering and Computer Science KTH Royal Institute of Technology Stockholm Sweden Department of Mechanical and Mechatronics Engineering University of Waterloo Waterloo ON Canada Department of Control Science and Engineering Tongji University shanghai China Shanghai Research Institute for Intelligent Autonomous Systems Shanghai China Key Laboratory of Systems and Control Academy of Mathematics and Systems Science Beijing China School of Mathematical Sciences University of Chinese Academy of Sciences Beijing China Department of Electronic Systems Aalborg University Denmark Department of Engineering and Architecture University of Trieste Italy

ISBN: (数字)9798350316339

ISBN: (纸本)9798350316346

Sensor network localization (SNL) is a challenging problem due to its inherent non-convexity and the effects of noise in inter-node ranging measurements and anchor node position. We formulate a non-convex SNL problem as a multiplayer non-convex potential game and investigate the existence and uniqueness of a Nash equilibrium (NE) in both the ideal setting without measurement noise and the practical setting with measurement noise. We first show that the NE exists and is unique in the noiseless case, and corresponds to the precise network localization. Then, we study the SNL for the case with errors affecting the anchor node position and the inter-node distance measurements. Specifically, we establish that in case these errors are sufficiently small, the NE exists and is unique. It is shown that the NE is an approximate solution to the SNL problem, and that the position errors can be quantified accordingly. Based on these findings, we apply the results to case studies involving only inter-node distance measurement errors and only anchor position information inaccuracies.

关键词： Location awareness Noise Games Position measurement Nash equilibrium Distance measurement Noise measurement

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Scalable parallel flash firmware for many-core architectures 20

Scalable parallel flash firmware for many-core architectures

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Proceedings of the 18th USENIX Conference on File and Storage Technologies

作者： Jie Zhang Miryeong Kwon Michael Swift Myoungsoo Jung Computer Architecture and Memory Systems Laboratory Korea Advanced Institute of Science and Technology Computer Architecture and Memory Systems Laboratory University of Wisconsin at Madison

ISBN: (纸本)9781939133120

NVMe is designed to unshackle flash from a traditional storage bus by allowing hosts to employ many threads to achieve higher bandwidth. While NVMe enables users to fully exploit all levels of parallelism offered by modern SSDs, current firmware designs are not scalable and have difficulty in handling a large number of I/O requests in parallel due to its limited computation power and many hardware *** propose DeepFlash, a novel manycore-based storage platform that can process more than a million I/O requests in a second (1MIOPS) while hiding long latencies imposed by its internal flash media. Inspired by a parallel data analysis system, we design the firmware based on many-to-many threading model that can be scaled horizontally. The proposed DeepFlash can extract the maximum performance of the underlying flash memory complex by concurrently executing multiple firmware components across many cores within the device. To show its extreme parallel scalability, we implement DeepFlash on a many-core prototype processor that employs dozens of lightweight cores, analyze new challenges from parallel I/O processing and address the challenges by applying concurrency-aware optimizations. Our comprehensive evaluation reveals that DeepFlash can serve around 4.5 GB/s, while minimizing the CPU demand on microbenchmarks and real server workloads.

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DRAM-Less: Hardware Acceleration of Data Processing with New Memory

DRAM-Less: Hardware Acceleration of Data Processing with New...

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IEEE Symposium on High-Performance computer architecture

作者： Jie Zhang Gyuyoung Park David Donofrio John Shalf Myoungsoo Jung Computer Architecture and Memory Systems Laboratory Korea Advanced Institute of Science and Technology (KAIST) Computer Architecture and Memory Systems Laboratory Lawrence Berkeley National Laboratory

ISBN: (数字)9781728161495

ISBN: (纸本)9781728161501

General purpose hardware accelerators have become major data processing resources in many computing domains. However, the processing capability of hardware accelerations is often limited by costly software interventions and memory copies to support compulsory data movement between different processors and solid-state drives (SSDs). This in turn also wastes a significant amount of energy in modern accelerated systems. In this work, we propose, DRAM-less, a hardware automation approach that precisely integrates many state-of-the-art phase change memory (PRAM) modules into its data processing network to dramatically reduce unnecessary data copies with a minimum of software modifications. We implement a new memory controller that plugs a real 3x nm multi-partition PRAM to 28nm technology FPGA logic cells and interoperate its design into a real PCIe accelerator emulation platform. The evaluation results reveal that our DRAM-less achieves, on average, 47% better performance than advanced acceleration approaches that use a peer-to-peer DMA.

关键词： Phase change random access memory Data processing Hardware Acceleration Kernel Buffer storage

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