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6th IEEE International Conference on Power, Intelligent Computing and Systems, ICPICS 2024

作者： Mou, Chenglin Wu, Kaiqi Du, Pengcheng Yang, Kaibo School of Civil Engineering and Architecture Henan University of Science and Technology Department of Engineering Mechanics Luoyang471099 China School of Information Engineering Henan University of Science and Technology Department of Computer Science and Technology Luoyang471099 China School of Information Engineering Henan University of Science and Technology Department of Automation Luoyang471099 China School of International Education Henan University of Science and Technology Department of Civil Engineering Luoyang471099 China

ISBN: (纸本)9798350374315

Tower solar thermal power generation is a new type of low-carbon and environmentally friendly clean energy technology. In this paper, a single-objective optimization model is established with the maximum annual average thermal output per unit mirror area of the heliostat field as the objective function. By optimizing the heliostat width, heliostat height and heliostat coordinate, the annual average output thermal power can be maximized while meeting the rated power. The heliostat field is distributed in a circular shape. As the seasons change, the light intensity received by the heliostat field is uneven, so the optical efficiency of the heliostats is also different. We simplify the heliostat field into S area (area with higher optical efficiency) and W area (area with lower optical efficiency) based on the optical efficiency distribution of heliostats. At different locations, According to the heliostat width, heliostat height and heliostat coordinate generated by random functions, substituting these parameters into the efficiency model in this paper, and the random search algorithm is used to traverse the maximum annual output thermal power and the corresponding heliostat parameters. In the shadow occlusion loss model, we have grid to set up the heliostat and use the coordinate conversion to solve the shadow occlusion loss efficiency. © 2024 IEEE.

关键词： Heliostats (instruments)

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Quasi-Z-Source Cascaded H-Bridge Multilevel Inverters for PV Applications with Fault

Quasi-Z-Source Cascaded H-Bridge Multilevel Inverters for PV...

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International Conference on Environment and Electrical Engineering (EEEIC)

作者： David Carrasco-González Pablo Horrillo-Quintero Pablo García-Triviño Raúl Sarrias-Mena Carlos Andrés García-Vázquez Luis M. Fernández-Ramirez Department of Electrical Engineering SURET Research Group University of Cadiz Algeciras Spain Department of Engineering in Automation Electronics and Computer Architecture and Networks SURET Research Group University of Cadiz Algeciras Spain

Nowadays, the use of quasi-Z-source cascaded H-bridge multilevel inverters (qZS-CHBMLI) in photovoltaic (PV) has gained their attention. They permit the single-stage power transformation of a PV generator adjusting the DC voltage independently in each module to operate each PV generator at maximum power. This paper develops a new control strategy that allows the system to continue operating after a fault in a module, by increasing the DC voltage in the operating modules. The control strategy is employed to a grid-connected qZS-CHBMLI, which consists of three cascaded qZSI powered by independent 4.8 kW PV cells. Under several operating circumstances, the proposed control system is evaluated. The results demonstrate how the control strategy applied to the system successfully reacts to the failure of a module.

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A parallel evolutionary algorithm to optimize dynamic memory managers in embedded systems

arXiv

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arXiv 2024年

作者： Risco-Martín, José L. Atienza, David Colmenar, J. Manuel Garnica, Oscar Department of Computer Architecture and Automation Universidad Complutense de Madrid Madrid28040 Spain Lausanne1015 Switzerland C. E. S. Felipe II Universidad Complutense de Madrid Aranjuez28300 Spain

For the last thirty years, several Dynamic Memory Managers (DMMs) have been proposed. Such DMMs include first fit, best fit, segregated fit and buddy systems. Since the performance, memory usage and energy consumption of each DMM differs, software engineers often face difficult choices in selecting the most suitable approach for their applications. This issue has special impact in the field of portable consumer embedded systems, that must execute a limited amount of multimedia applications (e.g., 3D games, video players and signal processing software, etc.), demanding high performance and extensive memory usage at a low energy consumption. Recently, we have developed a novel methodology based on genetic programming to automatically design custom DMMs, optimizing performance, memory usage and energy consumption. However, although this process is automatic and faster than state-of-the-art optimizations, it demands intensive computation, resulting in a time consuming process. Thus, parallel processing can be very useful to enable to explore more solutions spending the same time, as well as to implement new algorithms. In this paper we present a novel parallel evolutionary algorithm for DMMs optimization in embedded systems, based on the Discrete Event Specification (DEVS) formalism over a Service Oriented architecture (SOA) framework. Parallelism significantly improves the performance of the sequential exploration algorithm. On the one hand, when the number of generations are the same in both approaches, our parallel optimization framework is able to reach a speed-up of 86.40× when compared with other state-of-the-art approaches. On the other, it improves the global quality (i.e., level of performance, low memory usage and low energy consumption) of the final DMM obtained in a 36.36% with respect to two well-known general-purpose DMMs and two state-of-the-art optimization methodologies. © 2024, CC BY-SA.

关键词： Energy utilization

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Simulation of High-Performance Memory Allocators

arXiv

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arXiv 2024年

作者： Risco-Martín, José L. Colmenar, J. Manuel Atienza, David Hidalgo, J. Ignacio Department of Computer Architecture and Automation Universidad Complutense de Madrid Madrid28040 Spain C. E. S. Felipe II Universidad Complutense de Madrid Aranjuez28300 Spain Lausanne1015 Switzerland

For the last thirty years, a large variety of memory allocators have been proposed. Since performance, memory usage and energy consumption of each memory allocator differs, software engineers often face difficult choices in selecting the most suitable approach for their applications. To this end, custom allocators are developed from scratch, which is a difficult and error-prone process. This issue has special impact in the field of portable consumer embedded systems, that must execute a limited amount of multimedia applications, demanding high performance and extensive memory usage at a low energy consumption. This paper presents a flexible and efficient simulator to study Dynamic Memory Managers (DMMs), a composition of one or more memory allocators. This novel approach allows programmers to simulate custom and general DMMs, which can be composed without incurring any additional runtime overhead or additional programming cost. We show that this infrastructure simplifies DMM construction, mainly because the target application does not need to be compiled every time a new DMM must be evaluated and because we propose a structured method to search and build DMMs in an object-oriented fashion. Within a search procedure, the system designer can choose the "best" allocator by simulation for a particular target application and embedded system. In our evaluation, we show that our scheme delivers better performance, less memory usage and less energy consumption than single memory allocators. © 2024, CC BY-SA.

关键词： Embedded systems

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QDMI - Quantum Device Management Interface: Hardware-Software Interface for the Munich Quantum Software Stack

QDMI - Quantum Device Management Interface: Hardware-Softwar...

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Quantum Computing and Engineering (QCE), IEEE International Conference on

作者： Robert Wille Ludwig Schmid Yannick Stade Jorge Echavarria Martin Schulz Laura Schulz Lukas Burgholzer Chair for Design Automation Technical University of Munich Munich Germany Software Competence Center Hagenberg GmbH Hagenberg Austria Leibniz Supercomputing Centre Garching Germany Chair of Computer Architecture and Parallel Systems Technical University of Munich Munich Germany

ISBN: (数字)9798331541378

ISBN: (纸本)9798331541385

Quantum computing is a promising technology that requires a sophisticated software stack to connect end users to the wide range of possible quantum backends. However, current software tools are usually hard-coded for single platforms and lack a dynamic interface that can automatically retrieve and adapt to changing physical characteristics and constraints of different platforms. With new hardware platforms frequently introduced and their performance changing on a daily basis, this constitutes a serious limitation. In this paper, we show-case a concept and a prototypical realization of an interface, called the Quantum Device Management Interface (QDMI), that addresses this problem by explicitly connecting the software and hardware developers, mediating between their competing interests. QDMI allows hardware platforms to provide their physical characteristics in a standardized way, and software tools to query that data to guide the compilation process accordingly. This enables software tools to automatically adapt to different platforms and to optimize the compilation process for the specific hardware constraints. QDMI is a central part of the Munich Quantum Software Stack (MQSS)-a sophisticated software stack to connect end users to the wide range of possible quantum backends. QDMI is publicly available as open source at https://***/Munich-Quantum-Software-Stack/QDMI.

关键词： Performance evaluation Quantum computing Full stack Hardware Software tools

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Passive Attack Detection for a Class of Stealthy Intermittent Integrity Attacks

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IEEE/CAA Journal of Automatica Sinica 2023年第4期10卷 898-915页

作者： Kangkang Zhang Christodoulos Keliris Thomas Parisini Bin Jiang Marios M.Polycarpou Department of Electrical and Electronic Engineering Imperial College LondonLondon SW72AZUKand also with the KIOS Research and Innovation Center of ExcellenceUniversity of CyprusNicosia 1678Cyprus KIOS Research and Innovation Center of Excellence and the Department of Electrical and Computer Engineering University of CyprusNicosia 1678Cyprus Department of Electrical and Electronic Engineering Imperial College LondonLondon SW72AZUK Department of Engineering and Architecture University of TriesteTrieste 34127Italy KIOS Research and Innovation Center of Excellence University of CyprusNicosia 1678Cyprus College of Automation Engineering Nanjing University of Aeronautics and AstronauticsNanjing 210016China

This paper proposes a passive methodology for detecting a class of stealthy intermittent integrity attacks in cyberphysical systems subject to process disturbances and measurement noise.A stealthy intermittent integrity attack strategy is first proposed by modifying a zero-dynamics attack *** stealthiness of the generated attacks is rigorously investigated under the condition that the adversary does not know precisely the system state *** order to help detect such attacks,a backward-in-time detection residual is proposed based on an equivalent quantity of the system state change,due to the attack,at a time prior to the attack occurrence time.A key characteristic of this residual is that its magnitude increases every time a new attack *** estimate this unknown residual,an optimal fixed-point smoother is proposed by minimizing a piece-wise linear quadratic cost function with a set of specifically designed weighting *** smoother design guarantees robustness with respect to process disturbances and measurement noise,and is also able to maintain sensitivity as time progresses to intermittent integrity attack by resetting the covariance matrix based on the weighting *** adaptive threshold is designed based on the estimated backward-in-time residual,and the attack detectability analysis is rigorously investigated to characterize quantitatively the class of attacks that can be detected by the proposed ***,a simulation example is used to demonstrate the effectiveness of the developed methodology.

关键词： Backward-in-time equivalent quantity fixed-point smoother intermittent integrity attacks

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Green Adaptation of Real-Time Web Services for Industrial CPS within a Cloud Environment

arXiv

引用

arXiv 2024年

作者： Higuera-Toledano, M. Teresa Risco-Martín, José L. Arroba, Patricia Ayala, José L. Department of Computer Architecture and Automation Complutense University of Madrid C/Prof. José García Santesmases 9 Madrid28040 Spain Department of Electronic Engineering Technical University of Madrid Avda. Complutense 30 Madrid28040 Spain

Managing energy efficiency under timing constraints is an interesting and big challenge. This work proposes an accurate power model in data centers for time-constrained servers in Cloud computing. This model, as opposed to previous approaches, does not only consider the workload assigned to the processing element, but also incorporates the need of considering the static power consumption and, even more interestingly, its dependency with temperature. The proposed model has been used in a multi-objective optimization environment in which the Dynamic Voltage and Frequency Scaling (DVFS) and workload assignment have been efficiently optimized. © 2024, CC BY-SA.

关键词： Energy efficiency

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VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency

VRank: Enhancing Verilog Code Generation from Large Language...

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IEEE International Symposium on Quality Electronic Design

作者： Zhuorui Zhao Ruidi Qiu Ing-Chao Lin Grace Li Zhang Bing Li Ulf Schlichtmann Chair of Electronic Design Automation Technical University of Munich (TUM) Munich Germany Computer Architecture and IC Design National Cheng Kung University Hardware for Artificial Intelligence Group Technical University of Darmstadt Research Group of Digital Integrated Systems University of Siegen

ISBN: (数字)9798331509422

ISBN: (纸本)9798331509439

Large Language Models (LLMs) have demonstrated promising capabilities in generating Verilog code from module specifications. To improve the quality of such generated Verilog codes, previous methods require either time-consuming manual inspection or generation of multiple Verilog codes, from which the one with the highest quality is selected with manually designed testbenches. To enhance the generation efficiency while maintaining the quality of the generated codes, we propose VRank, an automatic framework that generates Verilog codes with LLMs. In our framework, multiple code candidates are generated with LLMs by leveraging their probabilistic nature. Afterwards, we group Verilog code candidates into clusters based on identical outputs when tested against the same testbench, which is also generated by LLMs. Clusters are ranked based on the consistency they show on testbench. To determine the best candidate, Chain-of-Thought is further applied to select the best candidate from the top-ranked clusters. By systematically analyzing diverse outputs of generated codes, VRank reduces errors and enhances the overall quality of the generated Verilog code. Experimental results on the VerilogEval-Human benchmark demonstrate a significant 10.5% average increase in functional correctness (pass@1) across multiple LLMs, demonstrating VRank's effectiveness in improving the accuracy of automated hardware description language generation for complex design tasks.

关键词： Codes Accuracy Large language models Manuals Inspection Probabilistic logic Hardware Cognition Reliability Hardware design languages

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Towards the Munich Quantum Software Stack: Enabling Efficient Access and Tool Support for Quantum computers

Towards the Munich Quantum Software Stack: Enabling Efficien...

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Quantum Computing and Engineering (QCE), IEEE International Conference on

作者： Martin Schulz Laura Schulz Martin Ruefenacht Robert Wille Chair of Computer Architecture and Parallel Systems Technical University of Munich Munich Germany QCT Department Leibniz Supercomputing Centre Garching Germany Chair of Design Automation Technical University of Munich Munich Germany

As quantum computing systems mature and move from laboratories to production computing environments, corresponding software stacks are becoming key for their successful utilization. In particular, the expected use of quantum systems as HPC accelerators requires a deep integration with the existing and widely deployed HPC software stacks. Additionally, new requirements such as dynamic compilation and new challenges for tools and programming models must be considered. We tackle these challenges by developing the Munich Quantum Software Stack—a comprehensive initiative by the Munich Quantum Valley to offer a flexible, efficient, and user-oriented software environment. In this poster, we describe the core components and workflows, and how they will enable this transformation from quantum experiments to quantum accelerators.

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Development of an interface for digital neuromorphic hardware based on an FPGA

arXiv

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arXiv 2023年

作者： Harmann, René Sohlbach, Lukas Perez-Peña, Fernando Schmidt, Karsten Department of Computer Science and Engineering Frankfurt University of Applied Sciences Nibelungenplatz 1 Frankfurt60318 Germany Department of Automation Electronics and Computer Architecture and Networks School of Engineering University of Cadiz Avda. de la Universidad 10 Puerto Real11519 Spain

Exploring and understanding the functioning of the human brain is one of the greatest challenges for current research. Neuromorphic engineering tries to address this challenge by abstracting biological mechanisms and translating them into technology. Via the abstraction process and experiments with the resulting technical system, an attempt is made to obtain information about the biological counterpart. One subsection of Neuromorphic Engineering (NE) are Spiking Neural Networks (SNN), which describe the structures of the human brain more and more closely than Artificial Neural Networks (ANN). Together with their dedicated hardware, SNNs provide a good platform for developing new algorithms for information processing. In the context of these neuromorphic hardware platforms, this paper aims to develop an interface for a digital hardware platform (SPINN-3 Development Board) to enable the use of industrial or conventional sensors and thus create new approaches for experimental research. The basis for this endeavor is a Field Programmable Gate Array (FPGA), which is placed as a gateway between the sensors and the neuromorphic hardware. Overall, the developed system provides a robust solution for a wide variety of investigations related to neuromorphic hardware and SNNs. Furthermore, the solution also offers suitable possibilities to monitor all processes within the system in order to obtain suitable measurements, which can be examined in search of meaningful results. © 2023, CC BY-NC-ND.

关键词： Neural networks

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