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检索条件"机构=Computer Architecture and Dependable Systems Laboratory Indian Institute of Technology"

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Achieving full functional coverage for the forwarding unit of pipelined processors

Achieving full functional coverage for the forwarding unit o...

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2017 IEEE East-West Design and Test Symposium, EWDTS 2017

作者： Vineesh, V.S. Hage, Nihar Karthik, B Singh, Virendra Computer Architecture and Dependable Systems Lab Department of Electrical Engineering Indian Institute of Technology Bombay India

ISBN: (纸本)9781538632994

Generic instruction based testing methods do not always give good fault coverage for the complex units like Forwarding unit. Hence it becomes important to carefully craft the test which are best for different parts of these units. In this paper we have identified two different test generation methods for different sections of the forwarding unit, namely muxes and comparators which offers better coverage independently: template based test instruction generation and test instruction generation from constrained test vectors. A wrapper designed using the functional constraints of the forwarding unit, is used for test generation. Both methods combined delivers fault coverage of 97.33%. A detailed analysis of the non-detected faults revealed the fact that they cannot be tested using the instruction set of the processor (MIPS 5-stage pipelined processor). This proves that the proposed method achieved 100% functional coverage for stuck-at faults in the forwarding unit. © 2017 IEEE.

关键词： Testing

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Way sharing set associative cache architecture

Way sharing set associative cache architecture

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25th International Conference on VLSI Design, VLSID 2012 and the 11th International Conference on Embedded systems

作者： Janraj, C.J. Kalyan, T. Venkata Warrier, Tripti Mutyam, Madhu Computer Architecture and Systems Laboratory Department of Computer Science and Engineering Indian Institute of Technology Madras Chennai 600036 India

ISBN: (纸本)9780769546384

In order to minimize the conflict miss rate, cache memories can be organized in set-associative manner. The downside of increasing the associativity is increase in the per access energy consumption. In conventional n-way set-associative caches, irrespective of the set-wise demand, each set has n cache ways at its disposal, but cache sets may exhibit nonuniform demand for these cache ways. Exploiting this property, we propose a novel cache architecture, called way sharing cache, wherein by allowing sharing of cache ways among a pair of cache sets, we obtain dynamic energy savings as high as 41% in DL1 cache with negligible performance penalty. © 2012 IEEE.

关键词： Energy conservation

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BOFAR: Buffer occupancy factor based adaptive router for mesh NoCs

BOFAR: Buffer occupancy factor based adaptive router for mes...

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4th International Workshop on Network on Chip architectures, NoCArc 2011, in Conjunction with the 44th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO44

作者： Jose, John Shankar, J. Shiva Mahathi, K.V. Kumar, Damarla Kranthi Mutyam, Madhu Computer Architecture and Systems Laboratory Department of Computer Science and Engineering Indian Institute of Technology Madras Chennai-36 India

ISBN: (纸本)9781450309479

If the route computation operation in an adaptive router returns more than one output channels, the selection strategy chooses one from them based on the congestion metric used. The effectiveness of a selection strategy depends on what metric is used to identify congestion and how precisely that metric captures the actual congestion. The number of cycles a flit stays in a router is a direct indication of the contention level of the output port it desires to move out. We propose buffer Occupancy Factor based Adaptive Router (BOFAR), wherein the history of cycles spent by flits in buffers is used as the congestion metric. BOFAR outperforms the baseline architectures built on minimal odd-even adaptive router model with conventional selection strategies like count of free downstream virtual channels at reachable neighbors, and fluidity of buffers in downstream neighbors. Our experiments on 4x4 mesh NoC with various synthetic traffic patterns show that BOFAR exceeds the performance of best baseline adaptive router with 21% average and 78% maximum latency reduction at saturation load. The reduced average packet latency, increased buffer fluidity fairness, and increased saturation point of BOFAR with minimal overhead in area, power, and wiring makes it a promising alternative to existing adaptive routers in mesh NoCs. © 2011 ACM.

关键词： Network-on-chip

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Early Execution for Soft Error Detection

Early Execution for Soft Error Detection

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International Conference on VLSI Design

作者： Raj Kumar Choudhary Janeel Patel Virendra Singh Computer Architecture and Dependable Systems Laboratory Indian Institute of Technology Bombay India

Single event upsets have made modern integrated circuits more susceptible to soft errors, making their operation less reliable. In order to detect induced computational faults, we propose a fault-tolerant, low-overhead microarchitecture that detects soft errors using temporal redundancy. The idea of introducing an Early Execution Unit (EXU) at the processor frontend has been explored by previous proposals in order to execute dynamic instructions with short dependency chains expeditiously for performance improvement. However, we observe that the functional units in the EXU are idle for a significant portion of the program execution duration. Our proposed microarchitecture utilises these inactive frontend functional units in order to re-execute dynamic instructions to ascertain computational correctness. A low-overhead backend verifier leverages idle resources for redundant execution using the proposed priority-based scheduling algorithm that interleaves program execution with re-execution for error detection. Our proposal provides exhaustive transient fault coverage while improving performance by 7.5% over an existing restricted OoO microarchitecture, Freeflow Core, delivering IPC close to that of an out-of-order baseline, while being $1.78 \times $ more energy-efficient than the involuted, power-hungry out-of-order design.

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ERrOR: Improving Performance and Fault Tolerance Using Early Execution

ERrOR: Improving Performance and Fault Tolerance Using Early...

引用

IEEE Symposium on On-Line Testing (IOLTS)

作者： Raj Kumar Choudhary Janeel Patel Virendra Singh Computer Architecture and Dependable Systems Laboratory Indian Institute of Technology Bombay India

Contemporary integrated circuits are becoming increasingly susceptible to soft errors due to single-event upsets, effectively decreasing the reliability of operation. In this paper, we propose the ERrOR microarchitecture, that detects soft errors in processor operation using temporal redundancy with minimal hardware overhead. Previous proposals have explored the idea of introducing an Early Execution Unit (EXU) at the processor frontend in order to expeditiously execute dynamic instructions with short dependency chains for performance improvement. However, we observe that the functional units in the EXU are idle for a significant fraction of the program execution duration. ERrOR leverages these inactive frontend functional units to re-execute dynamic instructions for the purpose of error detection. A lightweight verifier introduced at the backend makes use of idle resources for redundant execution by interleaving program execution with re-execution for error detection. ERrOR provides exhaustive transient fault coverage while improving performance by 7.5% over an existing restricted OoO microarchitecture, Freeflow Core.

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REMO: Redundant execution with minimum area, power, performance overhead fault tolerant architecture

REMO: Redundant execution with minimum area, power, performa...

引用

IEEE Symposium on On-Line Testing (IOLTS)

作者： Shoba Gopalakrishnan Virendra Singh Computer Architecture & Dependable Systems Lab Indian Institute of Technology Bombay India

ISBN: (纸本)9781509015085

Relentless scaling in CMOS fabrication technology has made contemporary integrated circuits continue to evolve and grow in functionality with high clock frequencies and exponentially increasing transistor counts. However, it also makes them more susceptible to transient faults effectively decreasing their reliability. Therefore, ensuring correct and reliable operation of these microprocessors at low cost has become a challenging task. This paper proposes a light weight error detection method called REMO which aims to incorporate simple fault tolerance mechanisms as part of the basic architecture. It dynamically verifies the execution results of the instructions by exploiting spatial and temporal redundancy and detects soft errors. REMO shows that with minimal area, power and performance overhead, and a very low detection latency, a very high degree of fault coverage can be achieved. Our simulation results shows an increase in area is about 0.4%, power overhead near to 9% and a negligible performance penalty during fault free run.

关键词： Redundancy Out of order Pipelines Hardware Fault tolerant systems

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Dynamic Optimizations in GPU Using Roofline Model

Dynamic Optimizations in GPU Using Roofline Model

引用

IEEE International Symposium on Circuits and systems

作者： Winnie Thomas Suryakant Toraskar Virendra Singh Computer Architecture and Dependable Systems Laboratory Dept. of Electrical Engineering Indian Institute of Technology Bombay India

ISBN: (纸本)9781728192017;9781728192024

Massively parallel processors such as graphics processing units (GPUs) often face the challenge of resource underutilization due to varying resource proclivity of workloads. Running multiple applications on a GPU has been an efficient and known alternative to mitigate underutilization. This paper proposes a multi-application oriented framework that carries out dynamic optimizations based on the operational intensities of various applications. Our framework analyzes applications based on operational intensities to identify their bottleneck resources using Roofline model. We demonstrate that the proposed optimizations improve the utilization and system-wide throughput of the GPU co-running applications with irregular resource demands. The dynamic optimizations improve the performance by 14.8% on average and up to 72.4% over a state-of-the-art spatial multitasking technique.

关键词： Heuristic algorithms Graphics processing units Throughput Multitasking Resource management Optimization Faces

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A trace signal selection algorithm for improved post-silicon debug

A trace signal selection algorithm for improved post-silicon...

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East-West Design & Test Symposium (EWDTS)

作者： Binod Kumar Ankit Jindal Virendra Singh Computer Architecture and Dependable Systems Lab (CADSL) Indian Institute of Technology Bombay India

ISBN: (纸本)9781509006946

Enhancing observability is a key challenge in post-silicon validation. On-chip trace buffers store real time data which can be used for analyzing and debugging. Appropriate selection of these signals is crucial for storing useful debug data. This paper proposes a methodology for identifying trace signals so as to maximize detection of erroneous behavior of the failing chip which helps in improving quality of information available for debugging. Different quantitative measures are proposed to assess utility of debug data. Experimental results on benchmark circuits indicate that the methodology is useful for selecting trace signals which maximize debug data effectiveness.

关键词： computer bugs Clocks Logic gates Buffer storage Algorithm design and analysis Silicon Debugging

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PHP: Power hungry pattern generation at higher abstraction level

PHP: Power hungry pattern generation at higher abstraction l...

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East-West Design & Test Symposium (EWDTS)

作者： Rohini Gulve Anshu Goel Virendra Singh Computer Architecture and Dependable Systems Lab Electrical Engineering Indian Institute of Technology Bombay India

The Performance, area, and power are most essential factors to be considered and optimize at every step in the design cycle. Design engineers often need to learn about these factors in order make right decisions on design strategies. Power analysis at lower levels of abstraction can provide more accurate analysis than higher levels. Worst case power can be estimated through high activity pattern generation. However, generation of such power hungry patterns (PHP) become challenging as the number of modules or design components increases. This process can be accelerated at higher abstraction levels by utilizing the available information. In this paper, we generate PHP by at higher abstraction level with significant speed up. A genetic algorithm is implemented to find out the global maximum power of designs. An experiment indicates that the process implemented is much faster and it finds about 10 % more power demanding PHP than random samples generated.

关键词： Mathematical model Genetic algorithms Integrated circuit modeling Logic gates Power demand Optimization Libraries

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A technique for low power, stuck-at fault diagnosable and reconfigurable scan architecture

A technique for low power, stuck-at fault diagnosable and re...

引用

East-West Design & Test Symposium (EWDTS)

作者： Binod Kumar Boda Nehru Brajesh Pandey Virendra Singh Jaynarayan Tudu Computer Architecture and Dependable Systems Lab (CADSL) Indian Institute of Technology Bombay India Dept. of Computer Science and Automation Indian Institute of Science Bangalore

ISBN: (纸本)9781509006946

Power dissipation is a major issue with testing of designs having full scan architectures. The proposed scan technique minimizes toggle activity while scanning in test patterns. The method uses bit inversion technique to avoid toggles in scan flip-flops. The setup is dynamically configurable to one among the logic reversal structure and traditional scan while shift-in/shift-out of test patterns. Experimental results indicate that the average toggle activity is minimized substantially compared to California Scan architecture. It has features of full diagnosability of single stuck-at faults along the scan chain path.

关键词： computer architecture Silicon Circuit faults Testing Logic gates Inverters Clocks

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