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检索条件"机构=Computer Architecture and Languages Laboratory Institute of Computer Science"

共 738 条记录，以下是131-140 订阅

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Fusion Coherence: Scalable Cache Coherence for Heterogeneous Kilo-Core System

Fusion Coherence: Scalable Cache Coherence for Heterogeneous...

引用

10th Annual Conference of Advanced computer architecture, ACA 2014

作者： Pei, Songwen Kim, Myoung-Seo Gaudiot, Jean-Luc Xiong, Naixue Department of Computer Science and Engineering University of Shanghai for Science and Technology Shanghai 200093 China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Department of Electrical Engineering and Computer Science University of California Irvine CA 92697 United States School of Computer Science Colorado Technical University Springs CO 80907 United States

ISBN: (纸本)9783662444900

Future heterogeneous systems will integrate CPUs and GPUs on a single chip to achieve high computing performance as well as high throughput. In general, it would discard the current discrete pattern and will build a uniformed shared memory system avoiding explicit data movement among CPUs and GPUs connected by high throughput NoC. We propose a scalable cache coherence solution Fusion Coherence for Heterogeneous Kilo-core System architecture by integrating CPUs and GPUs on a single chip to mitigate the coherence bandwidth side effects of GPU memory requests as well as overhead of copying data among memories of CPUs and GPUs. The Fusion Coherence coalesces L3 data cache of CPUs and GPUs based on a uniformed physical memory, further integrates a region directory and cuckoo directory into two levels of cache coherence directory without modifying cache coherence protocol. According to the experimental results with a subset of Rodina benchmarks, it is effective to decrease the overhead of data transfer and get an average execution speedup by 2.4x. The highest speedup is approximate to 4x for data-intensive applications. © Springer-Verlag Berlin Heidelberg 2014.

关键词： Program processors

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Flooding-X: Improving BERT's Resistance to Adversarial Attacks via Loss-Restricted Fine-Tuning 60

Flooding-X: Improving BERT's Resistance to Adversarial Attac...

引用

60th Annual Meeting of the Association for Computational Linguistics, ACL 2022

作者： Liu, Qin Zheng, Rui Bao, Rong Liu, Jingyi Liu, ZhiHua Cheng, Zhanzhan Qiao, Liang Gui, Tao Zhang, Qi Huang, Xuanjing School of Computer Science Fudan University China Institute of Modern Languages and Linguistics Fudan University China Shanghai Key Laboratory of Intelligent Information Processing China Hikvision Research Institute Hangzhou China

ISBN: (纸本)9781955917216

Adversarial robustness has attracted much attention recently, and the mainstream solution is adversarial training. However, the tradition of generating adversarial perturbations for each input embedding (in the settings of NLP) scales up the training computational complexity by the number of gradient steps it takes to obtain the adversarial samples. To address this problem, we leverage Flooding method which primarily aims at better generalization and we find promising in defending adversarial attacks. We further propose an effective criterion to bring hyper-parameter-dependent flooding into effect with a narrowed-down search space by measuring how the gradient steps taken within one epoch affect the loss of each batch. Our approach requires zero adversarial sample for training, and its time consumption is equivalent to fine-tuning, which can be 2-15 times faster than standard adversarial training. We experimentally show that our method improves BERT's resistance to textual adversarial attacks by a large margin, and achieves state-of-the-art robust accuracy on various text classification and GLUE tasks. © 2022 Association for Computational Linguistics.

关键词： Floods

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Xdn: towards efficient inference of residual neural networks on cambricon chips 2nd

Xdn: towards efficient inference of residual neural networks...

引用

2nd International Symposium on Benchmarking, Measuring, and Optimization, Bench 2019

作者： Li, Guangli Wang, Xueying Ma, Xiu Liu, Lei Feng, Xiaobing State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China School of Computer Science and Technology University of Chinese Academy of Sciences Beijing China College of Computer Science and Technology Jilin University Changchun China MOE Key Laboratory of Symbolic Computation and Knowledge Engineering Jilin University Changchun China

ISBN: (纸本)9783030495558

In this paper, we present XDN, an optimization and inference engine for accelerating residual neural networks on Cambricon chips. We leverage a channel pruning method to compress the weights of ResNet-50. By exploring the optimization opportunities in computational graphs, we propose a layer fusion strategy, which dramatically decreases the number of scalar computation layers, such as Batch Normalization, Scale. Furthermore, we design an efficient implementation of XDN, including data preprocessing, hyper-parameter auto-tuning, etc. The experimental results show that the ResNet-50 model can achieve significant speedup without accuracy loss by using our XDN engine. © Springer Nature Switzerland AG 2020.

关键词： Engines

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An ultra-fast hybrid simulation framework for ASIP

An ultra-fast hybrid simulation framework for ASIP

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2011 18th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2011

作者： Qiu, Ji Gao, Xiang Jiang, Yifei Xiao, Xu Key Laboratory of Computer System and Architecture Institute of Computing Technology Graduate University of Chinese Academy of Science Beijing 100190 China Department of Electrical and Computer Engineering University of Illinois at Urbana-Champaign Urbana IL United States

ISBN: (纸本)9781457718458

ISS (Instruction Set Simulator) plays an important role in pre-silicon software development for ASIP. However, the speed of traditional simulation is too slow to effectively support full-scale software development. In this paper, we propose a hybrid simulation framework which further improves the previous simulation methods by aggressively utilizing the host machine resources. The utilization is achieved by categorizing instructions of ASIP application into two types, namely custom and basic instructions, via binary instrumentation. Then in a way of hybrid simulation, only custom instructions are simulated on the ISS and basic instructions are executed fast and natively on the host machine. We implement this framework for an industrial ASIP to validate our approach. Experimental results show that when the implemented ISS, namely GS-Sim, is applied to practical multimedia decoders, an average simulation speed up to 1058.5MIPS can be achieved, which is 34.7 times of the state-of-art dynamic binary translation simulator and is the fastest to the best of our knowledge. © 2011 IEEE.

关键词： Software design

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Concurrency bug localization using shared memory access pairs 14

Concurrency bug localization using shared memory access pair...

引用

2014 19th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPoPP 2014

作者： Wang, Wenwen Wu, Chenggang Yew, Pen-Chung Yuan, Xiang Wang, Zhenjiang Li, Jianjun Feng, Xiaobing State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China University of Chinese Academy of Sciences Beijing China Department of Computer Science and Engineering University of Minnesota at Twin-Cities United States

ISBN: (纸本)9781450326568

Non-determinism in concurrent programs makes their debugging much more challenging than that in sequential programs. To mitigate such difficulties, we propose a new technique to automatically locate buggy shared memory accesses that triggered concurrency bugs. Compared to existing fault localization techniques that are based on empirical statistical approaches, this technique has two advantages. First, as long as enough successful runs of a concurrent program are collected, the proposed technique can locate buggy memory accesses to the shared data even with only one single failed run captured, as opposed to the need of capturing multiple failed runs in other statistical approaches. Second, the proposed technique is more precise because it considers memory accesses in those failed runs that terminate prematurely.

关键词： Program debugging

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Concurrency bug localization using shared memory access pairs

Concurrency bug localization using shared memory access pair...

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关键词： Memory architecture

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Optimizing web browser on many-core architectures

Optimizing web browser on many-core architectures

引用

2011 12th International Conference on Parallel and Distributed Computing, Applications and Technologies, PDCAT 2011

作者： Fan, Lingjun Shi, Weisong Tang, Shibin Yan, Chenggang Fan, Dongrui Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Academy of Sciences Graduate University Beijing China Department of Computer Science Wayne State University Detroit United States

ISBN: (纸本)9780769545646

As more and more Web applications emerging on sever end today, the Web browser on client end has become a host of a variety of applications other than just rendering static Web pages. This leads to more and more performance requirements of a Web browser, for which user experience is very important. This situation may become more urgency when on handheld devices. Some efforts like redesign a new Web browser have been made to overcome this problem. In this paper, we address this issue by optimizing the main processes of the Web browser on a state-of-the-art 64-core architecture, Godson-T, which was developed at Chinese Academy of sciences, as multi-/many-core architecture to be the mainstream processor in the upcoming years. We start a new core to process a new tab when facing up to intensive URL requests, and we use scratch-pad memory (SPM) of each core as a local buffer to store the HTML source data to be processed to reduce off-chip memory access and exploit more data locality, otherwise, we use DTA to transfer HTML data for backup. Experiments conducted on the cycle-accurate simulator show that, starting each tab process by a new core could obtain 5.7% to 50% speedup with different number of cores used to process corresponding URL requests, with onchip scratchpad memory of each core used to store the HTML data, more speedup could be achieved when number of cores increase. Also, as Data Transfer Agent (DTA) used to transfer the HTML data, the backup of HTML data can get 2X to 5X speedups according to different data amount. © 2011 IEEE.

关键词： Data transfer

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Safety and Ethical Concerns of Large Language Models 22

Safety and Ethical Concerns of Large Language Models

引用

22nd Chinese National Conference on Computational Linguistics, CCL 2023

作者： Xi, Zhiheng Zheng, Rui Gui, Tao School of Computer Science Fudan University Shanghai China Shanghai Key Laboratory of Intelligent Information Processing Shanghai China Institute of Modern Languages and Linguistics Fudan University Shanghai China

ISBN: (纸本)9781713889915

Recent months have witnessed significant progress in the field of large language models (LLMs). Represented by ChatGPT and GPT-4, LLMs perform well in various natural language processing tasks and have been applied to many downstream applications to facilitate people’s lives. However, there still exist safety and ethical concerns. Specifically, LLMs suffer from social bias, robustness problems, and poisoning issues, all of which may induce LLMs to spew harmful contents. We propose this tutorial as a gentle introduction to the safety and ethical issues of LLMs. © 2023 China National Conference on Computational Linguistics.

关键词： Computational linguistics

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Mcc: a predictable and scalable massive client load generator 2nd

Mcc: a predictable and scalable massive client load generato...

引用

2nd International Symposium on Benchmarking, Measuring, and Optimization, Bench 2019

作者： Wu, Wenqing Feng, Xiao Zhang, Wenli Chen, Mingyu State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Science Beijing China University of Chinese Academy of Sciences Beijing China Peng Cheng Laboratory Shenzhen China

ISBN: (纸本)9783030495558

The network load generators are widely used by network researchers to analyze link bandwidth, evaluate network performance and test device capabilities. Data center and IoT networks are quickly evolving and we desire to get a load generator that can precisely generate flow-level workload with high-throughput. Often researchers choose software-based generators because of their flexibility and open-source nature. However, despite the emerging of different solutions, existing software-based flow-level generators have difficulty in generating millions of concurrent TCP connections or achieving one-microsecond precision of packet inter departure time (IDT) which can undermine the correctness of experiments. In this paper, we present a new network load generator, called Massive Client Connections (MCC). MCC is a client load generator which means it performs flow-level load simulation. We separate the control plane from the data plane and design a two-stage timer mechanism to get higher precision. To take full advantage of multicore processors, we utilize the shared-nothing multi-threaded model. Our evaluation demonstrates that MCC generates network load conforming to expected distribution with one-microsecond precision. Moreover, MCC shows definite scalability of throughput in multicore systems. And it is capable of generating more than three million concurrent TCP connections with ten CPU cores. © Springer Nature Switzerland AG 2020.

关键词： Scalability

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High Performance Computing for CS-InSAR Data Processing

High Performance Computing for CS-InSAR Data Processing

引用

2021 SAR in Big Data Era, BIGSARDATA 2021

作者： Zhang, Weikang You, Haihang Tang, Yixian Wang, Chao Zhang, Hong Chinese Academy of Sciences State Key Laboratory of Computer Architecture Institute of Computing Technology Beijing China Chinese Academy of Sciences Key Laboratory of Digital Earth Science Aerospace Information Research Institute Beijing China

ISBN: (纸本)9781665401234

In this paper, we have developed a highperformance data processing system for big SAR data based on parallel and distributed computation using supercomputer. Aiming at the pipeline of InSAR, we mainly focus on the parallelization and optimization of computing hotspot to accelerate the operation. Furthermore, we take advantage of the technology of distributed computation and multitask automation to get higher performance - process more data in less time. With the high-performance system, we obtained the nationwide measurement of China's surface movement from September 2018 to February 2020 and from January to December in 2020 using 20-30 computing nodes, processing nearly 1PB of data in total. The calculation time of the two images of national scale surface movement is completed in only 7 and 5 days, respectively. © 2021 IEEE.

关键词： Supercomputers

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