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Adaptive weighting for neural machine translation 27

Adaptive weighting for neural machine translation

引用

27th International Conference on Computational Linguistics, COLING 2018

作者： Li, Yachao Li, Junhui Zhang, Min Institute of Artificial Intelligence School of Computer Science and Technology Soochow University China Key Laboratory of China’s Ethnic Languages and Information Technology of Ministry of Education Northwest Minzu University China

ISBN: (纸本)9781948087506

In the popular sequence to sequence (seq2seq) neural machine translation (NMT), there exist many weighted sum models (WSMs), each of which takes a set of input and generates one output. However, the weights in a WSM are independent of each other and fixed for all inputs, suggesting that by ignoring different needs of inputs, the WSM lacks effective control on the influence of each input. In this paper, we propose adaptive weighting for WSMs to control the contribution of each input. Specifically, we apply adaptive weighting for both GRU and the output state in NMT. Experimentation on Chinese-to-English translation and English-to-German translation demonstrates that the proposed adaptive weighting is able to much improve translation accuracy by achieving significant improvement of 1.49 and 0.92 BLEU points for the two translation tasks. Moreover, we discuss in-depth on what type of information is encoded in the encoder and how information influences the generation of target words in the decoder. © 2018 COLING 2018 - 27th International Conference on Computational Linguistics, Proceedings. All rights reserved.

关键词： Neural machine translation

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Providing fairness on shared-memory multiprocessors via process scheduling 12

Providing fairness on shared-memory multiprocessors via proc...

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12th Joint International Conference on Measurement and Modeling of computer Systems, ACM SIGMETRICS/Performance 2012

作者： Xu, Di Wu, Chenggang Yew, Pen-Chung Li, Jianjun Wang, Zhenjiang State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Graduate University Chinese Academy of Sciences Beijing China Department of Computer Science and Engineering University of Minnesota at Twin-Cities MN United States Institute of Information Science Academia Sinica Taiwan

ISBN: (纸本)9781450310970

Competition for shared memory resources on multiprocessors is the most dominant cause for slowing down applications and makes their performance varies unpredictably. It exacerbates the need for Quality of Service (QoS) on such systems. In this paper, we propose a fair-progress process scheduling (FPS) policy to improve system fairness. Its strategy is to force the equally-weighted applications to have the same amount of slowdown when they run concurrently. The basic approach is to monitor the progress of all applications at runtime. When we find an application suffered more slowdown and accumulated less effective work than others, we allocate more CPU time to give it a better parity. Our policy also allows different weights to different threads, and provides an effective and robust tuner that allows the OS to freely make tradeoffs between system fairness and higher throughput. Evaluation results show that FPS can significantly improve system fairness by an average of 53.5% and 65.0% on a 4-core processor with a private cache and a 4-core processor with a shared cache, respectively. The penalty is about 1.1% and 1.6% of the system throughput. For memory-intensive workloads, FPS also improves system fairness by an average of 45.2% and 21.1% on 4-core and 8-core system respectively at the expense of a throughput loss of about 2%. © 2012 ACM.

关键词： Throughput

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Block-gram: Mining Knowledgeable Features for Smart Contract Vulnerability Detection 7th

Block-gram: Mining Knowledgeable Features for Smart Contrac...

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7th International Conference on Smart Computing and Communication, SmartCom 2022

作者： Li, Tao Wang, Haolong Fang, Yaozheng Jian, Zhaolong Wang, Zichun Xie, Xueshuo Tianjin Key Laboratory of Network and Data Security Technology Tianjin China College of Computer Science Nankai University Tianjin China Key Laboratory of Blockchain and Cyberspace Governance of Zhejiang Province Hangzhou China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

ISBN: (纸本)9783031281235

Effective vulnerability detection of large-scale smart contracts is critical because smart contract attacks frequently bring about tremendous economic loss. However, code analysis requiring traversal paths and learning methods requiring many features training is too time-consuming to detect large-scale on-chain contracts. This paper focuses on improving detection efficiency by reducing the dimension of the features, combined with expert knowledge. We propose a feature extraction method Block-gram to form low-dimensional knowledgeable features from the bytecode. We first separate the metadata and convert the runtime code to opcode sequence, dividing the opcode sequence into segments according to some instructions (jump, etc.). Then, we mine extensible Block-gram features for learning-based model training, consisting of 4-dimensional block features and 8-dimensional attribute features. We evaluate these knowledge-based features using seven state-of-the-art learning algorithms to show that the average detection latency speeds up 25 to 650 times, compared with the features extracted by N-gram. © 2023, The Author(s), under exclusive license to Springer Nature Switzerland AG.

关键词： Smart contract

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Making Parameter-efficient Tuning More Efficient: A Unified Framework for Classification Tasks 29

Making Parameter-efficient Tuning More Efficient: A Unified ...

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29th International Conference on Computational Linguistics, COLING 2022

作者： Zhou, Xin Ma, Ruotian Zou, Yicheng Chen, Xuanting Gui, Tao Zhang, Qi Huang, Xuanjing Xie, Rui Wu, Wei School of Computer Science Fudan University China Institute of Modern Languages and Linguistics Fudan University China Shanghai Key Laboratory of Intelligent Information Processing China Meituan Inc. Beijing China

Large pre-trained language models (PLMs) have demonstrated superior performance in industrial applications. Recent studies have explored parameter-efficient PLM tuning, which only updates a small amount of task-specific parameters while achieving both high efficiency and comparable performance against standard fine-tuning. However, all these methods ignore the inefficiency problem caused by the task-specific output layers, which is inflexible for us to re-use PLMs and introduces non-negligible parameters. In this work, we focus on the text classification task and propose plugin-tuning, a framework that further improves the efficiency of existing parameter-efficient methods with a unified classifier. Specifically, we re-formulate both token and sentence classification tasks into a unified language modeling task, and map label spaces of different tasks into the same vocabulary space. In this way, we can directly re-use the language modeling heads of PLMs, avoiding introducing extra parameters for different tasks. We conduct experiments on six classification benchmarks. The experimental results show that plugin-tuning can achieve comparable performance against fine-tuned PLMs, while further saving around 50% parameters on top of other parameter-efficient methods. © 2022 Proceedings - International Conference on Computational Linguistics, COLING. All rights reserved.

关键词： Classification (of information)

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Scalable parallel flash firmware for many-core architectures 20

Scalable parallel flash firmware for many-core architectures

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Proceedings of the 18th USENIX Conference on File and Storage Technologies

作者： Jie Zhang Miryeong Kwon Michael Swift Myoungsoo Jung Computer Architecture and Memory Systems Laboratory Korea Advanced Institute of Science and Technology Computer Architecture and Memory Systems Laboratory University of Wisconsin at Madison

ISBN: (纸本)9781939133120

NVMe is designed to unshackle flash from a traditional storage bus by allowing hosts to employ many threads to achieve higher bandwidth. While NVMe enables users to fully exploit all levels of parallelism offered by modern SSDs, current firmware designs are not scalable and have difficulty in handling a large number of I/O requests in parallel due to its limited computation power and many hardware *** propose DeepFlash, a novel manycore-based storage platform that can process more than a million I/O requests in a second (1MIOPS) while hiding long latencies imposed by its internal flash media. Inspired by a parallel data analysis system, we design the firmware based on many-to-many threading model that can be scaled horizontally. The proposed DeepFlash can extract the maximum performance of the underlying flash memory complex by concurrently executing multiple firmware components across many cores within the device. To show its extreme parallel scalability, we implement DeepFlash on a many-core prototype processor that employs dozens of lightweight cores, analyze new challenges from parallel I/O processing and address the challenges by applying concurrency-aware optimizations. Our comprehensive evaluation reveals that DeepFlash can serve around 4.5 GB/s, while minimizing the CPU demand on microbenchmarks and real server workloads.

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A scalable parallel ray tracing algorithm for satellite imagery

A scalable parallel ray tracing algorithm for satellite imag...

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IEEE International Conference on computer Research and Development

作者： Li, Yu-Gang Zhao, Kun Huang, Yu-Qing Qiu, Zhen-Ge Liu, Zhi-Yong Beijing Lab. of Intelligent Information Technology School of Computer Science BIT Beijing 100081 China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100081 China Institute of Computing Technology Chinese Academy Sciences Beijing China

ISBN: (纸本)9781612848372

Ray-tracing, can produce high-quality images, however, the use of ray-tracing has been limited due to its high demands on computational power and memory bandwidth, especially in the case of satellite imagery. In this paper, we propose a scalable parallel ray tracing algorithm of satellite imagery on a cluster of multi-core architecture. The algorithm combines demand-driven and data-driven models in order to reduce communication on the cost of maintaining redundant data. In order to make the most of computer's parallelism and increase computational efficiency, it combines two levels of parallelisms, the TLP parallelism brought by the many core architecture and the inter-node parallelism via MPI and OpenMP. Experiment results show that the algorithm is highly scalability. © 2011 IEEE.

关键词： Satellite imagery

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DRAM-Less: Hardware Acceleration of Data Processing with New Memory

DRAM-Less: Hardware Acceleration of Data Processing with New...

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IEEE Symposium on High-Performance computer architecture

作者： Jie Zhang Gyuyoung Park David Donofrio John Shalf Myoungsoo Jung Computer Architecture and Memory Systems Laboratory Korea Advanced Institute of Science and Technology (KAIST) Computer Architecture and Memory Systems Laboratory Lawrence Berkeley National Laboratory

ISBN: (数字)9781728161495

ISBN: (纸本)9781728161501

General purpose hardware accelerators have become major data processing resources in many computing domains. However, the processing capability of hardware accelerations is often limited by costly software interventions and memory copies to support compulsory data movement between different processors and solid-state drives (SSDs). This in turn also wastes a significant amount of energy in modern accelerated systems. In this work, we propose, DRAM-less, a hardware automation approach that precisely integrates many state-of-the-art phase change memory (PRAM) modules into its data processing network to dramatically reduce unnecessary data copies with a minimum of software modifications. We implement a new memory controller that plugs a real 3x nm multi-partition PRAM to 28nm technology FPGA logic cells and interoperate its design into a real PCIe accelerator emulation platform. The evaluation results reveal that our DRAM-less achieves, on average, 47% better performance than advanced acceleration approaches that use a peer-to-peer DMA.

关键词： Phase change random access memory Data processing Hardware Acceleration Kernel Buffer storage

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Eliminating data invalidation in debugging multiple-clock chips

Eliminating data invalidation in debugging multiple-clock ch...

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作者： Gao, Jianliang Han, Yinhe Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China School of Information Science and Engineering Central South University China

ISBN: (纸本)9783981080179

A critical concern for post-silicon debug is the need to control the chip at clock cycle level. In a single clock chip, run-stop control can be implemented by gating the clock signal using a stop signal. However, data invalidation might occur when it comes to multiple-clock chips. In this paper, we analyze the possible data invalidation, including data repetition and data loss, when stopping and resuming a multiple-clock chip. Furthermore, we propose an efficient solution to eliminate data repetition and data loss. Theoretical analysis and simulation experiments are both conducted for the proposed solution. We implement the proposed Design-for-Debug (DfD) circuit with SMIC 0.18/Ltm technology and simulate the data transfer across clock domains using SPICE tool. The results show that both data repetition and data loss can be avoided with the proposed solution, even if metastability occurs. © 2011 EDAA.

关键词： Clocks

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Theoretical treatment of sink scheduling problem in wireless sensor networks

Theoretical treatment of sink scheduling problem in wireless...

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2011 IEEE Conference on computer Communications Workshops, INFOCOM WKSHPS 2011

作者： Gu, Yu Ji, Yusheng Li, Jie Zhao, Baohua Information Systems Architecture Science Research Division National Institute of Informatics Tokyo Japan State Key Laboratory of Networking and Switching Technology Beijing 100876 China School of Computer Science Univ. of Science and Technology of China Hefei Anhui 230027 China Department of Computer Science University of Tsukuba Ibaraki 305-8573 Japan

ISBN: (纸本)9781457702488

Sink Scheduling, in the form of scheduling multiple sinks among sink sites to leverage traffic burden, is an effective mechanism for the energy-efficiency of wireless sensor networks (WSNs). Due to the inherent difficulty (NP-hard in general), existing works on this topic mainly focus on heuristic/greedy algorithms and theoretic results remain unknown. In this paper, we fill in the research blank with two algorithms. The first one is based on the Column Generation (CG). It decomposes the original problem into two sub problems and solve them iteratively to approach the optimal solution. However, due to its high computational complexity, this algorithm is only suitable for small scale networks. The other one is a polynomial-time algorithm based on relaxation techniques to obtain an upperbound, which can serve as a performance benchmark for other algorithms on this problem. Through comprehensive simulations, we evaluate the efficiency of proposed algorithms. © 2011 IEEE.

关键词： Wireless sensor networks

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Multi-FPGA Evaluation Platform for Disaggregated Computing

Multi-FPGA Evaluation Platform for Disaggregated Computing

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Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Dimitris Theodoropoulos Nikolaos Alachiotis Dionisios Pnevmatikatos Computer Architecture and VLSI Systems Laboratory Institute of Computer Science Foundation for Research and Technology - Hellas (FORTH)

We present a versatile FPGA-based evaluation platform for exploring alternative execution strategies on disaggregated environments for applications, considering different processing block types: compute cores, memory, and accelerators. Developers can interconnect different blocks types in order to create optimal configurations. A user-level software library allows quick mapping of applications on real hardware. We have implemented a fully working prototype using three ZC706 FPGA boards, and evaluated different software / hardware configurations of a matrix multiplication benchmark.

关键词： computer architecture Hardware Software Acceleration Prototypes Benchmark testing Resource management

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