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International Conference on Parallel architecture and Compilation Techniques (PACT)

作者： M.G. Valluri R. Govindarajan Laboratory for Computer Architecture ECE Department University of Technology Austin TX USA Supercomputer Education and Research Centre Department of Computer Science and Automation Indian Institute of Science Bangalore India

The phase ordering of register allocation and instruction scheduling in a compiler and their integration have been well studied for in-order issue and VLIW processors. In this paper we study this problem in the context of out-of-order issue processors. Such a study is interesting as the dynamic instruction ordering and register renaming support mechanisms in out-of-order issue processors are similar in spirit to what the complex register allocation and instruction scheduling techniques do at compile-time. We evaluated four existing techniques, namely postpass scheduling, prepass scheduling, parallel interference graph, and integrated prepass scheduling methods. Our initial experimental results reveal that for o-o-o issue processors the focus should be on reducing the register pressure/spill code than exposing the parallelism at compiling time.

关键词： Out of order Registers Processor scheduling VLIW Laboratories computer architecture Supercomputers computer science education computer science Automation

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A java code protection scheme via dynamic recovering runtime instructions 18th

A java code protection scheme via dynamic recovering runtime...

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18th International Conference on Algorithms and architectures for Parallel Processing, ICA3PP 2018

作者： Jiajia, Sun Jinbao, Gao Yu-an, Tan Yu, Zhang Xiao, Yu School of Computer Science and Technology Beijing Institute of Technology Beijing100081 China School of Electrical and Information Engineering Beijing Key Laboratory of Intelligent Processing for Building Big Data Beijing University of Civil Engineering and Architecture Beijing100044 China China University of Mining and Technology Beijing100083 China Department of Computer Science and Technology Shandong University of Technology ZiboShandong255022 China

ISBN: (纸本)9783030050627

As Android operating system and applications on the device play important roles, the security requirements of Android applications increased as well. With the upgrade of Android system, Android runtime mode (ART mode) has gradually become the mainstream architecture of the Android operating system. ART introduces several improvements in Android, but it also introduces new ways to enhance malicious activities. This paper proposed a confidential finer granularity protection scheme for application programs under ART mode of ROOT Android devices. Taking Java method as the protection granularity, the protection scheme increased the accuracy of protecting targets. In addition, the protection scheme provided a more thorough protection for applications by combining dynamic loading technology and encryption technology in ART mode, and improved the security of Android applications. Experiments showed that the proposed protection scheme is effective. © Springer Nature Switzerland AG 2018.

关键词： Android (operating system)

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An Auto-Parallel Method for Deep Learning Models Based on Genetic Algorithm 29

An Auto-Parallel Method for Deep Learning Models Based on Ge...

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29th IEEE International Conference on Parallel and Distributed Systems, ICPADS 2023

作者： Zeng, Yan Huang, Chengchuang Ni, Yijie Zhou, Chunbao Zhang, Jilin Wang, Jue Zhou, Mingyao Xue, Meiting Zhang, Yunquan Hangzhou Dianzi University School of Computer Science and Technology Hangzhou310018 China Ministry of Education Key Laboratory for Modeling and Simulation of Complex Systems Hangzhou310018 China Data Security Governance Zhejiang Engineering Research Center Hangzhou310018 China Hangzhou Dianzi University School of ITMO Joint Institute Hangzhou310018 China Institute of Computer Network Information Center of the Chinese Academy of Sciences Beijing100086 China HuaWei China Institute of Computing Technology of the Chinese Academy of Sciences State Key Laboratory of Computer Architecture Beijing100086 China

ISBN: (纸本)9798350330717

As the size of datasets and neural network models increases, automatic parallelization methods for models have become a research hotspot in recent years. The existing auto-parallel methods based on machine learning or graph algorithms still have issues with search efficiency and applicability. This paper proposes an automatic parallel method based on a dual-population genetic algorithm, TGA, which transforms model partitioning and placement into an integer linear programming problem and constructs a cost model to evaluate the solution. The solution space is built using the neural network's dataflow graph and device cluster's topology, and the dual-population genetic algorithm is used to search for the optimal model parallel strategy. Experiments with various models show that the proposed method can improve single-step execution time by up to 42% compared to the Baechi method and up to 37.7% compared to the Hierarchical method. © 2023 IEEE.

关键词： Auto-Parallel Distributed machine learning Genetic algorithm Integer linear programming Model parallelism

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Panel position statements 3

Panel position statements

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3rd International Symposium on Foundations of Health Information Engineering and Systems, FHIES 2013

作者： Dube, Kudakwashe Moodley, Deshendran Thies, Bill Liu, Jane W.S Cafazzo, Joseph Sokolsky, Oleg School of Engineering and Advanced Technology Massey University New Zealand UKZN/CSIR Meraka Centre for Artificial Intelligence Research and Health Architecture Laboratory School of Mathematics Statistics and Computer Science University of KwaZulu-Natal Durban South Africa Microsoft Research India India Institute of Information Science Academia Sinica Taipei Taiwan Centre for Global eHealth Innovation Canada Department of Computer and Information Science University of Pennsylvania United States

ISBN: (纸本)9783642539558

The western world enjoys a far greater degree of sophistication in computer technology than the developing world; challenges include the fact that infrastructure and resources in the developing world lag far behind; education to use and maintain the technology is often lacking; and cultural and societal issues prohibit its use. Questions include: What is the role of the first world in promoting more widespread use of technology for health informatics? What are the advantages to the first world in promoting more widespread use? What is the role of scientists in the first world in developing technology suitable for less technologically savvy regions? Should we interfere in cultures that do not use technology as we do? What can we practically expect to positively influence by engaging with developing world? How do we engage with the developing world in a sustainable way? Finally, modern vaccines have made huge differences in health the world over; can we expect similar positive transformation from increased computer/information technology in the developing world?

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Modeling Layout Reading Order as Ordering Relations for Visually-rich Document Understanding

Modeling Layout Reading Order as Ordering Relations for Visu...

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2024 Conference on Empirical Methods in Natural Language Processing, EMNLP 2024

作者： Zhang, Chong Tu, Yi Zhao, Yixi Yuan, Chenshu Chen, Huan Zhang, Yue Chai, Mingxu Guo, Ya Zhu, Huijia Zhang, Qi Gui, Tao School of Computer Science Fudan University Shanghai China Shanghai Key Laboratory of Intelligent Information Processing Shanghai China Ant Tiansuan Security Lab Ant Group Hangzhou China School of Statistics and Data Science Nankai University Tianjin China Institute of Modern Languages and Linguistics Fudan University Shanghai China

ISBN: (纸本)9798891761643

Modeling and leveraging layout reading order in visually-rich documents (VrDs) is critical in document intelligence as it captures the rich structure semantics within documents. Previous works typically formulated layout reading order as a permutation of layout elements, i.e. a sequence containing all the layout elements. However, we argue that this formulation does not adequately convey the complete reading order information in the layout, which may potentially lead to performance decline in downstream VrD tasks. To address this issue, we propose to model the layout reading order as ordering relations over the set of layout elements, which have sufficient expressive capability for the complete reading order information. To enable empirical evaluation on methods towards the improved form of reading order prediction (ROP), we establish a comprehensive benchmark dataset including the reading order annotation as relations over layout elements, together with a relation-extraction-based method that outperforms previous methods. Moreover, to highlight the practical benefits of introducing the improved form of layout reading order, we propose a reading-order-relation-enhancing pipeline to improve model performance on any arbitrary VrD task by introducing additional reading order relation inputs. Comprehensive results demonstrate that the pipeline generally benefits downstream VrD tasks: (1) with utilizing the reading order relation information, the enhanced downstream models achieve SOTA results on both two task settings of the targeted dataset;(2) with utilizing the pseudo reading order information generated by the proposed ROP model, the performance of the enhanced models has improved across all three models and eight cross-domain VrD-IE/QA task settings without targeted optimization. © 2024 Association for Computational Linguistics.

关键词： Semantics

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Unveiling and Consulting Core Experts in Retrieval-Augmented MoE-based LLMs

Unveiling and Consulting Core Experts in Retrieval-Augmented...

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2024 Conference on Empirical Methods in Natural Language Processing, EMNLP 2024

作者： Zhou, Xin Nie, Ping Guo, Yiwen Wei, Haojie Zhang, Zhanqiu Minervini, Pasquale Ma, Ruotian Gui, Tao Zhang, Qi Huang, Xuanjing School of Computer Science Fudan University Shanghai China LightSpeed Studios Tencent China Institute of Modern Languages and Linguistics Fudan University Shanghai China Key Laboratory of Intelligent Information Processing Fudan University Shanghai China School of Informatics and ELLIS University of Edinburgh United Kingdom

ISBN: (纸本)9798891761643

Retrieval-Augmented Generation (RAG) significantly improved the ability of Large Language Models (LLMs) to solve knowledge-intensive tasks. While existing research seeks to enhance RAG performance by retrieving higher-quality documents or designing RAG-specific LLMs, the internal mechanisms within LLMs that contribute to the effectiveness of RAG systems remain underexplored. In this paper, we aim to investigate these internal mechanisms within the popular Mixture-of-Expert (MoE)based LLMs and demonstrate how to improve RAG by examining expert activations in these LLMs. Our controlled experiments reveal that several core groups of experts are primarily responsible for RAG-related behaviors. The activation of these core experts can signify the model's inclination towards external/internal knowledge and adjust its behavior. For instance, we identify core experts that can (1) indicate the sufficiency of the model's internal knowledge, (2) assess the quality of retrieved documents, and (3) enhance the model's ability to utilize context. Based on these findings, we propose several strategies to enhance RAG's efficiency and effectiveness through expert activation. Experimental results across various datasets and MoE-based LLMs show the effectiveness of our method. © 2024 Association for Computational Linguistics.

关键词： Computational linguistics

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WIP: An Engaging Undergraduate Intro to Model Checking in Software Engineering Using TLA+

WIP: An Engaging Undergraduate Intro to Model Checking in So...

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Frontiers in Education (FIE) Conference

作者： Konstantin Läufer Gunda Mertin George K. Thiruvathukal Department of Computer Science Software and Systems Laboratory Loyola University Chicago Institute for Software Engineering and Programming Languages University of Lübeck

ISBN: (数字)9798350351507

ISBN: (纸本)9798350363067

Background: In this Innovative Practice Work in Progress, we present our initial efforts to integrate formal methods, with a focus on model-checking specifications written in Temporal Logic of Actions $(\text{TLA}^{+})$ , into computer science education, targeting undergraduate juniors/seniors and graduate students. Many safety-critical systems and services crucially depend on correct and reliable behavior. Formal methods can play a key role in ensuring correct and safe system behavior, yet remain underutilized in educational and industry contexts. Aims: We aim to (1) qualitatively assess the state of formal methods in computer science programs, (2) construct level-appropriate examples that could be included midway into one's undergraduate studies, (3) demonstrate how to address successive “failuresy” through progressively stringent safety and liveness requirements, and (4) establish an ongoing framework for assessing interest and relevance among students. Methods: We detail our pedagogical strategy for embedding $\text { TLA }^{+}$ into an intermediate course on formal methods at our institution. After starting with a refresher on mathematical logic, students specify the rules of simple puzzles in $\text { TLA }^{+}$ and use its included model checker (known as TLC) to find a solution. We gradually escalate to more complex, dynamic, event-driven systems, such as the control logic of a microwave oven, where students will study safety and liveness requirements. We subsequently discuss explicit concurrency, along with thread safety and deadlock avoidance, by modeling bounded counters and buffers. Results: Our initial findings suggest that through careful curricular design and choice of examples and tools, it is possible to inspire and cultivate a new generation of software engineers proficient in formal methods. Conclusions: Our initial efforts suggest that 84% of our students had a positive experience in our formal methods course. Our future plans include a longitudi

关键词： computer science Open Access Model checking System recovery Software Safety Logic Reliability Proposals Software engineering

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What Dense Graph Do You Need for Self-Attention?

arXiv

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arXiv 2022年

作者： Wang, Yuxin Lee, Chu-Tak Guo, Qipeng Yin, Zhangyue Zhou, Yunhua Huang, Xuanjing Qiu, Xipeng School of Computer Science Fudan University China Institute of Modern Languages and Linguistics Fudan University China Peng Cheng Laboratory China

Transformers have made progress in miscellaneous tasks, but suffer from quadratic computational and memory complexities. Recent works propose sparse Transformers with attention on sparse graphs to reduce complexity and remain strong performance. While effective, the crucial parts of how dense a graph needs to be to perform well are not fully explored. In this paper, we propose Normalized Information Payload (NIP), a graph scoring function measuring information transfer on graph, which provides an analysis tool for trade-offs between performance and complexity. Guided by this theoretical analysis, we present Hypercube Transformer, a sparse Transformer that models token interactions in a hypercube and shows comparable or even better results with vanilla Transformer while yielding O(N log N) complexity with sequence length N. Experiments on tasks requiring various sequence lengths lay validation for our graph function well. Copyright © 2022, The Authors. All rights reserved.

关键词： Economic and social effects

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VNet: A Versatile Network for Efficient Real-Time Semantic Segmentation

VNet: A Versatile Network for Efficient Real-Time Semantic S...

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IEEE International Conference on computer Design: VLSI in computers and Processors, (ICCD)

作者： Ning Lin Hang Lu Jingliang Gao Shunjie Qiao Xiaowei Li State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences University of Chinese Academy of Sciences Department of Computer Science University of Hong Kong

Many recent excellent methods for efficient real-time semantic segmentation are of low precision and heavily rely on multiple GPUs for training. In this paper, we rethink the critical factors affecting the accuracy of efficient segmentation models. The previous works usually reduce the input resolution prior to training the parameters of models by cropping or resizing the images. On the contrary, our empirical study shows that the reduced images lose the important content information and details, which are vital to the high precision. However, the previous methods are unable to train the original high-resolution images due to the memory-limited GPUs. To tackle this problem, we propose a novel versatile network (VNet), which employs reversible mechanism and asymmetric convolution to achieve highly efficient and extremely low memory consumption in backward propagation. In particular, we keep all the detailed spatial information of the input images without cropping or resizing to pursue decent prediction accuracy. It is worth noting that VNet can train multiple 1024×2048 high-resolution images on only one standard GPU card. Under the same conditions, our model achieves a new state-of-the-art result on Cityscapes datasets. Specifically, it can process the 1024×2048 high-resolution inputs at a rate of 37.4 and 15.5 frames per second (fps) on a standard GPU and an edge device, respectively, with only 0.16 million parameters.

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Accelerating Deep Learning Inference with Cross-Layer Data Reuse on GPUs

arXiv

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arXiv 2020年

作者： Wang, Xueying Li, Guangli Dong, Xiao Li, Jiansong Liu, Lei Feng, Xiaobing State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China School of Computer Science and Technology University of Chinese Academy of Sciences China

Accelerating the deep learning inference is very important for real-time applications. In this paper, we propose a novel method to fuse the layers of convolutional neural networks (CNNs) on Graphics Processing Units (GPUs), which applies data reuse analysis and access optimization in different levels of the memory hierarchy. To achieve the balance between computation and memory access, we explore the fusion opportunities in the CNN computation graph and propose three fusion modes of convolutional neural networks: straight, merge and split. Then, an approach for generating efficient fused code is designed, which goes deeper in multi-level memory usage for cross-layer data reuse. The effectiveness of our method is evaluated with the network layers from state-of-the-art CNNs on two different GPU platforms, NVIDIA TITAN Xp and Tesla P4. The experiments show that the average speedup is 2.02 × on representative structures of CNNs, and 1.57× on end-to-end inference of SqueezeNet. Copyright © 2020, The Authors. All rights reserved.

关键词： Memory architecture

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