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A survey of neural network accelerators

Frontiers of computer science 2017年第5期11卷 746-761页

作者： Zhen LI Yuqing WANG Tian ZHI Tianshi CHEN State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China School of Computer Science and Technology University of Science and Technology of China Hefei 230026 China

Machine-learning techniques have recently been proved to be successful in various domains, especially in emerging commercial applications. As a set of machine- learning techniques, artificial neural networks （ANNs）, requiring considerable amount of computation and memory, are one of the most popular algorithms and have been applied in a broad range of applications such as speech recognition, face identification, natural language processing, ect. Conventionally, as a straightforward way, conventional CPUs and GPUs are energy-inefficient due to their excessive effort for flexibility. According to the aforementioned situation, in recent years, many researchers have proposed a number of neural network accelerators to achieve high performance and low power consumption. Thus, the main purpose of this literature is to briefly review recent related works, as well as the DianNao-family accelerators. In summary, this review can serve as a reference for hardware researchers in the area of neural networks.

关键词： neural networks accelerators FPGAs ASICs,DianNao series

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Trainbow: a new trusted virtual machine based platform

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中国高等学校学术文摘·计算机科学 2010年第1期4卷 47-64页

作者： Yuzhong SUN Yongbing HUANG Yunwei GAO Haifeng FANG Ying SONG Lei DU Kai ZHANG Hongyong ZANG Yaqiong LI Yajun YANG Ran AO Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of SciencesBeijing 100190China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of SciencesBeijing 100190China Graduate University of Chinese Academy of Sciences Beijing 100190China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of SciencesBeijing 100190China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of SciencesBeijing 100190China Graduate University of Chinese Academy of Sciences Beijing 100190China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of SciencesBeijing 100190China Department of Computer Science and Technology Xi'an Jiaotong University Xi'an 710049China Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy of Sciences Beijing 100190China Graduate University of Chinese Academy of Sciences Beijing 100190China

Currently, with the evolution of virtualization technology, cloud computing mode has become more and more popular. However, people still concern the issues of the runtime integrity and data security of cloud computing platform, as well as the service efficiency on such computing platform. At the same time, according to our knowledge, the design theory of the trusted virtual computing environment and its core system software for such network-based computing platform is at the exploratory stage. In this paper, we believe that efficiency and isolation are the two key proprieties of the trusted virtual computing environment. To guarantee these two proprieties, based on the design principle of splitting, customizing, reconstructing, and isolation-based enhancing to the platform, we introduce TRainbow, a novel trusted virtual computing platform developing by our research *** the two creative mechanisms, that is, capacity flowing amongst VMs and VM-based kernel reconstructing, TRainbow provides great improvements (up to 42%) in service performance and isolated reliable computing environment for Internet-oriented, large-scale, concurrent services.

关键词： Computing platform virtual machine capacity service computing trust chain isolation

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Dynamic I/O-Aware Scheduling for Batch-Mode Applications on Chip Multiprocessor Systems of Cluster Platforms

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Journal of computer science & Technology 2014年第1期29卷 21-37页

作者：吕方崔慧敏王蕾刘磊武成岗冯晓兵游本中 State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences University of Chinese Academy of Sciences CCF ACM IEEE Department of Computer Science and Engineering University of Minnesota at Twin Cities Institute of Information Science Academia Sinica

Efficiency of batch processing is becoming increasingly important for many modern commercial service centers, e.g., clusters and cloud computing datacenters. However, periodical resource contentions have become the major performance obstacles for concurrently running applications on mainstream CMP servers. I/O contention is such a kind of obstacle, which may impede both the co-running performance of batch jobs and the system throughput seriously. In this paper, a dynamic I/O-aware scheduling algorithm is proposed to lower the impacts of I/O contention and to enhance the co-running performance in batch processing. We set up our environment on an 8-socket, 64-core server in Dawning Linux Cluster. Fifteen workloads ranging from 8 jobs to 256 jobs are evaluated. Our experimental results show significant improvements on the throughputs of the workloads, which range from 7% to 431%. Meanwhile, noticeable improvements on the slowdown of workloads and the average runtime for each job can be achieved. These results show that a well-tuned dynamic I/O-aware scheduler is beneficial for batch-mode services. It can also enhance the resource utilization via throughput improvement on modern service platforms.

关键词： chip multiprocessor batch processing co-running I/0 contention scheduling

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Constructing Edge-Colored Graph for Heterogeneous Networks

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Journal of computer science & Technology 2015年第5期30卷 1154-1160页

作者：侯睿武继刚陈亚文张海波隋秀峰 School of Computer Science and Software Engineering Tianjin Polytechnic University Tianjin 300387 China State Key Laboratory of Computer Architecture~ Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Department of Computer Science University of Otago Dunedin 9054 New Zealand

In order to build a fault-tolerant network, heterogeneous facilities are arranged in the network to prevent homogeneous faults from causing serious damage. This paper uses edge-colored graph to investigate the features of a network topology which is survivable after a set of homogeneous devices malfunction. We propose an approach to designing such networks under arbitrary parameters. We also show that the proposed approach can be used to optimize inter-router connections in network-on-chip to reduce the additional consum!otion of energy and time delay.

关键词： network reliability homogeneous fault fault tolerance reconfigurable system network-on-chip

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Theoretical Treatment of Target Coverage in Wireless Sensor Networks

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Journal of computer science & Technology 2011年第1期26卷 117-129页

作者：谷雨赵保华计宇生李颉 School of Computer Science University of Science and Technology of China State Key Laboratory of Networking and Switching Technology Information Systems Architecture Science Research Division National Institute of InformaticsTokyoJapan Department of Computer Science University of TsukubaTsukuba Science CityIbarakiJapan

The target coverage is an important yet challenging problem in wireless sensor networks, especially when both coverage and energy constraints should be taken into account. Due to its nonlinear nature, previous studies of this problem have mainly focused on heuristic algorithms; the theoretical bound remains unknown. Moreover, the most popular method used in the previous literature, i.e., discretization of continuous time, has yet to be justified. This paper fills in these gaps with two theoretical results. The first one is a formal justification for the method. We use a simple example to illustrate the procedure of transforming a solution in time domain into a corresponding solution in the pattern domain with the same network lifetime and obtain two key observations. After that, we formally prove these two observations and use them as the basis to justify the method. The second result is an algorithm that can guarantee the network lifetime to be at least （1 - ε） of the optimal network lifetime, where ε can be made arbitrarily small depending on the required precision. The algorithm is based on the column generation （CG） theory, which decomposes the original problem into two sub-problems and iteratively solves them in a way that approaches the optimal solution. Moreover, we developed several constructive approaches to further optimize the algorithm. Numerical results verify the efficiency of our CG-based algorithm.

关键词： target coverage wireless sensor networks time-dependent solution pattern-based solution column generation

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Memory Efficient Two-Pass 3D FFT Algorithm for Intel~ Xeon Phi^(TM) Coprocessor

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Journal of computer science & Technology 2014年第6期29卷 989-1002页

作者：刘益群李焱张云泉张先轶 Institute of Software Chinese Academy of Sciences University of Chinese Academy of Sciences Department of Computer Science and Technology Tsinghua University CCF ACM IEEE State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences

Equipped with 512-bit wide SIMD inst d large numbers of computing cores, the emerging x86-based Intel（R） Many Integrated Core （MIC） architecture ot only high floating-point performance, but also substantial off-chip memory bandwidth. The 3D FFT （three-di fast Fourier transform） is a widely-studied algorithm; however, the conventional algorithm needs to traverse the three times. In each pass, it computes multiple 1D FFTs along one of three dimensions, giving rise to plenty of rided memory accesses. In this paper, we propose a two-pass 3D FFT algorithm, which mainly aims to reduce of explicit data transfer between the memory and the on-chip cache. The main idea is to split one dimension into ensions, and then combine the transform along each sub-dimension with one of the rest dimensions respectively erence in amount of TLB misses resulting from decomposition along different dimensions is analyzed in detail. el parallelism is leveraged on the many-core system for a high degree of parallelism and better data reuse of loc On top of this, a number of optimization techniques, such as memory padding, loop transformation and vectoriz employed in our implementation to further enhance the performance. We evaluate the algorithm on the Intel（R） PhiTM coprocessor 7110P, and achieve a maximum performance of 136 Gflops with 240 threads in offload mode, which ts the vendor-specific Intel（R）MKL library by a factor of up to 2.22X.

关键词： 3D-FFT memory efficie many-core Many Integrated Core Intel（R） Xeon PhiTM

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A Hybrid Circular Queue Method for Iterative Stencil Computations on GPUs

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Journal of computer science & Technology 2012年第1期27卷 57-74页

作者： Yang Yang Hui-Min Cui Xiao-Bing Feng Jing-Ling Xue State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences Beijing 100190China Graduate University of Chinese Academy of Sciences Beijing 100190China Programming Languages and Compilers Group School of Computer Science and Engineering University of New South WalesSydneyNSW 2052Australia

In this paper, we present a hybrid circular queue method that can significantly boost the performance of stencil computations on GPU by carefully balancing usage of registers and shared-memory. Unlike earlier methods that rely on circular queues predominantly implemented using indirectly addressable shared memory, our hybrid method exploits a new reuse pattern spanning across the multiple time steps in stencil computations so that circular queues can be implemented by both shared memory and registers effectively in a balanced manner. We describe a framework that automatically finds the best placement of data in registers and shared memory in order to maximize the performance of stencil computations. Validation using four different types of stencils on three different GPU platforms shows that our hybrid method achieves speedups up to 2.93X over methods that use circular queues implemented with shared-memory only.

关键词： stencil computation circular queue GPU occupancy register

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Efficient Algorithm for Energy-Aware Virtual Network Embedding

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Tsinghua science and Technology 2016年第4期21卷 407-414页

作者： Shuxian Jia Guiyuan Jiang Peilan He Jigang Wu School of Computer Software Technology Zhejiang University Ningbo 315048 China School of Computer Science and Engineering Nanyang Technological University 639798 Singapore State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China

Network virtualization is a promising approach for resource management that allows customized Virtual Networks （VNs） to be multiplexed on a shared physical infrastructure. A key function that network virtualization can provide is Virtual Network Embedding （VNE）, which maps virtual networks requested by users to a shared substrate network maintained by an Internet service provider. Existing research has worked on this, but has primarily focused on maximizing the revenue of the Internet service provider. In this paper, we consider energy-aware virtual network embedding, which aims at minimizing the energy consumption for embedding virtual networks in a substrate network. In our optimization model, we consider energy consumption of both links and nodes. We propose an efficient heuristic to assign virtual nodes to appropriate substrate nodes based on priority, where existing activated nodes have higher priority for hosting newly arrived virtual nodes. In addition, our proposed algorithm can take advantage of activated links for embedding virtual links so as to minimize total energy consumption. The simulation results show that, for all the cases considered, our algorithm can improve upon previous work by an average of 12.6% on acceptance rate, while the consumed energy can be reduced by 12.34% on average.

关键词： virtualization technology virtual network embedding energy efficient optimization algorithm

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STATIC FILTERING ON STRATIFIED PROGRAMS

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INFORMATION PROCESSING LETTERS 1993年第5期47卷 237-244页

作者： CHANG, BM CHOE, KM HAN, TS Programming Languages Laboratory Department of Computer Science Korea Advanced Institute of Science and Technology 373-1 Kusong-dong Yusung-ku Taejon 305-701 South Korea

We extend static filtering in [8], a query optimization strategy based on seminaive evaluation on system graphs, so that it can efficiently handle stratified programs without extra overhead. The computation of static filters is formalized as a transformation so that the least fixed point of the transformation can be the static filters. The static filtering on stratified programs is shown to be complete with respect to the iterated fixed point semantics.

关键词： APPLICATIVE (LOGIC) PROGRAMMING STRATIFIED PROGRAMS QUERY OPTIMIZATION STATIC FILTERING SYSTEM GRAPHS

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SYNTACTIC ERROR REPAIR USING REPAIR PATTERNS

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INFORMATION PROCESSING LETTERS 1993年第4期47卷 189-196页

作者： YUN, IS CHOE, KM HAN, T Programming Languages Laboratory Department of Computer Science Korea Advanced Institute of Science and Technology 373-1 Kusong-Dong Yusung-Cu Taejon 305-701 South Korea

A syntactic error repair model is proposed, and is defined as a partial function from strings to sentences. The replacement of a substring of a string with a substring of a sentence is described by a repair pattern, which is roughly a pair of strings of grammar symbols. The model can be efficient with some restriction on repair patterns. An LR-based implementation of the model is discussed.

关键词： COMPILERS SYNTACTIC ERROR RECOVERY SYNTACTIC ERROR REPAIR MODEL REPAIR PATTERN

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