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作者： Fu, Xiang Li, Huawei Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academic of Science Beijing 100190 China Graduate University of Chinese Academic of Sciences Beijing 100039 China

Critical path selection is very important in delay testing. Critical paths found by conventional static timing analysis (STA) tools are inadequate to represent the real timing of the circuit, since neither the testability of paths nor the statistical variation of cell delays caused by process variation is considered. This paper proposed a novel path selection method considering process variation. The circuit is firstly simplified by eliminating non-critical edges under statistical timing model, and then divided into sub-circuits, while each sub-circuit has only one prime input (PI) and one prime output (PO). Critical paths are selected only in critical sub-circuits. The concept of partially critical edges (PCEs) and completely critical edges (CCEs) are introduced to speed up the path selection procedure. Two path selection strategies are also presented to search for a testable critical path set to cover all the critical edges. The experimental results showed that the proposed circuit division approach is efficient in path number reduction, and PCEs and CCEs play an important role as a guideline during path selection. Copyright © 2010 The institute of Electronics.

关键词： Delay circuits

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Formula-Oriented Compositional Minimization in Model Checking

Formula-Oriented Compositional Minimization in Model Checkin...

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2010 19th IEEE Asian Test Symposium(第19届IEEE亚洲测试技术学术会议 ATS 2010)

作者： Bowen Chen Haihua Shen Wenhui Zhang Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acade Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acade State Key Laboratory of Computer Science Institute of Software Chinese Academy of Sciences Beijin

This paper presents a new approach to reduce finite state machines with respect to a CTL formula to alleviate state explosion problem. Reduction is achieved by removing parts useless to the formula of original machines. The main contribution of this paper is to exploit relations among subformulas of the CTL formula so as to gain more reduction, as well as to extend traditional pruning method, which handles only existential formulas, to handle universal formulas. Based on this kind of reduction, verification of a large system, which usually consists of several components, can be done by evaluating properties on a reduced version of the system, which is built by composing components of the system one by one while doing reduction after each composition. Experimental results show the effectiveness of the approach. Especially when a property is written in a more detailed way, that is to describe the system part by part, the approach has a great potential.

关键词： Formula-Oriented Compositional Minimization CTL Model Checking Formal Verification

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Performance-asymmetry-aware topology virtualization for defect-tolerant NoC-based many-core processors 10

Performance-asymmetry-aware topology virtualization for defe...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Lei Zhang Yue Yu Jianbo Dong Yinhe Han Shangping Ren Xiaowei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences China Department of Computer Science Illinois Institute of Technology USA

ISBN: (纸本)9783981080162

Topology virtualization techniques are proposed for NoC-based many-core processors with core-level redundancy to isolate hardware changes caused by on-chip defective cores. Prior work focuses on homogeneous cores with symmetric performance and optimizes on-chip communication only. However, core-to-core performance asymmetry due to manufacturing process variations poses new challenges for constructing virtual topologies. Lower performance cores may scatter over a virtual topology, while operating systems typically allocate tasks to continuous cores. As a result, parallel applications are probably assigned to a region containing many slower cores that become bottlenecks. To tackle the above problem, in this paper we present a novel performance-asymmetry-aware reconfiguration algorithm Bubble-Up based on a new metric called core fragmentation factor (CFF). Bubble-Up can arrange cores with similar performance closer, yet maintaining reasonable hop distances between virtual neighbors, thus accelerating applications with higher degree of parallelism, without changing existing allocation strategies for OS. Experimental results show its effectiveness.

关键词： Network topology Network-on-a-chip Programming profession Hardware System-on-a-chip Manufacturing processes Scattering Operating systems Parallel processing Throughput

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Outlier Detection for Learning-Based Optimizing Compiler

Outlier Detection for Learning-Based Optimizing Compiler

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Japan-China Joint Workshop on Frontier of computer science and Technology (FCST)

作者： Shun Long Weiheng Zhu Department of Computer Science Jinan University Guangzhou China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences China

Modern compilers use machine learning to find from their prior experience useful heuristics for new programs encountered in order to accelerate the optimization process. However, prior experience might not be applicable for outlier programs with unfamiliar code features. This paper presents a Reverse K-nearest neighbor (RKNN) algorithm based approach for outlier detection. The compiler can therefore launch a search within an optimization space when outlier programs are encountered, or directly apply its experience to non-outliers. Preliminary experimental results demonstrate the effectiveness of the approach.

关键词： Optimization Program processors Training Kernel Benchmark testing Arrays Nearest neighbor searches

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DCMTs: Supporting Dynamically Created Migratory Threads

DCMTs: Supporting Dynamically Created Migratory Threads

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IEEE International Conference on Computational science and Engineering, CSE

作者： Yueting Zhu Wu Zhang Hai Jiang Yu Lei Junjie Peng Department of Computer Science and Engineering Shanghai University Shanghai China Department of Computer Science and Engineering University of Technology Arlington TX USA Department of Computer Science Arkansas State University Jonesboro AR USA Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences China

Thread migration is an effective technique for fault resilience and load balancing in high performance computing. However, flexible thread migration is not easy to achieve. In this paper, we present an approach to creating migratory threads dynamically at application level. The targets must be executable source files. Compared to the static ones, the number of threads created during migration with the new scheme is independent from the context. Various thread cases are considered for migration. Thread state is handled at application level. Variables are saved in structures in C language for speedy state construction. In order to solve the inability of traditional methods in tracking the created threads, a tree of active function calls is used to record the callback. The preprocessor of the proposed one is written in YACC for accuracy and programmability. The migration enabling process is transparent to programmers with the help of the preprocess. The experimental results have demonstrated the effectiveness of this approach.

关键词： Instruction sets Switches computer science Electronic mail Data preprocessing Flexible printed circuits

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Pricing of multi-energy network flow

Pricing of multi-energy network flow

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2010 IEEE International Energy Conference and Exhibition, EnergyCon 2010

作者： Schulze, Matthias Gasparovic, Goran Lee, Jieun High Voltage Laboratory Swiss Federal Institute of Technology Zurich Physikstrasse 3 8092 Zurich Switzerland Faculty of Electrical Engineering Mechanical Engineering and Naval Architecture University of Split R. Bokovia b. b. 21000 Split Croatia Dept. of Computer Science Korea Advanced Institute of Science and Technology Guseong-dong Yuseong-gu Daejeon 305-701 Korea Republic of

ISBN: (纸本)9781424493807

The network model bases upon the energy hub concept, which was developed by the Vision of Future Energy Networks (VoFEN) research group at ETH Zurich in the last years. Keynote of the concept is a combined optimization of different energy carrier. Synergetic effects are expected to give unusual optimization results, when allowing any possible energy conversion inside a specific area that constitute the hub. Costs for the energy consumption or production are generally used as the optimization criteria. Any technologies for conversion and storage are integrated in a coupling matrix, which links input and output. This paper deals with an extension to the optimization part by merging the network flows with the pricing of grid costs. The impact of network flow pricing is at first derived from theory, then translated into the energy hub concept and finally illustrated in an example. © 2010 IEEE.

关键词： Costs

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Senior-friendly technologies: Interaction design for senior users

Senior-friendly technologies: Interaction design for senior ...

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28th Annual CHI Conference on Human Factors in Computing Systems, CHI 2010

作者： Duh, Henry Been-Lirn Do, Ellen Yi-Luen Billinghurst, Mark Quek, Francis Chen, Vivian Hsueh-Hua National University of Singapore Department of Electrical and Computer Engineering 4 Engineering Drive 3 Singapore 117576 Singapore Georgia Institute of Technology College of Architecture School of Interactive Computing 245 Fourth Street Atlanta GA 30332-0155 United States University of Canterbury Human Interface Laboratory Old Maths Building New Zealand Virginnia Tech. Department of Computer Science Center for Human Computer Interaction Blacksburg VA 24061 United States Nanyang Technological University Wee Kim Wee School of Communication and Information 31 Nanyang Link Singapore 637718 Singapore

ISBN: (纸本)9781605589312

The elderly represent a valid group of users who can potentially benefit greatly from engaging with technology, such as healthcare systems or playing digital games. Yet, less attention has been given to the significance of senior citizens as technology users, as compared to the common younger population. In an effort to fill in the gap, this workshop aims to investigate the design of technology for senior citizens. To provide for more focused, thus more productive discussion, we will use elderly mobile phone games as a case in point here. The overarching objective is to understand what can help to make for better and more meaningful use of interactive applications and technology by the elderly, for instance, games on the mobile phone. © 2010 Copyright is held by the author/owner(s).

关键词： Cellular telephones

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Pricing of multi-energy network flow

Pricing of multi-energy network flow

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IEEE International Energy Conference and Exhibition (EnergyCon)

作者： Matthias Schulze Goran Gašparović Jieun Lee High Voltage Laboratory Swiss Federal Institute of Technology Zurich Switzerland Faculty of Electrical Engineering and Naval Architecture Mechanical Engineering University of Split Split Croatia Department of Computer Science Korea Advanced Institute of Science and Technology Daejeon South Korea

The network model bases upon the energy hub concept, which was developed by the Vision of Future Energy Networks” (VoFEN) research group at ETH Zurich in the last years. Keynote of the concept is a combined optimization of different energy carrier. Synergetic effects are expected to give unusual optimization results, when allowing any possible energy conversion inside a specific area that constitute the hub. Costs for the energy consumption or production are generally used as the optimization criteria. Any technologies for conversion and storage are integrated in a coupling matrix, which links input and output. This paper deals with an extension to the optimization part by merging the network flows with the pricing of grid costs. The impact of network flow pricing is at first derived from theory, then translated into the energy hub concept and finally illustrated in an example.

关键词： Electricity Optimization Resistance heating Mathematical model Smart grids Equations

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PARBLO:Page-Allocation-Based DRAM Row Buffer Locality Optimization

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Journal of computer science & Technology 2009年第6期24卷 1086-1097页

作者：米伟冯晓兵贾耀仓陈莉薛京灵 Key Laboratory of Computer System and Architecture Institution of Computing Technology Chinese Academy of Sciences Graduate University of Chinese Academy of Sciences Programming Languages and Compilers Group School of Computer Science and Engineering University of New South Wales

DRAM row buffer conflicts can increase memory access latency significantly. This paper presents a new pageallocation-based optimization that works seamlessly together with some existing hardware and software optimizations to eliminate significantly more row buffer conflicts. Validation in simulation using a set of selected scientific and engineering benchmarks against a few representative memory controller optimizations shows that our method can reduce row buffer miss rates by up to 76% （with an average of 37.4%）. This reduction in row buffer miss rates will be translated into performance speedups by up to 15% （with an average of 5%）.

关键词： DRAM row buffer page allocation locality optimization

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A parallel algorithm for computing betweenness centrality

A parallel algorithm for computing betweenness centrality

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38th International Conference on Parallel Processing, ICPP-2009

作者： Tan, Guangming Tu, Dengbiao Sun, Ninghui Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Science Beijing China

ISBN: (纸本)9780769538020

In this paper we present a multi-grained parallel algorithm for computing betweenness centrality, which is extensively used in large-scale network analysis. Our method is based on a novel algorithmic handling of access conflicts for a CREW PRAM algorithm. We propose a proper data-processor mapping, a novel edge-numbering strategy and a new triple array data structure recording the shortest path for eliminating conflicts to access the shared memory. The algorithm requires O(n + m) space and O(nm/p ) ( or O(nm+n2logn /p )) time for unweighted (or weighted) graphs, and it is a work-optimal CREW PRAM algorithm. On current multi-core platforms, our algorithm outperforms the previous algorithm by 2-3 times. © 2009 IEEE.

关键词： Parallel algorithms

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