A new variant of 5-round distinguisher of meet-in-the-middle attack on AES was constructed by exploiting the properties of the round transform of AES. Based on the variant of distinguisher, meet-in-the-middle attacks ...
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A new variant of 5-round distinguisher of meet-in-the-middle attack on AES was constructed by exploiting the properties of the round transform of AES. Based on the variant of distinguisher, meet-in-the-middle attacks on 7-round AES-192 and 8-round AES-256 were presented by using the time-memory tradeoff approach. It is shown that the new results are better than the cryptanalytic results presented at FSE2008 on reduced AES in terms of the time complexity and the memory complexity.
Ring is a promising on-chip interconnection for CMP. It is more scalable than bus and much simpler than packet-switched networks. The ordering property of ring can be used to optimize cache coherence protocol design. ...
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This paper presents differential evolution with self-adaptation and local search for constrained multiobjective optimization algorithm (DECMOSA-SQP), which uses the self-adaptation mechanism from DEMOwSA algorithm pre...
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This paper presents differential evolution with self-adaptation and local search for constrained multiobjective optimization algorithm (DECMOSA-SQP), which uses the self-adaptation mechanism from DEMOwSA algorithm presented at CEC 2007 and a SQP local search. The constrained handling mechanism is also incorporated in the new algorithm. Assessment of the algorithm using CEC 2009 special session and competition on constrained multiobjective optimization test functions is presented. The functions are composed of unconstrained and constrained problems. Their results are assessed using the IGD metric. Based on this metric, algorithm strengths and weaknesses are discussed.
With the universal test machine and temperature test chamber, the effect of pressure and temperature on the behavior of 1-3 and 1-3-2 piezocomposites prepared with PZT/epoxy in our lab has been investigated through el...
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With the universal test machine and temperature test chamber, the effect of pressure and temperature on the behavior of 1-3 and 1-3-2 piezocomposites prepared with PZT/epoxy in our lab has been investigated through electrical impedance and dielectric analysis. The permittivity, resonant frequency and dielectric loss of the composites have been measured under vertical stress and temperature, and the variety of the material properties under pressure and temperature could also be obtained. The pressure and temperature stability of the composites have been assessed through experiments. The data of these two types of composites indicated that the stability of 1-342 composite with pressure was better than that of 1-3 composite, and two composites have almost the same dielectric stability with temperature. However, 1-3-2 composite showed slower frequency variation than 1-3 composite.
With increasing defect density, microprocessors, especially the embedded caches, will encounter more faults. Adding spare resources to replace defective components is a widely accepted method for yield enhancement. In...
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The domain knowledge has a direct impact on the result of question - answering (Q & A) in the restricted domain Question Answering System (QA). In this paper, a method of answer extraction for domain Chinese quest...
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The fast evolutionary programming (FEP) introduced the Cauchy distribution into its mutation operator, thus the performances of EP were promoted significantly on a number of benchmark problems. However, the scaling pa...
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The fast evolutionary programming (FEP) introduced the Cauchy distribution into its mutation operator, thus the performances of EP were promoted significantly on a number of benchmark problems. However, the scaling parameter of the Cauchy mutation is invariable, which has become an obstacle for FEP to reach better performance. This paper proposes and analyzes a new stochastic method for controlling the variable scaling parameters of Cauchy mutation. This stochastic method collects information from a group of individuals randomly selected from the population. Empirical evidence validates our method to be very helpful in promoting the performance of FEP.
When a concurrent shared-memory program written with a sequential consistency (SC) model is run on a machine implemented with a relaxed consistency (RC) model, it could cause SC violations that are very hard to debug....
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ISBN:
(纸本)9780769535760
When a concurrent shared-memory program written with a sequential consistency (SC) model is run on a machine implemented with a relaxed consistency (RC) model, it could cause SC violations that are very hard to debug. To avoid such violations, programmers need to provide explicit synchronizations or insert fence instructions. In this paper, we propose a scheme to detect and eliminate potential SC violations by combining Shasha/Snir's conflict graph and delay set theory with existing data race detection techniques. For each execution, we generate a race graph, which contains the improperly synchronized conflict accesses, called race accesses, and race cycles formed with those accesses. As a race cycle would probably lead to a non-sequential-consistent execution, we call it a potential violation of sequential consistency (PVSC) bug. We then compute the race delays of race cycles, and suggest programmers to insert fences into source code to eliminate PVSC bugs. We further convert a race graph into a PC race graph, and improves cycle detection and race delay computation to O(n 2 ), where n is the number of race access instructions. We evaluate our approach with the SPLASH-2 benchmarks, two large real-world applications (MySQL and Apache), and several multi-threaded Cilk programs. The results show that (1) the proposed approach could effec-tively detect PVSC bugs in real-world applications with good scalability; (2) it retains most of the performance of the concurrent program after inserting required fence instructions, with less than 6.3% performance loss; and (3) the additional cost of our approach over traditional race detection techniques is quite low, with 3.3% on average.
With the wide application of EDA technique, the period for the development of electronic products has been shortened. That implements the software of the hardware design and reduces the costs. Based on the analysis of...
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With the wide application of EDA technique, the period for the development of electronic products has been shortened. That implements the software of the hardware design and reduces the costs. Based on the analysis of the principle of digital logic analyzer circuit, this paper discusses the working principles of its flip-flop circuit module and the implementation method of FPGA, and presents the program design and emulation result of part circuits.
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