With increasing defect density, microprocessors, especially the embedded caches, will encounter more faults. Adding spare resources to replace defective components is a widely accepted method for yield enhancement. In...
With increasing defect density, microprocessors, especially the embedded caches, will encounter more faults. Adding spare resources to replace defective components is a widely accepted method for yield enhancement. In this work, a repair method using content addressable memory combined with spare bits, as well as a novel fault injection method is proposed. With the proposed fault injection technique, various numbers and types of faults can be flexibly injected into the silicon. A wireless sensor network system using our self-repairable microprocessor (SRP) is developed to prove the effectiveness of the proposed technique.
Microprocessors have turned to multicore, i.e. multiple processor cores, along with some levels of on-chip caches and interconnection networks, integrated on a singe chip. However, it brings challenges on how to progr...
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The amount of die area consumed by scan chains and scan control circuit can range from 15%∼30%, and scan chain failures account for almost 50% of chip failures. As the conventional diagnosis process usually runs on t...
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CAM is widely used in microprocessors and SOC TLB modules. It gives great advantage for software development. And TLB operations become bottleneck of the microprocessor performance. The test cost of normal BIST approa...
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Data availability is a challenging issue for large- scale cluster file systems built upon thousands of individual storage devices. Replication is a well-known solution used to improve data availability. However, how t...
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Data availability is a challenging issue for large- scale cluster file systems built upon thousands of individual storage devices. Replication is a well-known solution used to improve data availability. However, how to efficiently guarantee replicas consistency under concurrent conflict mutations remains a challenge. Moreover, how to quickly recover replica consistency from a storage server crash or storage device failure is also a tough problem. In this paper, we present a replication-based data availability mechanism designed for a large-scale cluster file system prototype named LionFS. Unlike other replicated storage systems that serialize replica updates, LionFS introduces a relaxed consistency model to enable concurrent updating all replicas for a mutation operation, greatly reducing the latency of operations. LionFS ensures replica consistency if applications use file locks to synchronize the concurrent conflict mutations. Another novelty of this mechanism is its light-weight log, which only records failed mutations and imposes no overhead on failure-free execution and low overhead when some storage devices are unavailable. Furthermore, recovery of replica consistency needs not stop the file system services and running applications. Performance evaluation shows that our solution achieves 50-70% higher write performance than serial replica updates. The logging overhead is shown to be low, and the recovery time is proportional to the amount of data written during the failure.
Network on chip (NoC) has become an active research area for high performance computer. Based on round-robin scheduling algorithm, we present three new scheduling algorithms for FIFO input queue (IQ) switches of netwo...
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Network on chip (NoC) has become an active research area for high performance computer. Based on round-robin scheduling algorithm, we present three new scheduling algorithms for FIFO input queue (IQ) switches of network on chip, which are called rr-path, rr-dist and rr-al respectively, rr-path schedules the NoC traffic according to the distance between the source node and the destination node, and rr-dist schedules the NoC traffic according to the distance between the current and the destination nodes, and rr-al schedules the NoC traffic according to the difference between the arrival and the left flits numbers of every ports. We implement these algorithms in a network simulator, and analyze their performance using hotspot and uniform traffic patterns. Compared to round-robin scheduling algorithm, all of the new algorithms can reduce the max communication latency. In most cases, they can also reduce the average communication latency. Consequently, these new algorithms can improve the performance of multiprocessor systems.
Power consumption in scan-based testing is a major concern nowadays. In this paper, we present a new X-filling technique to reduce both shift power and capture power during scan tests, namely LSC-filling. The basic id...
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Conventional random access scan (RAS) designs, although economic in test power dissipation, test application time and test data volume, are expensive in area and routing overhead. In this paper, we present a localized...
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ISBN:
(纸本)9781424419210
Conventional random access scan (RAS) designs, although economic in test power dissipation, test application time and test data volume, are expensive in area and routing overhead. In this paper, we present a localized RAS architecture (LRAS) to address this issue. A novel scan cell structure, which has fewer transistors than the multiplexer-type scan cell, is proposed to eliminate the global test enable signal and to localize the row enable and the column enable signals. Experimental results on ISCAS'89 and ITC'99 benchmark circuits demonstrate that LRAS has 54% less area overhead than multiplexer-type scan chain based designs, while significantly outperforms the state-of-the-art RAS scheme in routing overhead.
Multiplication operations are the normal operations in operating systems or scientific calculations. Multipliers embedded in processors, DSP or SoC are well optimized for best performance, and they are sensitive to te...
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This paper is concerned with prototype development and motion control of a dolphin-like underwater robot. The propulsion and maneuvering of the robotic dolphin are realized with the flapping motion of the mechanical f...
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This paper is concerned with prototype development and motion control of a dolphin-like underwater robot. The propulsion and maneuvering of the robotic dolphin are realized with the flapping motion of the mechanical flippers and the combined heaving and pitching motions of the fluke. Mechanical design and control of the flipper apparatus and the flexible tail mechanism are presented. Through coordinated control of the propulsors, several swimming movements are designed. Preliminary experimental results verify the effectiveness of the proposed design scheme.
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