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7th International Conference on Embedded and Multimedia Computing, EMC 2012

作者： Ma, Yue Sang, Nan Jiang, Wei Zhang, Lei School of Computer Science and Engineering University of Electronic Science and Technology of China Chengdu China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

ISBN: (纸本)9789400750753

Security has become an important characteristic for many real-time systems. Due to the lack of enough and stable energy supply in battery-powered embedded systems, one of the foremost challenges is the mismatch between energy and performance requirements of security processing. In this paper, we propose a security-aware and energy-efficient scheduling algorithm that aims at reducing energy consumption while ensuring the real-time and security requirements. Based on the feedback control theory, we employ a feedback unit to keep track of the CPU utilization and manage the security level dynamically. Simulation results show the effectiveness and efficiency of the proposed algorithm. © 2012 Springer science+Business Media.

关键词： Feedback control

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I/O lower bounds for auto-tuning of convolutions in CNNs 21

I/O lower bounds for auto-tuning of convolutions in CNNs

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26th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPoPP 2021

作者： Zhang, Xiaoyang Xiao, Junmin Tan, Guangming State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences University of Chinese Academy of Science China

ISBN: (纸本)9781450382946

Convolution is the most time-consuming part in the computation of convolutional neural networks (CNNs), which have achieved great successes in numerous practical applications. Due to the complex data dependency and the increase in the amount of model samples, the convolution suffers from high overhead on data movement (i.e., memory access). This work provides comprehensive analysis and methodologies to minimize the communication for the convolution in CNNs. With an in-depth analysis of the recent I/O complexity theory under the red-blue game model, we develop a general I/O lower bound theory for a composite algorithm which consists of several different sub-computations. Based on the proposed theory, we establish the data movement lower bound results for two main convolution algorithms in CNNs, namely the direct convolution and Winograd algorithm, which represents the direct and indirect implementations of a convolution respectively. Next, derived from I/O lower bound results, we design the near I/O-optimal dataflow strategies for the two main convolution algorithms by fully exploiting the data reuse. Furthermore, in order to push the envelope of performance of the near I/O-optimal dataflow strategies further, an aggressive design of auto-tuning based on I/O lower bounds, is proposed to search an optimal parameter configuration for the direct convolution and Winograd algorithm on GPU, such as the number of threads and the size of shared memory used in each thread block. Finally, experiment evaluation results on the direct convolution and Winograd algorithm show that our dataflow strategies with the auto-tuning approach can achieve about 3.32× performance speedup on average over cuDNN. In addition, compared with TVM, which represents the state-of-the-art technique for auto-tuning, not only our auto-tuning method based on I/O lower bounds can find the optimal parameter configuration faster, but also our solution has higher performance than the optimal solution provided

关键词： Convolution

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Pedestrian wind flow prediction using spatial-frequency generative adversarial network

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Building Simulation 2024年第2期17卷 319-334页

作者： Pengyue Wang Maozu Guo Yingeng Cao Shimeng Hao Xiaoping Zhou Lingling Zhao School of Architecture and Urban Planning Beijing University of Civil Engineering and ArchitectureBeijing100044China Beijing Key Laboratory of Intelligent Processing for Building Big Data Beijing100044China School of Electrical and Information Engineering Beijing University of Civil Engineering and ArchitectureBeijing100044China School of Computer Science and Technology Harbin Institute of TechnologyHarbin150001China

Pedestrian wind flow is a critical factor in designing livable residential environments under growing complex urban *** pedestrian wind flow during the early design stages is essential but currently suffers from inefficiencies in numerical *** learning,particularly generative adversarial networks(GAN),has been increasingly adopted as an alternative method to provide efficient prediction of pedestrian wind ***,existing GAN-based wind flow prediction schemes have limitations due to the lack of considering the spatial and frequency characteristics of wind flow *** study proposes a novel approach termed SFGAN,which embeds spatial and frequency characteristics to enhance pedestrian wind flow *** the spatial domain,Gaussian blur is employed to decompose wind flow into components containing wind speed and distinguished flow edges,which are used as the embedded spatial *** information of wind flow is obtained through discrete wavelet transformation and used as the embedded frequency *** spatial and frequency characteristics of wind flow are jointly utilized to enforce consistency between the predicted wind flow and ground truth during the training phase,thereby leading to enhanced *** results demonstrate that SFGAN clearly improves wind flow prediction,reducing Wind_MAE,Wind_RMSE and the Fréchet Inception Distance(FID)score by 5.35%,6.52%and 12.30%,compared to the previous best method,*** also analyze the effectiveness of incorporating the spatial and frequency characteristics of wind flow in predicting pedestrian wind *** reduces errors in predicting wind flow at large error intervals and performs well in wake regions and regions surrounding *** enhanced predictions provide a better understanding of performance variability,bringing insights at the early design stage to improve pedestrian wind *** proposed spatial-frequen

关键词： pedestrian wind flow prediction generative adversarial network Gaussian kernel wavelet transform objective function

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Design automation methodology from RTL to gate-level netlist and schematic for RSFQ logic circuits 20

Design automation methodology from RTL to gate-level netlist...

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30th Great Lakes Symposium on VLSI, GLSVLSI 2020

作者： Fu, Rongliang Zhang, Zhi-Min Tang, Guang-Ming Huang, Junying Ye, Xiao-Chun Fan, Dong-Rui Sun, Ning-Hui State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China School of Computer Science and Technology University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781450379441

The superconducting rapid single flux quantum (RSFQ) logic circuit has the characteristics of high speed and low power consumption, making it an attractive candidate for future supercomputers. However, computer-aided design (CAD) tools for CMOS cannot be directly applied to RSFQ logic due to their distinct properties. For instance, the RSFQ logic gate can work properly when all its fan-ins have the same logic level. This paper presents the design flow from RTL to RSFQ logic netlist and schematic. First, we implement logic synthesis for RSFQ logic circuits. It achieves path balancing while minimizing the number of DFFs. In addition, we propose an automatic schematic generator for the RSFQ logic circuits. It converts the synthesized netlist into its equivalent schematic. A layer assignment algorithm is proposed, which makes all gates layered in the order of the clock arrival time. Experimental results with ISCAS85 and EPFL benchmarks along with some Kogge-Stone adders have shown a 29.2% reduction in the number of DFFs over the breadth-first first search;moreover, 59.57% and 5.3% decrease in the number of layers of the schematic and number of edge crossings over the ELK tool. © 2020 Association for Computing Machinery.

关键词： Logic circuits

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Statistical static timing analysis for circuit aging prediction

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The Journal of China Universities of Posts and Telecommunications 2021年第2期28卷 14-23页

作者： Duan Shengyu Zhai Dongyao Lu Yue Shanghai Engineering Research Center of Intelligent Computing System Shanghai UniversityShanghai 200444China State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of SciencesBeijing 100190China School of Electronics and Computer Science University of SouthamptonSouthamptonUK

Complementary metal oxide semiconductor(CMOS)aging mechanisms including bias temperature instability(BTI)pose growing concerns about circuit *** results in threshold voltage increases on CMOS transistors,causing delay shifts and timing violations on logic *** amount of degradation is dependent on the circuit workload,which increases the challenge for accurate BTI aging prediction at the design *** this paper,a BTI prediction method for logic circuits based on statistical static timing analysis(SSTA)is proposed,especially considering the correlation between circuit workload and BTI *** consists of a training phase,to discover the relationship between circuit scale and the required workload samples,and a prediction phase,to present the degradations under different workloads in Gaussian probability *** method can predict the distribution of degradations with negligible errors,and identify 50%more BTI-critical paths in an affordable time,compared with conventional methods.

关键词： bias temperature instability(BTI) reliability prediction statistical static timing analysis(SSTA)

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HDCat: Effectively identifying hot data in large-Scale I/O streams with enhanced temporal locality 15th

HDCat: Effectively identifying hot data in large-Scale I/O s...

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15th International Conference on Algorithms and architectures for Parallel Processing, ICA3PP 2015

作者： Chen, Jiahao Deng, Yuhui Huang, Zhan Department of Computer Science Jinan University Guangzhou510632 China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing100190 China

ISBN: (纸本)9783319271217

Hot data is very important for optimizing modern computer systems. For example, the identified hot data can be employed to extend the lifespan of flash memory. However, it is very challenging to effectively identify hot data with low memory consumption and low runtime overhead. This paper proposes a Hot Data Catcher (HDCat) which can effectively identify hot data in large-scale I/O streams by leveraging enhanced temporal locality. HDCat only maintains a hot data queue and a candidate hot data queue to record the data access pattern by tracking limited data set, thus effectively reducing the memory consumption. Furthermore, HDCat adopts a D-bit counter and a recency-bit to leverage both the frequency and recency contained in the data stream. Additionally, HDCat can significantly reduce the conversion between hot data and cold data. Real traces are used to evaluate the proposed approach. Experimental results demonstrate that HDCat significantly outperforms the state-of-the-art Multi-hash algorithm and the two-level LRU algorithm. © Springer International Publishing Switzerland 2015.

关键词： Hash functions

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Designing a power-aware replication strategy for storage clusters

Designing a power-aware replication strategy for storage clu...

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2013 IEEE International Conference on Green Computing and Communications and IEEE Internet of Things and IEEE Cyber, Physical and Social Computing, GreenCom-iThings-CPSCom 2013

作者： Zhang, Lingwei Deng, Yuhui Department of Computer Science Jinan University Guangzhou 510632 China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China

ISBN: (纸本)9780769550466

The exponential data growth is presenting challenges to traditional storage systems. Component-based cluster storage systems, due to their high scalability, are becoming the architecture of next generation storage systems. Cluster storage systems often use data replication to ensure high availability, fault tolerance, and load balance. However, this kind of data replication not only consumes a large amount of storage resources, but also generates more energy consumption. This paper presents a power-aware data replication strategy by leveraging data access behavior. This strategy uses 80/20 rule (80% of the data accesses often go to 20% of the storage space) to replicate only a small amount of frequently accessed data. Furthermore, the storage nodes are divided into a hot node set and a cold node set. Hot nodes, which store a small amount of hot data copies, are always in an active state to guarantee the QoS of the system. The cold nodes which store a large number of infrequently accessed cold data, are placed in a low power state, thus reducing the energy consumption of the cluster storage system. The experimental results show that the proposed strategy can effectively reduce the resource and energy consumption of the system, while ensuring the system performance. © 2013 IEEE.

关键词： Energy utilization

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An efficient and fast polarity optimization approach for mixed polarity Reed-Muller logic circuits

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Frontiers of computer science 2017年第4期11卷 728-742页

作者： Zhenxue HE Limin XIAO Fei GU Tongsheng XIA Shubin SU Zhisheng HUO Rong ZHANG Longbing ZHANG Li RUAN Xiang WANG State Key Laboratory of Software Development Environment Beihang University Beijing 100191 China School of Computer Science and Engineering Beihang University Beijing 100191 China School of Electronic and Information Engineering Beihang University Beijing 100191 China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China National Engineering Research Center for Science & Technology Resources Sharing Service Beijing 100191 China

Although the genetic algorithm has been widely used in the polarity optimization of mixed polarity Reed- Muller （MPRM） logic circuits, few studies have taken into account the polarity conversion sequence. In order to im- prove the efficiency of polarity optimization of MPRM logic circuits, we propose an efficient and fast polarity optimiza- tion approach （FPOA） considering the polarity conversion se- quence. The main idea behind the FPOA is that, firstly, the best polarity conversion sequence of the polarity set wait- ing for evaluation is obtained by using the proposed hybrid genetic algorithm （HGA）; secondly, each of polarity in the polarity set is converted according to the best polarity con- version sequence obtained by HGA. Our proposed FPOA is implemented in C and a comparative analysis has been pre- sented for MCNC benchmark circuits. The experimental re- suits show that for the circuits with more variables, the FPOA is highly effective in improving the efficiency of polarity op- timization of MPRM logic circuits compared with the tradi- tional polarity optimization approach which neglects the po- larity conversion sequence and the improved polarity opti- mization approach with heuristic technique.

关键词： genetic algorithm polarity optimization mixed

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Parallelizing a machine translation decoder for multicore computer

Parallelizing a machine translation decoder for multicore co...

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2011 7th International Conference on Natural Computation, ICNC 2011

作者： Chen, Long Huo, Wei Mi, Haitao Zhang, Zhaoqing Feng, Xiaobing Li, Zhiyuan Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Department of Computer Science Purdue University West Lafayette IN 47907 United States

ISBN: (纸本)9781424499533

Machine translation (MT), with its broad potential use, has gained increased attention from both researchers and software vendors. To generate high quality translations, however, MT decoders can be highly computation intensive. With significant raw computing power, multi-core microprocessors have the potential to speed up MT software on desktop machines. However, retrofitting existing MT decoders is a nontrivial issue. Race conditions and atomicity issues are among those complications making parallelization difficult. In this article, we show that, to parallelize a state-of-the-art MT decoder, it is much easier to overcome such difficulties by using a process-based parallelization method, called functional task parallelism, than using conventional thread-based methods. We achieve a 7.60 times speed up on an 8-core desktop machine while making significantly less changes to the original sequential code than required by using multiple threads. © 2011 IEEE.

关键词： Machine translation

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MAP-numa: Access patterns used to characterize the NUMA memory access optimization techniques and algorithms

MAP-numa: Access patterns used to characterize the NUMA memo...

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9th IFIP International Conference on Network and Parallel Computing, NPC 2012

作者： Luo, Qiuming Liu, Chenjian Kong, Chang Cai, Ye Shenzhen China College of Computer Science and Software Engineering Shenzhen University China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

ISBN: (纸本)9783642356056

Some typical memory access patterns are provided and programmed in C, which can be used as benchmark to characterize the various techniques and algorithms aim to improve the performance of NUMA memory access. These access patterns, called MAP-numa (Memory Access Patterns for NUMA), currently include three classes, whose working data sets are corresponding to 1-dimension array, 2-dimension matrix and 3-dimension cube. It is dedicated for NUMA memory access optimization other than measuring the memory bandwidth and latency. MAP-numa is an alternative to those exist benchmarks such as STREAM, pChase, etc. It is used to verify the optimizations' (made automatically/manually to source code/executive binary) capacities by investigating what locality leakage can be remedied. Some experiment results are shown, which give an example of using MAP-numa to evaluate some optimizations based on Oprofile sampling. © IFIP International Federation for Information Processing 2012.

关键词： Benchmarking

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