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FUSE: Fusing STT-MRAMinto GPUs to alleviate off-chip memory access overheads

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arXiv 2019年

作者： Zhang, Jie Jung, Myoungsoo Kandemir, Mahmut Taylan Computer Architecture and Memory Systems Laboratory Yonsei University Pennsylvania State University

In this work, we propose FUSE, a novel GPU cache system that integrates spin-Transfer torque magnetic random-Access memory (STT-MRAM) into the on-chip L1D cache. FUSE can minimize the number of outgoing memory accesses over the interconnection network of GPU-s multiprocessors, which in turn can considerably improve the level of massive computing parallelism in GPUs. Specifically, FUSE predicts a read-level of GPU memory accesses by extracting GPU runtime information and places write-once-read-multiple (WORM) data blocks into the STT-MRAM, while accommodating write-multiple data blocks over a small portion of SRAM in the L1D cache. To further reduce the off-chip memory accesses, FUSE also allows WORM data blocks to be allocated anywhere in the STT-MRAM by approximating the associativity with the limited number of tag comparators and I/O peripherals. Our evaluation results show that, in comparison to a traditional GPU cache, our proposed heterogeneous cache reduces the number of outgoing memory references by 32% across the interconnection network, thereby improving the overall performance by 217% and reducing energy cost by 53%. Copyright © 2019, The Authors. All rights reserved.

关键词： Graphics processing unit

Exploring system challenges of ultra-low latency solid state drives 10

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Exploring system challenges of ultra-low latency solid state...

10th USENIX Workshop on Hot Topics in Storage and File systems, HotStorage 2018, co-located with USENIX ATC 2018

作者： Koh, Sungjoon Lee, Changrim Kwon, Miryeong Jung, Myoungsoo Computer Architecture and Memory Systems Laboratory Yonsei University Korea Republic of

We quantitatively characterize performance behaviors of a real ultra-low latency (ULL) SSD archive by using a real 800GB Z-SSD prototype, and analyze system-level challenges that the current storage stack exhibits. Specifically, our comprehensive empirical evaluations and studies demonstrate i) diverse performance analyses of the ULL SSD, including a wide range of latency and queue examinations, ii) I/O interference characteristics, which are considered as one of the great performance bottlenecks of modern SSDs, and iii) efficiency and challenge analyses of a polling-based I/O service (newly added into Linux 4.4 kernel) by comparing it with conventional interrupt-based I/O services. In addition to these performance characterizations, we discuss several system implications, which are required to take a full benefit of ULL SSD in the future. © USENIX Workshop on Hot Topics in Storage and File systems, HotStorage 2018, co-located with USENIX ATC *** right reserved.

关键词： File organization

Exploring Fault-Tolerant Erasure Codes for Scalable All-Flash Array Clusters

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arXiv 2019年

作者： Koh, Sungjoon Zhang, Jie Kwon, Miryeong Yoon, Jungyeon Donofrio, David Kim, Nam Sung Jung, Myoungsoo Computer Architecture and Memory Systems Laboratory Korea Advanced Institute of Science and Technology School of Integrated Technology Yonsei Institute Convergence Technology Yonsei University Lawrence Berkeley National Laboratory Georgia Institute of Technology University of Illinois Urbana-Champaign

—Large-scale systems with all-flash arrays have become increasingly common in many computing segments. To make such systems resilient, we can adopt erasure coding such as Reed-Solomon (RS) code as an alternative to replication because erasure coding incurs a significantly lower storage overhead than replication. To understand the impact of using erasure coding on the system performance and other system aspects such as CPU utilization and network traffic, we build a storage cluster that consists of approximately 100 processor cores with more than 50 high-performance solid-state drives (SSDs), and evaluate the cluster with a popular open-source distributed parallel file system, called Ceph. Specifically, we analyze the behaviors of a system adopting erasure coding from the following five viewpoints, and compare with those of another system using replication: (1) storage system I/O performance;(2) computing and software overheads;(3) I/O amplification;(4) network traffic among storage nodes, and (5) impact of physical data layout on performance of RS-coded SSD arrays. For all these analyses, we examine two representative RS configurations, used by Google file systems, and compare them with triple replication employed by a typical parallel file system as a default fault tolerance mechanism. Lastly, we collect 96 block-level traces from the cluster and release them to the public domain for the use of other researchers. Copyright © 2019, The Authors. All rights reserved.

关键词： File organization

Flashabacus: A self-governing flash-based accelerator for low-power systems

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arXiv 2018年

作者： Zhang, Jie Jung, Myoungsoo Computer Architecture and Memory Systems Laboratory School of Integrated Technology Yonsei University

Energy efficiency and computing flexibility are some of the primary design constraints of heterogeneous computing. In this paper, we present FlashAbacus, a data-processing accelerator that self-governs heterogeneous kernel executions and data storage accesses by integrating many flash modules in lightweight multiprocessors. The proposed accelerator can simultaneously process data from different applications with diverse types of operational functions, and it allows multiple kernels to directly access flash without the assistance of a host-level file system or an I/O runtime *** prototype FlashAbacus on a multicore-based PCIe platform that connects to FPGA-based flash controllers with a 20 nm node process. The evaluation results show that FlashAbacus can improve the bandwidth of data processing by 127%, while reducing energy consumption by 78.4%, as compared to a conventional method of heterogeneous computing. Copyright © 2018, The Authors. All rights reserved.

关键词： Energy utilization

Flashshare: punching through server storage stack from kernel to firmware for ultra-low latency SSDs 18

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Flashshare: punching through server storage stack from kerne...

Proceedings of the 13th USENIX conference on Operating systems Design and Implementation

作者： Jie Zhang Miryeong Kwon Donghyun Gouk Sungjoon Koh Changlim Lee Mohammad Alian Myoungjun Chun Mahmut Taylan Kandemir Nam Sung Kim Jihong Kim Myoungsoo Jung Yonsei University Computer Architecture and Memory Systems Laboratory University of Illinois Urbana-Champaign Seoul National University Pennsylvania State University

ISBN: (纸本)9781931971478

A modern datacenter server aims to achieve high energy efficiency by co-running multiple applications. Some of such applications (e.g., web search) are latency sensitive. Therefore, they require low-latency I/O services to fast respond to requests from clients. However, we observe that simply replacing the storage devices of servers with Ultra-Low-Latency (ULL) SSDs does not notably reduce the latency of I/O services, especially when co-running multiple applications. In this paper, we propose FLASHSHARE to assist ULL SSDs to satisfy different levels of I/O service latency requirements for different co-running applications. Specifically, FLASHSHARE is a holistic cross-stack approach, which can significantly reduce I/O interferences among co-running applications at a server without any change in applications. At the kernel-level, we extend the data structures of the storage stack to pass attributes of (co-running) applications through all the layers of the underlying storage stack spanning from the OS kernel to the SSD firmware. For given attributes, the block layer and NVMe driver of FLASHSHARE differently manage the I/O scheduler and interrupt handler of NVMe. We also enhance the NVMe controller and cache layer at the SSD firmware-level, by dynamically partitioning DRAM in the ULL SSD and adjusting its caching strategies to meet diverse user requirements. The evaluation results demonstrate that FLASHSHARE can shorten the average and 99th-percentile turnaround response times of co-running applications by 22% and 31%, respectively.

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Sprinkler: Maximizing resource utilization in many-chip solid state disks

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arXiv 2017年

作者： Jung, Myoungsoo Kandemir, Mahmut T. Computer Architecture and Memory Systems Laboratory Yonsei University Department of EECS Pennsylvania State University

Resource utilization is one of the emerging problems in many-chip SSDs. In this paper, we propose Sprinkler, a novel device-level SSD controller, which targets maximizing resource utilization and achieving high performance without additional NAND flash chips. Specifically, Sprinkler relaxes parallelism dependency by scheduling I/O requests based on internal resource layout rather than the order imposed by the device-level queue. In addition, Sprinkler improves flash-level parallelism and reduces the number of transactions (i.e., improves transactionallocality) by over-committing flash memory requests to specific resources. Our extensive experimental evaluation using a cycle-accurate large-scale SSD simulation framework shows that a many-chip SSD equipped with our Sprinkler provides at least 56.6% shorter latency and 1.8 2.2 times better throughput than the state-of-the-art SSD controllers. Further, it improves overall resource utilization by 68.8% under different I/O request patterns and provides, on average, 80.2% more flash-level parallelism by reducing half of the flash memory requests at runtime. Copyright © 2017, The Authors. All rights reserved.

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TraceTracker: Hardware/software co-evaluation for large-scale I/O workload reconstruction

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arXiv 2017年

作者： Kwon, Miryeong Zhang, Jie Park, Gyuyoung Choi, Wonil Donofrio, David Shalf, John Kandemir, Mahmut Jung, Myoungsoo Computer Architecture and Memory Systems Laboratory School of Integrated Technology Yonsei University Pennsylvania State University Lawrence Berkeley National Laboratory

Block traces are widely used for system studies, model verifications, and design analyses in both industry and academia. While such traces include detailed block access patterns, existing trace-driven research unfortunately often fails to find true-north due to a lack of runtime contexts such as user idle periods and system delays, which are fundamentally linked to the characteristics of target storage hardware. In this work, we propose TraceTracker, a novel hardware/software co-evaluation method that allows users to reuse a broad range of the existing block traces by keeping most their execution contexts and user scenarios while adjusting them with new system information. Specifically, our TraceTracker's software evaluation model can infer CPU burst times and user idle periods from old storage traces, whereas its hardware evaluation method remasters the storage traces by interoperating the inferred time information, and updates all inter-arrival times by making them aware of the target storage system. We apply the proposed co-evaluation model to 577 traces, which were collected by servers from different institutions and locations a decade ago, and revive the traces on a high-performance flash-based storage array. The evaluation results reveal that the accuracy of the execution contexts reconstructed by TraceTracker is on average 99% and 96% with regard to the frequency of idle operations and the total idle periods, respectively. Copyright © 2017, The Authors. All rights reserved.

关键词： computer software selection and evaluation

Understanding System Characteristics of Online Erasure Coding on Scalable, Distributed and Large-Scale SSD Array systems

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arXiv 2017年

作者： Koh, Sungjoon Zhang, Jie Kwon, Miryeong Yoon, Jungyeon Donofrio, David Kim, Namsung Jung, Myoungsoo Computer Architecture and Memory Systems Laboratory School of Integrated Technology Yonsei University Lawrence Berkeley National Laboratory Sk Telecom University of Illinois Urbana-Champaign

Large-scale systems with arrays of solid state disks (SSDs) have become increasingly common in many computing segments. To make such systems resilient, we can adopt erasure coding such as Reed-Solomon (RS) code as an alternative to replication because erasure coding can offer a significantly lower storage cost than replication. To understand the impact of using erasure coding on system performance and other system aspects such as CPU utilization and network traffic, we build a storage cluster consisting of approximately one hundred processor cores with more than fifty high-performance SSDs, and evaluate the cluster with a popular open-source distributed parallel file system, Ceph. Then we analyze behaviors of systems adopting erasure coding from the following five viewpoints, compared with those of systems using replication: (1) storage system I/O performance;(2) computing and software overheads;(3) I/O amplification;(4) network traffic among storage nodes;(5) the impact of physical data layout on performance of RS-coded SSD arrays. For all these analyses, we examine two representative RS configurations, which are used by Google and Facebook file systems, and compare them with triple replication that a typical parallel file system employs as a default fault tolerance mechanism. Lastly, we collect 54 block-level traces from the cluster and make them available for other researchers. Copyright © 2017, The Authors. All rights reserved.

关键词： File organization

SimpleSSD: Modeling Solid State Drives for Holistic System Simulation

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arXiv 2017年

作者： Jung, Myoungsoo Zhang, Jie Abulila, Ahmed Kwon, Miryeong Shahidi, Narges Shalf, John Kim, Nam Sung Kandemir, Mahmut Computer Architecture and Memory Systems Lab Yonsei University University of Illinois Urbana-Champaign Pennsylvania State University Lawrence Berkeley National Laboratory

—Existing solid state drive (SSD) simulators unfortunately lack hardware and/or software architecture models. Consequently, they are far from capturing the critical features of contemporary SSD devices. More importantly, while the performance of modern systems that adopt SSDs can vary based on their numerous internal design parameters and storage-level configurations, a full system simulation with traditional SSD models often requires unreasonably long runtimes and excessive computational resources. In this work, we propose SimpleSSD1, a high-fidelity simulator that models all detailed characteristics of hardware and software, while simplifying the nondescript features of storage internals. In contrast to existing SSD simulators, SimpleSSD can easily be integrated into publicly-available full system simulators. In addition, it can accommodate a complete storage stack and evaluate the performance of SSDs along with diverse memory technologies and microarchitectures. Thus, it facilitates simulations that explore the full design space at different levels of system abstraction. Copyright © 2017, The Authors. All rights reserved.

关键词： Simulators