检索结果-内蒙古大学图书馆

Implementing a 1GHz Four-Issue Out-of-Order Execution Microprocessor in a Standard Cell ASIC Methodology

Journal of computer Science & Technology 2007年第1期22卷 1-14页

作者：胡伟武赵继业钟石强杨旭 Elio Guidetti 吴永强 Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China ST Microelectronics 39 Chemin du Camp-des-Filles 1228 Plan Les Ouates Geneva Switzerland

This paper introduces the microarchitecture and physical implementation of the Godson-2E processor, which is a four-issue superscalar RISC processor that supports the 64-bit MIPS instruction set. The adoption of the aggressive out-of-order execution and memory hierarchy techniques help Godson-2E to achieve high performance. The Godson-2E processor has been physically designed in a 7-metal 90nm CMOS process using the cell-based methodology with some bitsliced manual placement and a number of crafted cells and macros. The processor can be run at 1GHz and achieves a SPEC CPU2000 rate higher than 500.

关键词： general-purpose processor superscalar pipeline out-of-order execution non-blocking cache physical design,synthesis flow bit-sliced placement crafted cell performance evaluation

来源：评论

学校读者我要写书评

暂无评论

Accelerating Data Transfer in Dataflow architectures Through a Look-Ahead Acknowledgment Mechanism

引用

Journal of computer Science & Technology 2022年第4期37卷 942-959页

作者： Yu-Jing Feng De-Jian Li Xu Tan Xiao-Chun Ye Dong-Rui Fan Wen-Ming Li Da Wang Hao Zhang Zhi-Min Tang State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of SciencesBeijing 100190China Beijing Smartchip Microelectronics Technology Company Limited Beijing 100000China School of Computer and Control Engineering University of Chinese Academy of SciencesBeijing 100190China

The dataflow architecture,which is characterized by a lack of a redundant unified control logic,has been shown to have an advantage over the control-flow architecture as it improves the computational performance and power efficiency,especially of applications used in high-performance computing(HPC).Importantly,the high computational efficiency of systems using the dataflow architecture is achieved by allowing program kernels to be activated in a simultaneous ***,a proper acknowledgment mechanism is required to distinguish the data that logically belongs to different *** solutions include the tagged-token matching mechanism in which the data is sent before acknowledgments are received but retried after rejection,or a handshake mechanism in which the data is only sent after acknowledgments are ***,these mechanisms are characterized by both inefficient data transfer and increased area *** performance of the dataflow architecture depends on the efficiency of data *** order to optimize the efficiency of data transfer in existing dataflow architectures with a minimal increase in area and power cost,we propose a Look-Ahead Acknowledgment(LAA)*** accelerates the execution flow by speculatively acknowledging ahead without *** simulation analysis based on a handshake mechanism shows that our LAA increases the average utilization of computational units by 23.9%,with a reduction in the average execution time by 17.4%and an increase in the average power efficiency of dataflow processors by 22.4%.Crucially,our novel approach results in a relatively small increase in the area and power consumption of the on-chip logic of less than 0.9%.In conclusion,the evaluation results suggest that Look-Ahead Acknowledgment is an effective improvement for data transfer in existing dataflow architectures.

关键词： dataflow model control-flow model high-performance computing application data transfer power efficiency

来源：评论

学校读者我要写书评

暂无评论

Statistical Interconnect Crosstalk Noise Model and Analysis for Process Variations

引用

Chinese Journal of Electronics 2015年第1期24卷 83-87页

作者： LI Jianwei DONG Gang WANG Zeng YE Xiaochun Faculty of Automation and Information Engineering Xi'an University of Technology State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences Microelectronics Institute Xidian University College of Physics Sicence Qingdao University

When operating frequency is over several gigahertz, the effect of inductance plays an important role and should be included for accurate and speed crosstalk noise analysis. And for new generation IC(Integrated circuit) design tools, the crosstalk noise analysis tools should consider the influence of process variations. In this paper, we propose coupled RLC crosstalk noise distributed parameter model with capacitive load termination. And we develop the framework that how to use the crosstalk noise model for process variations. Our results show that compare with HSPICE, the critical data errors of proposed model are within 1% and the relative errors occurred between calculated values for process variations and HSPICE Monte Carlo simulation values are less than 5%. The key features of the new model include:(1) The impact of inductance on crosstalk noise is considered;(2) The model can be used for process variations analysis;(3) The model reflect the effects of load capacitance directly;(4) The numerical inversion of Laplace transform is introduced for improving speed. So the proposed model meets the needs of future IC design both in speed and accuracy.

关键词： Crosstalk noise Interconnect Inductance Process variation Statistical

来源：评论

学校读者我要写书评

暂无评论

An efficient parity rearrangement coding scheme for RRAM thermal crosstalk effects 12

An efficient parity rearrangement coding scheme for RRAM the...

引用

2017 IEEE 12th International Conference on ASIC

作者： Yun Li Hai-hua Shen Ce Li Feng Zhang Key Laboratory of Microelectronics devices & Integrated Techonology Institute of Microelectronics of Chinese Academy of Sciences University of Chinese Academy of Science State Key Laboratory of Computer Architecture University of Chinese Academy of Science Institute of Computing Technology Chinese Academy of Sciences

ISBN: (纸本)9781509066261;9781509066254

Resistive random access memory（RRAM） is a promising non-volatile memory owing to its low operation voltage,small area,and good ***,the thermal crosstalk issue will significantly impact the retention properties of RRAM for high density integration and frequent writing operation,which commonly causes a series of error flips in some serious *** this paper,we propose an efficient parity rearrangement coding scheme,named PRCoder,to alleviate the influence of thermal crosstalk in *** implement the PRCoder at the algorithm level and simulated it at the hardware circuits level for different RRAM *** show that PRCoder can reduce the error flips caused by thermal crosstalk by about 32.7% on average with only one extra bit of redundancy per storage ***,PRCoder incurs a negligible performance overhead of .3% with less than 0.008% additional RRAM area.

关键词： RRAM thermal crosstalk PRCoder reset parity rearrangement algorithm

来源：评论

学校读者我要写书评

暂无评论

PAMPAR: A new parallel benchmark for performance and energy consumption evaluation

PAMPAR: A new parallel benchmark for performance and energy ...

引用

作者： Marques Garcia, Adriano Schepke, Claudio Girardi, Alessandro Advanced Studies Laboratory Federal University of Pampa Alegrete Brazil Computer Architecture and Microelectronics Group Federal University of Pampa Alegrete Brazil

This paper presents PAMPAR, a new benchmark to evaluate the performance and energy consumption of different Parallel Programming Interfaces (PPIs). The benchmark is composed of 11 algorithms implemented in PThreads, OpenMP, MPI-1, and MPI-2 (spawn) PPIs. Previous studies have used some of these pseudo-applications to perform this type of evaluation in different architectures since there is no benchmark that offers this variety of PPIs and communication models. In this work, we measure the energy and performance of each pseudo-application in a single architecture, varying the number of threads/processes. We also organize the pseudo-applications according to their memory accesses, floating-point operations, and branches. The goal is to show that this set of pseudo-applications has enough features to build a parallel benchmark. The results show that there is no single best case that provides both better performance and low energy consumption in the presented scenarios. Moreover, the pseudo-applications usage of the system resources are different enough to represent different scenarios and be efficient as a benchmark. © 2019 John Wiley & Sons, Ltd.

关键词： Electric power utilization

来源：评论

学校读者我要写书评

暂无评论

piRT-IFC:Physics-informed real-time impedance flow cytometry for the characterization of cellular intrinsic electrical properties

引用

Microsystems & Nanoengineering 2023年第3期9卷 347-356页

作者： Xiaofeng Luan Pengbin Liu Di Huang Haiping Zhao Yuang Li Sheng Sun Wenchang Zhang Lingqian Zhang Mingxiao Li Tian Zhi Yang Zhao Chengjun Huang Institute of Microelectronics of the Chinese Academy of Sciences BeijingChina University of Chinese Academy of Sciences BeijingChina State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of SciencesBeijingChina Cerebrovascular Diseases Research Institute Xuanwu Hospital of Capital Medical UniversityBeijingChina

Real-time transformation was important for the practical implementation of impedance flow *** major obstacle was the time-consuming step of translating raw data to cellular intrinsic electrical properties(e.g.,specific membrane capacitance C_(sm) and cytoplasm conductivityσ_(cyto)).Although optimization strategies such as neural network-aided strategies were recently reported to provide an impressive boost to the translation process,simultaneously achieving high speed,accuracy,and generalization capability is still *** this end,we proposed a fast parallel physical fitting solver that could characterize single cells’C_(sm)andσ_(cyto)within 0.62 ms/cell without any data preacquisition or pretraining *** achieved the 27000-fold acceleration without loss of accuracy compared with the traditional *** on the solver,we implemented physics-informed real-time impedance flow cytometry(piRT-IFC),which was able to characterize up to 100,902 cells’C_(sm) andσ_(cyto)within 50 min in a real-time *** to the fully connected neural network(FCNN)predictor,the proposed real-time solver showed comparable processing speed but higher ***,we used a neutrophil degranulation cell model to represent tasks to test unfamiliar samples without data for *** being treated with cytochalasin B and N-Formyl-Met-Leu-Phe,HL-60 cells underwent dynamic degranulation processes,and we characterized cell’s C_(sm)andσ_(cyto)using *** to the results from our solver,accuracy loss was observed in the results predicted by the FCNN,revealing the advantages of high speed,accuracy,and generalizability of the proposed piRT-IFC.

关键词： impedance intrinsic flow

来源：评论

学校读者我要写书评

暂无评论

An intelligent design machine: architecture and search strategies

引用

AI EDAM 2009年第2期2卷 105-122页

作者： Michael A. Gray Artificial Intelligence Laboratory Advanced Computer Architecture Microelectronics and Computer Technology Corporation Austin TX 78759 U.S.A.

In this report the architecture of an intelligent design machine capable of performing routine design in different design domains is described. This machine is crafted to operate as a part of a larger system driven by a human designer. Notable features are its use of best-first search strategies for problem-solving control and its ability to adjust problem-solving control strategies, perform automated redesign following specification changes, and resolve constraint violations using domain knowledge. The claims made for this machine are analyzed and it is argued that these claims are founded on established principles of design for intelligent systems. An implementation of this architecture in a rule-based system named Proteus is discussed and its operation is examined using as an example the domain of register-transfer-level computer design.

关键词：

来源：评论

学校读者我要写书评

暂无评论

Design, test, integration and packaging of MEMS/MOEMS, 2005

引用

ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING 2006年第1期48卷 5-5页

作者： Courtois, B Laboratory of Techniques of Informatics and Microelectronics for Computer Architecture (TIMA) CMP Service France ACM ASME IEEE IMAPS IEEE Computer Society Technical University of Budapest Hungary

No abstract available

关键词：

来源：评论

学校读者我要写书评

暂无评论

Memory bandwidth optimization of SpMV on GPGPUs

引用

Frontiers of computer Science 2015年第3期9卷 431-441页

作者： Chenggang Clarence YAN Hui YU Weizhi XU Yingping ZHANG Bochuan CHEN Zhu TIAN Yuxuan WANG Jian YIN Key Lab of Intelligent Information Processing Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Institute of Microelectronics Tsinghua University Beijing 100084 China Automation Department Tsinghua University Beijing 100084 China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China State Grid Information & Communication Company of Hunan EPC Changsha 410007 China Department of Computer Shandong University Weihai 250101 China

It is an important task to improve performance for sparse matrix vector multiplication （SpMV）, and it is a difficult task because of its irregular memory access. Gen- eral purpose GPU （GPGPU） provides high computing abil- ity and substantial bandwidth that cannot be fully exploited by SpMV due to its irregularity. In this paper, we propose two novel methods to optimize the memory bandwidth for SpMV on GPGPU. First, a new storage format is proposed to exploit memory bandwidth of GPU architecture more effi- ciently. The new storage format can ensure that there are as many non-zeros as possible in the format which is suitable to exploit the memory bandwidth of the GPU. Second, we pro- pose a cache blocking method to improve the performance of SpMV on GPU architecture. The sparse matrix is partitioned into sub-blocks that are stored in CSR format. With the block- ing method, the corresponding part of vector x can be reused in the GPU cache, so the time to access the global memory for vector x is reduced heavily. Experiments are carried out on three GPU platforms, GeForce 9800 GX2, GeForce GTX 480, and Tesla K40. Experimental results show that both new methods can efficiently improve the utilization of GPU mem- ory bandwidth and the performance of the GPU.

关键词： GPGPU performance tuning SpMV cacheblocking memory bandwidth

来源：评论

学校读者我要写书评

暂无评论

Logic as energy: A SAT-based approach

Logic as energy: A SAT-based approach

引用

2nd International Symposium on Brain, Vision, and Artificial Intelligence, BVAI 2007

作者： Lima, Priscila M. V. Morveli-Espinoza, M. Mariela M. França, Felipe M. G. LAM - Computer Architecture and Microelectronics Laboratory Universidade Federal Do Rio de Janeiro Brazil Departament d'Informàtica Universitat Autònoma de Barcelona Spain COPPE - Systems Engineering and Computer Science Program Universidade Federal Do Rio de Janeiro Brazil

ISBN: (纸本)3540755543

This paper presents the implementation of ARQ-PROP II, a limited-depth propositional reasoner, via the compilation of its specification into an exact formulation using the satyrus platform. satyrus' compiler takes as input the definition of a problem as a set of pseudo-Boolean constraints and produces, as output, the Energy function of a higher-order artificial neural network. This way, satisfiability of a formula can be associated to global optima. In the case of ARQ-PROP II, global optima is associated to Resolution-based refutation, in such a way that allows for simplified abduction and prediction to be unified with deduction. Besides experimental results on deduction with ARQ-PROP II, this work also corrects the mapping of satisfiability into Energy minima originally proposed by Gadi Pinkas. © 2007 Springer-Verlag Berlin Heidelberg.

关键词： Neural networks

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：