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piRT-IFC:Physics-informed real-time impedance flow cytometry for the characterization of cellular intrinsic electrical properties

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Microsystems & Nanoengineering 2023年第3期9卷 347-356页

作者： Xiaofeng Luan Pengbin Liu Di Huang Haiping Zhao Yuang Li Sheng Sun Wenchang Zhang Lingqian Zhang Mingxiao Li Tian Zhi Yang Zhao Chengjun Huang Institute of Microelectronics of the Chinese Academy of Sciences BeijingChina University of Chinese Academy of Sciences BeijingChina State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of SciencesBeijingChina Cerebrovascular Diseases Research Institute Xuanwu Hospital of Capital Medical UniversityBeijingChina

Real-time transformation was important for the practical implementation of impedance flow *** major obstacle was the time-consuming step of translating raw data to cellular intrinsic electrical properties(e.g.,specific membrane capacitance C_(sm) and cytoplasm conductivityσ_(cyto)).Although optimization strategies such as neural network-aided strategies were recently reported to provide an impressive boost to the translation process,simultaneously achieving high speed,accuracy,and generalization capability is still *** this end,we proposed a fast parallel physical fitting solver that could characterize single cells’C_(sm)andσ_(cyto)within 0.62 ms/cell without any data preacquisition or pretraining *** achieved the 27000-fold acceleration without loss of accuracy compared with the traditional *** on the solver,we implemented physics-informed real-time impedance flow cytometry(piRT-IFC),which was able to characterize up to 100,902 cells’C_(sm) andσ_(cyto)within 50 min in a real-time *** to the fully connected neural network(FCNN)predictor,the proposed real-time solver showed comparable processing speed but higher ***,we used a neutrophil degranulation cell model to represent tasks to test unfamiliar samples without data for *** being treated with cytochalasin B and N-Formyl-Met-Leu-Phe,HL-60 cells underwent dynamic degranulation processes,and we characterized cell’s C_(sm)andσ_(cyto)using *** to the results from our solver,accuracy loss was observed in the results predicted by the FCNN,revealing the advantages of high speed,accuracy,and generalizability of the proposed piRT-IFC.

关键词： impedance intrinsic flow

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Accelerating Data Transfer in Dataflow architectures Through a Look-Ahead Acknowledgment Mechanism

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Journal of computer Science & Technology 2022年第4期37卷 942-959页

作者： Yu-Jing Feng De-Jian Li Xu Tan Xiao-Chun Ye Dong-Rui Fan Wen-Ming Li Da Wang Hao Zhang Zhi-Min Tang State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of SciencesBeijing 100190China Beijing Smartchip Microelectronics Technology Company Limited Beijing 100000China School of Computer and Control Engineering University of Chinese Academy of SciencesBeijing 100190China

The dataflow architecture,which is characterized by a lack of a redundant unified control logic,has been shown to have an advantage over the control-flow architecture as it improves the computational performance and power efficiency,especially of applications used in high-performance computing(HPC).Importantly,the high computational efficiency of systems using the dataflow architecture is achieved by allowing program kernels to be activated in a simultaneous ***,a proper acknowledgment mechanism is required to distinguish the data that logically belongs to different *** solutions include the tagged-token matching mechanism in which the data is sent before acknowledgments are received but retried after rejection,or a handshake mechanism in which the data is only sent after acknowledgments are ***,these mechanisms are characterized by both inefficient data transfer and increased area *** performance of the dataflow architecture depends on the efficiency of data *** order to optimize the efficiency of data transfer in existing dataflow architectures with a minimal increase in area and power cost,we propose a Look-Ahead Acknowledgment(LAA)*** accelerates the execution flow by speculatively acknowledging ahead without *** simulation analysis based on a handshake mechanism shows that our LAA increases the average utilization of computational units by 23.9%,with a reduction in the average execution time by 17.4%and an increase in the average power efficiency of dataflow processors by 22.4%.Crucially,our novel approach results in a relatively small increase in the area and power consumption of the on-chip logic of less than 0.9%.In conclusion,the evaluation results suggest that Look-Ahead Acknowledgment is an effective improvement for data transfer in existing dataflow architectures.

关键词： dataflow model control-flow model high-performance computing application data transfer power efficiency

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PAMPAR: A new parallel benchmark for performance and energy consumption evaluation

PAMPAR: A new parallel benchmark for performance and energy ...

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作者： Marques Garcia, Adriano Schepke, Claudio Girardi, Alessandro Advanced Studies Laboratory Federal University of Pampa Alegrete Brazil Computer Architecture and Microelectronics Group Federal University of Pampa Alegrete Brazil

This paper presents PAMPAR, a new benchmark to evaluate the performance and energy consumption of different Parallel Programming Interfaces (PPIs). The benchmark is composed of 11 algorithms implemented in PThreads, OpenMP, MPI-1, and MPI-2 (spawn) PPIs. Previous studies have used some of these pseudo-applications to perform this type of evaluation in different architectures since there is no benchmark that offers this variety of PPIs and communication models. In this work, we measure the energy and performance of each pseudo-application in a single architecture, varying the number of threads/processes. We also organize the pseudo-applications according to their memory accesses, floating-point operations, and branches. The goal is to show that this set of pseudo-applications has enough features to build a parallel benchmark. The results show that there is no single best case that provides both better performance and low energy consumption in the presented scenarios. Moreover, the pseudo-applications usage of the system resources are different enough to represent different scenarios and be efficient as a benchmark. © 2019 John Wiley & Sons, Ltd.

关键词： Electric power utilization

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An Ultra-Low Power 3-T Chaotic Map based True Random Number Generator

An Ultra-Low Power 3-T Chaotic Map based True Random Number ...

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IEEE Asian Hardware-Oriented Security and Trust (AsianHOST)

作者： Lijuan Han Yuan Cao Lei Qian Haodong Xie Chip-Hong Chang College of Internet of Tings Engineering Hohai University Chang Zhou China Changzhou Galaxy Century Microelectronics Co. Ltd. State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences School of Electrical and Electronic Engineering Nanyang Technological University Singapore

ISBN: (纸本)9781665441865

In this paper, discrete-time chaos generator is exploited for lightweight and energy-efficient true random number generator (TRNG) implementation. The chaos generator is realized with a two-stage tent map circuit with feedback. Each stage consists of three transistors. Its transient characteristics can be tuned over a range of bias voltage to realize a family of tent map functions. The chaotic output voltage amplitude of each stage is highly sensitive to the environmental noise. The difference signal between two such chaos generators at each stage is amplified to produce a random binary output. The output of the quantized sense amplifier is sampled at twice the bit rate of each stage of tent map circuit. The proposed design was simulated using a standard 55 nm 1.2 V CMOS process. The results show that it has a very low power consumption of 10.98 μW. It has an ultra-low energy consumption of only 5.49 pJ/bit at a throughput of 2 Mbps, which is 19x lower than the recently reported state-of-the-art and the most power efficient chaotic TRNGs. The random bit stream generated by the proposed TRNG has passed entropy, ACF and NIST randomness tests.

关键词： Chaos Voltage NIST Throughput CMOS process Generators Entropy

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Fault Tolerance Research of Visual Convolutional Neural Networks Based on Soft Errors

Fault Tolerance Research of Visual Convolutional Neural Netw...

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IEEE Information Technology, Networking, Electronic and Automation Control Conference

作者： Xiaotong Xu Yuzhuo Fu Ting Liu Hongjun You Intelligent Computer Architecture Technology(iCAT) Lab of School of Microelectronics Shanghai JiaoTong University Shanghai China Key Laboratory of Intelligent Computing Technology (SAST) Shanghai Aerospace Electronic Technology Institute Shanghai China

ISBN: (数字)9781728143903

ISBN: (纸本)9781728143910

Injecting faults to the system architecture layer and studying the upper neural network for fault tolerancehe is difficult and time-consuming. This paper proposes an automatic method covering time and space, which can inject faults into the processor on the Simics simulation platform, simulating soft errors, and then collect the time sequence data of the system architecture layer and the observed node data of visual convolutional neural networks program layer. At the same time, combined with the relevant standards, the GAN classifier is used to calibrate the different fault models after converting time sequence data into time sequence images. Finally, the Bayesian network is used to form the path of fault propagation from the architecture layer to the program layer and the result layer. After intensive fault injection into critical registers, the probability of neural network failure caused by soft errors is effectively stimulated.

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An efficient parity rearrangement coding scheme for RRAM thermal crosstalk effects 12

An efficient parity rearrangement coding scheme for RRAM the...

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2017 IEEE 12th International Conference on ASIC

作者： Yun Li Hai-hua Shen Ce Li Feng Zhang Key Laboratory of Microelectronics devices & Integrated Techonology Institute of Microelectronics of Chinese Academy of Sciences University of Chinese Academy of Science State Key Laboratory of Computer Architecture University of Chinese Academy of Science Institute of Computing Technology Chinese Academy of Sciences

ISBN: (纸本)9781509066261;9781509066254

Resistive random access memory（RRAM） is a promising non-volatile memory owing to its low operation voltage,small area,and good ***,the thermal crosstalk issue will significantly impact the retention properties of RRAM for high density integration and frequent writing operation,which commonly causes a series of error flips in some serious *** this paper,we propose an efficient parity rearrangement coding scheme,named PRCoder,to alleviate the influence of thermal crosstalk in *** implement the PRCoder at the algorithm level and simulated it at the hardware circuits level for different RRAM *** show that PRCoder can reduce the error flips caused by thermal crosstalk by about 32.7% on average with only one extra bit of redundancy per storage ***,PRCoder incurs a negligible performance overhead of .3% with less than 0.008% additional RRAM area.

关键词： RRAM thermal crosstalk PRCoder reset parity rearrangement algorithm

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Combination of Measurements of the Top Quark Mass from Data Collected by the ATLAS and CMS Experiments at s=7 and 8 TeV

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Physical Review Letters 2024年第26期132卷 261902-261902页

作者： A. Hayrapetyan A. Tumasyan W. Adam J. W. Andrejkovic T. Bergauer S. Chatterjee K. Damanakis M. Dragicevic P. S. Hussain M. Jeitler N. Krammer A. Li D. Liko I. Mikulec J. Schieck R. Schöfbeck D. Schwarz M. Sonawane S. Templ W. Waltenberger C.-E. Wulz M. R. Darwish T. Janssen P. Van Mechelen E. S. Bols J. D’Hondt S. Dansana A. De Moor M. Delcourt H. El Faham S. Lowette I. Makarenko D. Müller A. R. Sahasransu S. Tavernier M. Tytgat S. Van Putte D. Vannerom B. Clerbaux G. De Lentdecker L. Favart D. Hohov J. Jaramillo A. Khalilzadeh K. Lee M. Mahdavikhorrami A. Malara S. Paredes L. Pétré N. Postiau L. Thomas M. Vanden Bemden C. Vander Velde P. Vanlaer M. De Coen D. Dobur Y. Hong J. Knolle L. Lambrecht G. Mestdach C. Rendón A. Samalan K. Skovpen N. Van Den Bossche J. van der Linden L. Wezenbeek A. Benecke G. Bruno C. Caputo C. Delaere I. S. Donertas A. Giammanco K. Jaffel Sa. Jain V. Lemaitre J. Lidrych P. Mastrapasqua K. Mondal T. T. Tran S. Wertz G. A. Alves E. Coelho C. Hensel T. Menezes De Oliveira A. Moraes P. Rebello Teles M. Soeiro W. L. Aldá Júnior M. Alves Gallo Pereira M. Barroso Ferreira Filho H. Brandao Malbouisson W. Carvalho J. Chinellato E. M. Da Costa G. G. Da Silveira D. De Jesus Damiao S. Fonseca De Souza R. Gomes De Souza J. Martins C. Mora Herrera K. Mota Amarilo L. Mundim H. Nogima A. Santoro A. Sznajder M. Thiel A. Vilela Pereira C. A. Bernardes L. Calligaris T. R. Fernandez Perez Tomei E. M. Gregores P. G. Mercadante S. F. Novaes B. Orzari Sandra S. Padula A. Aleksandrov G. Antchev R. Hadjiiska P. Iaydjiev M. Misheva M. Shopova G. Sultanov A. Dimitrov L. Litov B. Pavlov P. Petkov A. Petrov E. Shumka S. Keshri S. Thakur T. Cheng Q. Guo T. Javaid L. Yuan Z. Hu J. Liu K. Yi G. M. Chen H. S. Chen M. Chen F. Iemmi C. H. Jiang A. Kapoor H. Liao Z.-A. Liu R. Sharma J. N. Song J. Tao C. Wang J. Wang Z. Wang H. Zhang A. Agapitos Y. Ban A. Levin C. Li Q. Li Y. Mao S. J. Qian X. Sun D. Wang H. Yang L. Zhang C. Zhou Z. You N. Lu G. Bauer X. Gao D. Leggat H. Okawa Y. Zhang Z. Lin C. Lu M. Xiao C. Avila D. A. Yerevan Physics Institute Yerevan Armenia Institut für Hochenergiephysik Vienna Austria Indian Institute of Technology Madras Madras India APC Université Paris Cité CNRS/IN2P3 Paris France Universiteit Antwerpen Antwerpen Belgium Vrije Universiteit Brussel Brussel Belgium Université Libre de Bruxelles Bruxelles Belgium Korea University Seoul Korea Ghent University Ghent Belgium Université Catholique de Louvain Louvain-la-Neuve Belgium Centro Brasileiro de Pesquisas Fisicas Rio de Janeiro Brazil Universidade do Estado do Rio de Janeiro Rio de Janeiro Brazil Universidade Estadual Paulista Universidade Federal do ABC São Paulo Brazil Institute for Nuclear Research and Nuclear Energy Bulgarian Academy of Sciences Sofia Bulgaria University of Sofia Sofia Bulgaria IJCLab Université Paris-Saclay CNRS/IN2P3 91405 Orsay France Instituto De Alta Investigación Universidad de Tarapacá Casilla 7 D Arica Chile Beihang University Beijing China Department of Physics Tsinghua University Beijing China Institute of High Energy Physics Beijing China Department of Physics Oxford University Oxford United Kingdom School of Physics and Astronomy Shanghai Jiao Tong University Key Laboratory for Particle Astrophysics and Cosmology (MOE) SKLPPC Shanghai China Department of Physics Chinese University of Hong Kong Shatin N.T. Hong Kong China Department of Physics University of Michigan Ann Arbor Michigan USA State Key Laboratory of Nuclear Physics and Technology Peking University Beijing China Department of Modern Physics and State Key Laboratory of Particle Detection and Electronics University of Science and Technology of China Hefei China Department of Physics Nanjing University Nanjing China Sun Yat-Sen University Guangzhou China University of Science and Technology of China Hefei China Nanjing Normal University Nanjing China Institute of Modern Physics and Key Laboratory of Nuclear Physics and Ion-beam Application (MOE)—Fudan University Shanghai China Zhe

A combination of fifteen top quark mass measurements performed by the ATLAS and CMS experiments at the LHC is presented. The datasets used correspond to an integrated luminosity of up to 5 and 20 fb−1 of proton-proton collisions at center-of-mass energies of 7 and 8 TeV, respectively. The combination includes measurements in top quark pair events that exploit both the semileptonic and hadronic decays of the top quark, and a measurement using events enriched in single top quark production via the electroweak t channel. The combination accounts for the correlations between measurements and achieves an improvement in the total uncertainty of 31% relative to the most precise input measurement. The result is mt=172.52±0.14(stat)±0.30(syst) GeV, with a total uncertainty of 0.33 GeV.

关键词： Top quark Hadron colliders

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Statistical Interconnect Crosstalk Noise Model and Analysis for Process Variations

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Chinese Journal of Electronics 2015年第1期24卷 83-87页

作者： LI Jianwei DONG Gang WANG Zeng YE Xiaochun Faculty of Automation and Information Engineering Xi'an University of Technology State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences Microelectronics Institute Xidian University College of Physics Sicence Qingdao University

When operating frequency is over several gigahertz, the effect of inductance plays an important role and should be included for accurate and speed crosstalk noise analysis. And for new generation IC(Integrated circuit) design tools, the crosstalk noise analysis tools should consider the influence of process variations. In this paper, we propose coupled RLC crosstalk noise distributed parameter model with capacitive load termination. And we develop the framework that how to use the crosstalk noise model for process variations. Our results show that compare with HSPICE, the critical data errors of proposed model are within 1% and the relative errors occurred between calculated values for process variations and HSPICE Monte Carlo simulation values are less than 5%. The key features of the new model include:(1) The impact of inductance on crosstalk noise is considered;(2) The model can be used for process variations analysis;(3) The model reflect the effects of load capacitance directly;(4) The numerical inversion of Laplace transform is introduced for improving speed. So the proposed model meets the needs of future IC design both in speed and accuracy.

关键词： Crosstalk noise Interconnect Inductance Process variation Statistical

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Memory bandwidth optimization of SpMV on GPGPUs

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Frontiers of computer Science 2015年第3期9卷 431-441页

作者： Chenggang Clarence YAN Hui YU Weizhi XU Yingping ZHANG Bochuan CHEN Zhu TIAN Yuxuan WANG Jian YIN Key Lab of Intelligent Information Processing Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Institute of Microelectronics Tsinghua University Beijing 100084 China Automation Department Tsinghua University Beijing 100084 China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China State Grid Information & Communication Company of Hunan EPC Changsha 410007 China Department of Computer Shandong University Weihai 250101 China

It is an important task to improve performance for sparse matrix vector multiplication （SpMV）, and it is a difficult task because of its irregular memory access. Gen- eral purpose GPU （GPGPU） provides high computing abil- ity and substantial bandwidth that cannot be fully exploited by SpMV due to its irregularity. In this paper, we propose two novel methods to optimize the memory bandwidth for SpMV on GPGPU. First, a new storage format is proposed to exploit memory bandwidth of GPU architecture more effi- ciently. The new storage format can ensure that there are as many non-zeros as possible in the format which is suitable to exploit the memory bandwidth of the GPU. Second, we pro- pose a cache blocking method to improve the performance of SpMV on GPU architecture. The sparse matrix is partitioned into sub-blocks that are stored in CSR format. With the block- ing method, the corresponding part of vector x can be reused in the GPU cache, so the time to access the global memory for vector x is reduced heavily. Experiments are carried out on three GPU platforms, GeForce 9800 GX2, GeForce GTX 480, and Tesla K40. Experimental results show that both new methods can efficiently improve the utilization of GPU mem- ory bandwidth and the performance of the GPU.

关键词： GPGPU performance tuning SpMV cacheblocking memory bandwidth

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Automatic complex instruction identification for efficient application mapping onto ASIPs

Automatic complex instruction identification for efficient a...

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IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： Alexandre S. Nery Nadia Nedjah Felipe M. G. França Lech Jozwiak Henk Corporaal Department of Electrical Engineering - Electronic Systems Eindhoven University of Technology The Netherlands Department of Electronics Engineering and Telecommunications Universidade do Estado do Rio de Janeiro Brazil LAM - Computer Architecture and Microelectronics Laboratory Universidade Federal do Rio de Janeiro Brazil

Instruction Set Customization is a well-known technique to enhance the performance and efficiency of Application-Specific Processors (ASIPs). An extensive application profiling can indicate which parts of a given application, or class of applications, are most frequently executed, enabling the implementation of such frequently executed parts in hardware as custom instructions. However, a naive ad hoc instruction set customization process may identify and select poor instruction extension candidates, which may not result in a significantly improved performance with low circuit-area and energy footprints. In this paper we propose and discuss an efficient instruction set customization method and automatic tool, which exploit the maximal common subgraphs (common operation patterns) of the most frequently executed basic blocks of a given application. The speed results from our tool for a VLIW ASIP are provided for a set of benchmark applications. The average execution time reduction ranges from 30% to 40%, with only a few custom instructions.

关键词： VLIW Hardware Ray tracing Program processors Registers Libraries Convolution

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