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2012 IEEE International Conference on computer Science and Automation Engineering, CSAE 2012

作者： Pei, Songwei Li, Zhaolin Li, Huawei Li, Xiaowei Wei, Shaojun Research Institute of Information Technology Tsinghua University Beijing 100084 China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Institute of Microelectronics Tsinghua University Beijing 100084 China

ISBN: (纸本)9781467300865

With the continual scaling of semiconductor process technology, the circuit timing is increasingly impacted by process variations. It is thus important to categorize high-speed digital circuits into multiple bins of different performances. However, the speed-binning process typically needs very long test application time. In this paper, we proposed a unified architecture, which can accomplish performance grading with a high confidence and short test application time. Moreover, the proposed architecture can be used for on-line circuit failure prediction and detection. Experimental results are presented to validate the proposed architecture. © 2012 IEEE.

关键词： Grading

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Analytical modelling and simulations of a MEMS micro-mirror - MATLAB implementation

Analytical modelling and simulations of a MEMS micro-mirror ...

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International Conference on CAD Systems in microelectronics (CADSM)

作者： W. Cichalewski A. Napieralski H. Camon B. Estibals Department of Microelectronics and Computer Science TUL Lodz Poland Laboratory for Analysis and Architecture of Systems CNRS Toulouse France

This paper is devoted to the study of the static and dynamical behaviour of a ID torsion single crystal silicon micro-mirror. The aim is to create a parametric model of such mirror allowing to use a simple calculation program to avoid expensive and long FEM simulations. This study tries to put in place a modelling to define the best structure with regard to various specification by taking into account the technological possibilities and to simulate the experimental characteristics before the expensive technological process.

关键词： Analytical models Mathematical model Micromechanical devices MATLAB Mirrors Electrodes Torque Silicon Electrostatics Voltage

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An efficient shared memory based virtual communication system for embedded SMP cluster

An efficient shared memory based virtual communication syste...

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IEEE International Conference on Networking, architecture and Storage

作者： Yin, Wenxuan Gao, Xiang Zhu, Xiaojing Guo, Deyuan Graduate University of Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Loongson Technology Corporation Limited Beijing China Institute of Microelectronics Tsinghua University Beijing China

ISBN: (纸本)9780769545097

With the prevalence of multi-core processors, it is a trend that the embedded cluster deploys SMP nodes to gain more computing power. As a crucial issue, the MPI interprocess communication has been suffering the contradiction between high performance and embedded constraints. Moreover, there is a big performance gap between intra- and inter-node communication for different infrastructures. In this paper, we design a virtual communication system called SMVN, which extends the shared memory mechanism typically used in intra-node case into the inter-node case. The SMVN utilizes the HT inter-chip interconnect interface in Godson-3A SMP nodes to build a mesh topology. It is Ethernet compatible by simulating bottom layers of TCP/IP protocol. With the design, the node interconnection can get rid of NICs, cables and switches. Furthermore, we exploit the zero-copy scheme and other optimizations to improve the performance. We port the MPICH2 library by socket channel and formulate its process allocation. The MPI latency and bandwidth tests show that the performance difference between two levels is small. The inter-node bandwidth is 27.3MB/s, which is more than twice the theoretical peak value of 100Mb Ethernet and reaches 84% of the intra-node performance. © 2011 IEEE.

关键词： Bandwidth

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A parallel Ray Tracing architecture suitable for application-specific hardware and GPGPU implementations

A parallel Ray Tracing architecture suitable for application...

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2011 14th Euromicro Conference on Digital System Design: architectures, Methods and Tools, DSD 2011

作者： Nery, Alexandre S. Nedjah, Nadia Franca, Felipe M.G. Jozwiak, Lech LAM - Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal Rio de Janeiro Brazil Department of Electronics Engineering and Telecommunications Faculty of Engineering Universidade do Estado Rio de Janeiro Brazil Department of Electrical Engineering - Electronic Systems Eindhoven University of Technology Netherlands

ISBN: (纸本)9780769544946

The Ray Tracing rendering algorithm can produce high-fidelity images of 3-D scenes, including shadow effects, as well as reflections and transparencies. This is currently done at a processing speed of at most 30 frames per second. Therefore, actual implementations of the algorithm are not yet suitable for interactive real-time rendering, which is required in games and virtual reality based applications. Fortunately, the algorithm allows for massive parallelization of its computations. In this paper, we present a parallel architecture for ray tracing based on a uniform spatial subdivision of the scene and exploiting an embedded computation of ray-triangle intersections. This approach allows for a significant acceleration of intersection computations, as well as, a reduction of the total number of the required intersections checks. Furthermore, it allows for these checks to be performed in parallel and in advance for each ray. In this paper we discuss and analyze an ASIP-based implementation using FPGAs and a GPGPU-based parallel implementation of the proposed architecture. The performance of both implementations are reported and compared." © 2011 IEEE.

关键词： Ray tracing

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An algorithm for geometric load balancing with two constraints

An algorithm for geometric load balancing with two constrain...

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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： J. Kim M. Papaefthymiou A. Tayyab Advanced Computer Architecture Laboratory EECS Department University of Michigan Ann Arbor MI USA IBM Microelectronics Austin TX USA

Summary form only given. We describe an algorithm for partitioning 2-weighted geometric graphs, so that each of the two weights is evenly distributed among all partitions and cutsize is minimal. This algorithm is applicable to load balancing problems in parallel computing, including scientific computation or circuit optimization, in which computational load depends on multiple factors, and geometric proximity needs to be preserved. We first show that for two continuous weight distributions, there always exists an L-shape separator that divides the two weights exactly. Based on this fact, we then give a practical and efficient heuristic for 2/sup p/-way partitioning. Our heuristic relies on recursive bipartitioning and runs in O(nlgn+m2/sup p/) time, where n is the number of vertices and m is the number of rows in the graph. In experiments with geometric graphs obtained from placed benchmark VLSI circuits, our heuristic generates balanced partitions with imbalance no greater than 2%, very short runtimes, and good cutsizes. For example, given a geometric graph with n>100,000, our heuristic computes a 32-way partitioning with 0.46% maximum imbalance within 0.5 second.

关键词： Load management Parallel processing Partitioning algorithms Concurrent computing Particle separators Very large scale integration Circuits computer architecture Laboratories microelectronics

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An Efficient Shared Memory Based Virtual Communication System for Embedded SMP Cluster

An Efficient Shared Memory Based Virtual Communication Syste...

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International Conference on Networking, architecture, and Storage (NAS)

作者： Wenxuan Yin Xiang Gao Xiaojing Zhu Deyuan Guo Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Institute of Microelectronics Tsinghua University Beijing China

With the prevalence of multi-core processors, it is a trend that the embedded cluster deploys SMP nodes to gain more computing power. As a crucial issue, the MPI inter-process communication has been suffering the contradiction between high performance and embedded constraints. Moreover, there is a big performance gap between intra- and inter-node communication for different infrastructures. In this paper, we design a virtual communication system called SMVN, which extends the shared memory mechanism typically used in intra-node case into the inter-node case. The SMVN utilizes the HT inter-chip interconnect interface in Godson-3A SMP nodes to build a mesh topology. It is Ethernet compatible by simulating bottom layers of TCP/IP protocol. With the design, the node interconnection can get rid of NICs, cables and switches. Furthermore, we exploit the zero-copy scheme and other optimizations to improve the performance. We port the MPICH2 library by socket channel and formulate its process allocation. The MPI latency and bandwidth tests show that the performance difference between two levels is small. The inter-node bandwidth is 27.3 MB/s, which is more than twice the theoretical peak value of 100 Mb Ethernet and reaches 84% of the intra-node performance.

关键词： Program processors IP networks Protocols computer architecture Bandwidth Resource management Synchronization

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Hardware reuse in modern application-specific processors and accelerators

Hardware reuse in modern application-specific processors and...

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2011 14th Euromicro Conference on Digital System Design: architectures, Methods and Tools, DSD 2011

作者： Nery, Alexandre S. Jozwiak, Lech Lindwer, Menno Cocco, Mauro Nedjah, Nadia França, Felipe M.G. LAM - Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal do Rio de Janeiro Brazil Department of Electronics Engineering and Telecommunications Faculty of Engineering Universidade do Estado do Rio de Janeiro Brazil Department of Electrical Engineering - Electronic Systems Eindhoven University of Technology Netherlands Silicon Hive - Intel UMG Netherlands

ISBN: (纸本)9780769544946

Effective exploitation of the application-specific parallel patterns and computation operations through their direct implementation in hardware is the base for construction of high-quality application-specific (re-) configurable application specific instruction set processors (ASIPs) and hardware accelerators for modern highly-demanding applications. Although it receives a lot of attention from the researchers and practitioners, a very important problem of hardware reuse in ASIP and accelerator synthesis is clearly underestimated and does not get enough attention in the published research. This paper is an effect of an industry and academic collaborative research. It analyses the problem of hardware sharing, shows its high practical relevance, as well as a big influence of hardware sharing on the major circuit and system parameters, and its importance for the multi-objective optimization and tradeoff exploitation. It also demonstrates that the state-of-the-art synthesis tools do not sufficiently address this problem and gives several guidelines related to enhancement of the hardware reuse. © 2011 IEEE.

关键词： Multiobjective optimization

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A massively parallel hardware architecture for ray-tracing

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International Journal of High Performance Systems architecture 2009年第1期2卷 26-34页

作者： Nery, A.S. Nedjah, N. França, F.M.G. Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE P.O. Box 68511 21941-972 Rio de Janeiro Brazil Department of Electronics Engineering and Telecommunications Faculty of Engineering Universidade do Estado do Rio de Janeiro Rua Sao Francisco Xavier 524 Sala 5145-F Maracana 20.550-900 Rio de Janeiro RJ Brazil Universidade Federal do Rio de Janeiro Rio de Janeiro Brazil Department of Electronics Engineering and Telecommunications Faculty of Engineering State University of Rio de Janeiro Brazil Brazil

Real time performance of non-interactive rendering of three-dimensional scenes is usually unachievable. Ray tracing is one of the methods used for rendering such scenes. The performance achieved by a sequential software-based implementation of ray tracing is far from satisfactory. In contrast, many parallel implementations of ray tracing have been enabling real time performance, as the underlying algorithm can be massively parallelised. Thus, it is expected that a custom parallel design in hardware is likely to achieve the acceptable performance standards. In this paper, we propose a hardware architecture, which we call GridRT, capable of dealing with the main desirable features of ray tracing, such as shadows and reflections effects, imposing low requirements in terms of silicon area while achieving acceptable performance in terms of rendering time. This architecture achieves is efficient yet compact as it explores the massive parallelism offered by the intrinsic structure of the algorithm. The design exploits the usage the spatial data structure of regular grids. Copyright © 2009 Inderscience Enterprises Ltd.

关键词： Ray tracing

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Fault Tolerance Research of Visual Convolutional Neural Networks Based on Soft Errors

Fault Tolerance Research of Visual Convolutional Neural Netw...

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IEEE Information Technology, Networking, Electronic and Automation Control Conference

作者： Xiaotong Xu Yuzhuo Fu Ting Liu Hongjun You Intelligent Computer Architecture Technology(iCAT) Lab of School of Microelectronics Shanghai JiaoTong University Shanghai China Key Laboratory of Intelligent Computing Technology (SAST) Shanghai Aerospace Electronic Technology Institute Shanghai China

ISBN: (数字)9781728143903

ISBN: (纸本)9781728143910

Injecting faults to the system architecture layer and studying the upper neural network for fault tolerancehe is difficult and time-consuming. This paper proposes an automatic method covering time and space, which can inject faults into the processor on the Simics simulation platform, simulating soft errors, and then collect the time sequence data of the system architecture layer and the observed node data of visual convolutional neural networks program layer. At the same time, combined with the relevant standards, the GAN classifier is used to calibrate the different fault models after converting time sequence data into time sequence images. Finally, the Bayesian network is used to form the path of fault propagation from the architecture layer to the program layer and the result layer. After intensive fault injection into critical registers, the probability of neural network failure caused by soft errors is effectively stimulated.

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A unified architecture for speed-binning and circuit failure prediction and detection

A unified architecture for speed-binning and circuit failure...

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IEEE International Conference on computer Science and Automation Engineering (CSAE)

作者： Songwei Pei Zhaolin Li Huawei Li Xiaowei Li Shaojun Wei Research Institute of Information Technology Tsinghua University Beijing China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Institute of Microelectronics Tsinghua University Beijing China

关键词： Delay Clocks computer architecture Circuit stability Aging Logic gates System-on-a-chip

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