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Euromicro Symposium on Digital System Design

作者： Alexandre S. Nery Nadia Nedjah Felipa M.G. Franca Lech Jozwiak LAM-Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal do Rio de Janeiro Brazil Department of Electrical Engineering-Electronic Systems Eindhoven University of Technology Netherlands Universidade do Estado do Rio de Janeiro Rio de Janeiro RJ BR

The Ray Tracing rendering algorithm can produce high-fidelity images of 3-D scenes, including shadow effects, as well as reflections and transparencies. This is currently done at a processing speed of at most 30 frames per second. Therefore, actual implementations of the algorithm are not yet suitable for interactive real-time rendering, which is required in games and virtual reality based applications. Fortunately, the algorithm allows for massive parallelization of its computations. In this paper, we present a parallel architecture for ray tracing based on a uniform spatial subdivision of the scene and exploiting an embedded computation of ray-triangle intersections. This approach allows for a significant acceleration of intersection computations, as well as, a reduction of the total number of the required intersections checks. Furthermore, it allows for these checks to be performed in parallel and in advance for each ray. In this paper we discuss and analyze an ASIP-based implementation using FPGAs and a GPGPU-based parallel implementation of the proposed architecture. The performance of both implementations are reported and compared.

关键词： Ray tracing Graphics processing unit Instruction sets computer architecture Registers Image color analysis Hardware

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A parallel architecture for ray-tracing with an embedded intersection algorithm

A parallel architecture for ray-tracing with an embedded int...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Alexandre S. Nery Nadia Nedjah Felipe M.G. França Lech Jozwiak LAM-Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal do Rio de Janeiro Brazil Department of Electrical Engineering-Electronic Systems Eindhovan University of Technology Netherlands Department of Electronics Engineering and Telecommunications-Faculty of Engineering Universidade do Estado do Rio de Janeiro (UERJ) Brazil

Real time rendering of three-dimensional scenes in Ray Tracing is a hard problem. However, parallel implementations have been enabling real time performance, as the algorithm can be highly parallelized. Thus, a custom parallel design in hardware is likely to achieve a good performance. In this paper, we further improve the GridRT architecture overall performance by embedding the ray-triangle intersection computation into the precessing elements that form the architecture. Low cost and high rendering performance are the main concerns in this novel design. The results show that the execution time of each intersection computation is reduced by at least 50%, while the area cost is practically unchanged or even reduced when compared to the original GridRT implementation.

关键词： Ray tracing Registers Equations USA Councils Mathematical model Parallel architectures

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Hardware Reuse in Modern Application-Specific Processors and Accelerators

Hardware Reuse in Modern Application-Specific Processors and...

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Euromicro Symposium on Digital System Design

作者： Alexandre S. Nery Lech Jozwiak Menno Lindwer Mauro Cocco Nadia Nedjah Felipe M.G. Franca LAM-Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal do Rio de Janeiro Brazil Department of Electrical Engineering-Electronic Systems Eindhoven University of Technology Netherlands Silicon Hive-Intel UMG Netherlands Department of Electronics Engineering and Telecommunications-Faculty of Engineering Universidade do Estado do Rio de Janeiro Brazil

Effective exploitation of the application-specific parallel patterns and computation operations through their direct implementation in hardware is the base for construction of high-quality application-specific (re-)configurable application specific instruction set processors (ASIPs) and hardware accelerators for modern highly-demanding applications. Although it receives a lot of attention from the researchers and practitioners, a very important problem of hardware reuse in ASIP and accelerator synthesis is clearly underestimated and does not get enough attention in the published research. This paper is an effect of an industry and academic collaborative research. It analyses the problem of hardware sharing, shows its high practical relevance, as well as a big influence of hardware sharing on the major circuit and system parameters, and its importance for the multi-objective optimization and tradeoff exploitation. It also demonstrates that the state-of-the-art synthesis tools do not sufficiently address this problem and gives several guidelines related to enhancement of the hardware reuse.

关键词： Hardware Resource management computer architecture Optimization Program processors Adders Delay

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An intelligent design machine: architecture and search strategies

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AI EDAM 2009年第2期2卷 105-122页

作者： Michael A. Gray Artificial Intelligence Laboratory Advanced Computer Architecture Microelectronics and Computer Technology Corporation Austin TX 78759 U.S.A.

In this report the architecture of an intelligent design machine capable of performing routine design in different design domains is described. This machine is crafted to operate as a part of a larger system driven by a human designer. Notable features are its use of best-first search strategies for problem-solving control and its ability to adjust problem-solving control strategies, perform automated redesign following specification changes, and resolve constraint violations using domain knowledge. The claims made for this machine are analyzed and it is argued that these claims are founded on established principles of design for intelligent systems. An implementation of this architecture in a rule-based system named Proteus is discussed and its operation is examined using as an example the domain of register-transfer-level computer design.

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A massively parallel hardware architecture for ray-tracing

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International Journal of High Performance Systems architecture 2009年第1期2卷 26-34页

作者： Nery, A.S. Nedjah, N. França, F.M.G. Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE P.O. Box 68511 21941-972 Rio de Janeiro Brazil Department of Electronics Engineering and Telecommunications Faculty of Engineering Universidade do Estado do Rio de Janeiro Rua Sao Francisco Xavier 524 Sala 5145-F Maracana 20.550-900 Rio de Janeiro RJ Brazil Universidade Federal do Rio de Janeiro Rio de Janeiro Brazil Department of Electronics Engineering and Telecommunications Faculty of Engineering State University of Rio de Janeiro Brazil Brazil

Real time performance of non-interactive rendering of three-dimensional scenes is usually unachievable. Ray tracing is one of the methods used for rendering such scenes. The performance achieved by a sequential software-based implementation of ray tracing is far from satisfactory. In contrast, many parallel implementations of ray tracing have been enabling real time performance, as the underlying algorithm can be massively parallelised. Thus, it is expected that a custom parallel design in hardware is likely to achieve the acceptable performance standards. In this paper, we propose a hardware architecture, which we call GridRT, capable of dealing with the main desirable features of ray tracing, such as shadows and reflections effects, imposing low requirements in terms of silicon area while achieving acceptable performance in terms of rendering time. This architecture achieves is efficient yet compact as it explores the massive parallelism offered by the intrinsic structure of the algorithm. The design exploits the usage the spatial data structure of regular grids. Copyright © 2009 Inderscience Enterprises Ltd.

关键词： Ray tracing

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Dynamic thermal management in 3D multicore architectures 09

Dynamic thermal management in 3D multicore architectures

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Design, Automation and Test in Europe Conference and Exhibition

作者： Ayse K. Coskun Jose L. Ayala David Atienza Tajana Simunic Rosing Yusuf Leblebici Computer Science and Engineering Department (CSE) University of California San Diego USA Computer Architecture and Automation Department (DACYA) Complutense University of Madrid Spain Embedded Systems Laboratory (ESL) Ecole Polytechnique Fédérale de Lausanne Switzerland Microelectronics Systems Laboratory (LSM) EPF Lausanne Switzerland

ISBN: (纸本)9783981080155

Technology scaling has caused the feature sizes to shrink continuously, whereas interconnects, unlike transistors, have not followed the same trend. Designing 3D stack architectures is a recently proposed approach to overcome the power consumption and delay problems associated with the interconnects by reducing the length of the wires going across the chip. However, 3D integration introduces serious thermal challenges due to the high power density resulting from placing computational units on top of each other. In this work, we first investigate how the existing thermal management, power management and job scheduling policies affect the thermal behavior in 3D chips. We then propose a dynamic thermally-aware job scheduling technique for 3D systems to reduce the thermal problems at very low performance cost. Our approach can also be integrated with power management policies to reduce energy consumption while avoiding the thermal hot spots and large temperature variations.

关键词： Thermal management Multicore processing Energy management Power system management Energy consumption Processor scheduling Transistors computer architecture Delay Wires

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Comparison of fault-tolerance techniques for massively defective fine- and coarse-grained nanochips

Comparison of fault-tolerance techniques for massively defec...

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International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES)

作者： Jacques Henri Collet Mihalis Psarakis Piotr Zajac Dimitris Gizopoulos Andrzej Napieralski Laboratoire d'Analyse et d'Architecture des Systèmes du CNRS Université de Toulouse Toulouse France Computer Systems Laboratory Department of Informatics University of Piraeus Piraeus Greece Department of Microelectronics and Computer Science Technical University of Lodz Lodz Poland

The fundamental question addressed in this paper is how to maintain the operation dependability of future chips built from forthcoming nano- (or subnano-) technologies characterized by the reduction of component dimensions, the increase of atomic fluctuations and the massive occurrence of physical defects. We focus on fault tolerance at the architectural level, and especially on fault-tolerance approaches, which are based on chip self-diagnosis and self-reconfiguration. We study test and reconfiguration methodologies in massively defective nanoscale devices, either at fine granularity field programmable devices or at coarse granularity multi-core arrays. In particular, we address the important question of up to which point could future chips have self-organizing fault-tolerance mechanisms to autonomously ensure their own dependable operation. In the case of FPGAs, we present known fault tolerant approaches and discuss their limitations in future nanoscale devices. In the case of multicore arrays, we show that such properties as self-diagnosis, self-isolation of faulty elements and self-reorganization of communication routes are possible.

关键词： Fault tolerance Circuit testing Circuit faults Redundancy Protection Field programmable gate arrays CMOS technology Phased arrays Multicore processing Nanoscale devices

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Implementing a 1GHz Four-Issue Out-of-Order Execution Microprocessor in a Standard Cell ASIC Methodology

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Journal of computer Science & Technology 2007年第1期22卷 1-14页

作者：胡伟武赵继业钟石强杨旭 Elio Guidetti 吴永强 Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China ST Microelectronics 39 Chemin du Camp-des-Filles 1228 Plan Les Ouates Geneva Switzerland

This paper introduces the microarchitecture and physical implementation of the Godson-2E processor, which is a four-issue superscalar RISC processor that supports the 64-bit MIPS instruction set. The adoption of the aggressive out-of-order execution and memory hierarchy techniques help Godson-2E to achieve high performance. The Godson-2E processor has been physically designed in a 7-metal 90nm CMOS process using the cell-based methodology with some bitsliced manual placement and a number of crafted cells and macros. The processor can be run at 1GHz and achieves a SPEC CPU2000 rate higher than 500.

关键词： general-purpose processor superscalar pipeline out-of-order execution non-blocking cache physical design,synthesis flow bit-sliced placement crafted cell performance evaluation

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Logic as energy: A SAT-based approach

Logic as energy: A SAT-based approach

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2nd International Symposium on Brain, Vision, and Artificial Intelligence, BVAI 2007

作者： Lima, Priscila M. V. Morveli-Espinoza, M. Mariela M. França, Felipe M. G. LAM - Computer Architecture and Microelectronics Laboratory Universidade Federal Do Rio de Janeiro Brazil Departament d'Informàtica Universitat Autònoma de Barcelona Spain COPPE - Systems Engineering and Computer Science Program Universidade Federal Do Rio de Janeiro Brazil

ISBN: (纸本)3540755543

This paper presents the implementation of ARQ-PROP II, a limited-depth propositional reasoner, via the compilation of its specification into an exact formulation using the satyrus platform. satyrus' compiler takes as input the definition of a problem as a set of pseudo-Boolean constraints and produces, as output, the Energy function of a higher-order artificial neural network. This way, satisfiability of a formula can be associated to global optima. In the case of ARQ-PROP II, global optima is associated to Resolution-based refutation, in such a way that allows for simplified abduction and prediction to be unified with deduction. Besides experimental results on deduction with ARQ-PROP II, this work also corrects the mapping of satisfiability into Energy minima originally proposed by Gadi Pinkas. © 2007 Springer-Verlag Berlin Heidelberg.

关键词： Neural networks

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Design, test, integration and packaging of MEMS/MOEMS, 2005

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ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING 2006年第1期48卷 5-5页

作者： Courtois, B Laboratory of Techniques of Informatics and Microelectronics for Computer Architecture (TIMA) CMP Service France ACM ASME IEEE IMAPS IEEE Computer Society Technical University of Budapest Hungary

No abstract available

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