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检索条件"机构=Computer Architecture and Microelectronics Laboratory"
32 条 记 录,以下是21-30 订阅
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A Parallel Ray Tracing architecture Suitable for Application-Specific Hardware and GPGPU Implementations
A Parallel Ray Tracing Architecture Suitable for Application...
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Euromicro Symposium on Digital System Design
作者: Alexandre S. Nery Nadia Nedjah Felipa M.G. Franca Lech Jozwiak LAM-Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal do Rio de Janeiro Brazil Department of Electrical Engineering-Electronic Systems Eindhoven University of Technology Netherlands Universidade do Estado do Rio de Janeiro Rio de Janeiro RJ BR
The Ray Tracing rendering algorithm can produce high-fidelity images of 3-D scenes, including shadow effects, as well as reflections and transparencies. This is currently done at a processing speed of at most 30 frame... 详细信息
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A parallel architecture for ray-tracing with an embedded intersection algorithm
A parallel architecture for ray-tracing with an embedded int...
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IEEE International Symposium on Circuits and Systems (ISCAS)
作者: Alexandre S. Nery Nadia Nedjah Felipe M.G. França Lech Jozwiak LAM-Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal do Rio de Janeiro Brazil Department of Electrical Engineering-Electronic Systems Eindhovan University of Technology Netherlands Department of Electronics Engineering and Telecommunications-Faculty of Engineering Universidade do Estado do Rio de Janeiro (UERJ) Brazil
Real time rendering of three-dimensional scenes in Ray Tracing is a hard problem. However, parallel implementations have been enabling real time performance, as the algorithm can be highly parallelized. Thus, a custom... 详细信息
来源: 评论
Hardware Reuse in Modern Application-Specific Processors and Accelerators
Hardware Reuse in Modern Application-Specific Processors and...
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Euromicro Symposium on Digital System Design
作者: Alexandre S. Nery Lech Jozwiak Menno Lindwer Mauro Cocco Nadia Nedjah Felipe M.G. Franca LAM-Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal do Rio de Janeiro Brazil Department of Electrical Engineering-Electronic Systems Eindhoven University of Technology Netherlands Silicon Hive-Intel UMG Netherlands Department of Electronics Engineering and Telecommunications-Faculty of Engineering Universidade do Estado do Rio de Janeiro Brazil
Effective exploitation of the application-specific parallel patterns and computation operations through their direct implementation in hardware is the base for construction of high-quality application-specific (re-)co... 详细信息
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An intelligent design machine: architecture and search strategies
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AI EDAM 2009年 第2期2卷 105-122页
作者: Michael A. Gray Artificial Intelligence Laboratory Advanced Computer Architecture Microelectronics and Computer Technology Corporation Austin TX 78759 U.S.A.
In this report the architecture of an intelligent design machine capable of performing routine design in different design domains is described. This machine is crafted to operate as a part of a larger system driven by...
来源: 评论
A massively parallel hardware architecture for ray-tracing
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International Journal of High Performance Systems architecture 2009年 第1期2卷 26-34页
作者: Nery, A.S. Nedjah, N. França, F.M.G. Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE P.O. Box 68511 21941-972 Rio de Janeiro Brazil Department of Electronics Engineering and Telecommunications Faculty of Engineering Universidade do Estado do Rio de Janeiro Rua Sao Francisco Xavier 524 Sala 5145-F Maracana 20.550-900 Rio de Janeiro RJ Brazil Universidade Federal do Rio de Janeiro Rio de Janeiro Brazil Department of Electronics Engineering and Telecommunications Faculty of Engineering State University of Rio de Janeiro Brazil Brazil
Real time performance of non-interactive rendering of three-dimensional scenes is usually unachievable. Ray tracing is one of the methods used for rendering such scenes. The performance achieved by a sequential softwa... 详细信息
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Dynamic thermal management in 3D multicore architectures  09
Dynamic thermal management in 3D multicore architectures
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Design, Automation and Test in Europe Conference and Exhibition
作者: Ayse K. Coskun Jose L. Ayala David Atienza Tajana Simunic Rosing Yusuf Leblebici Computer Science and Engineering Department (CSE) University of California San Diego USA Computer Architecture and Automation Department (DACYA) Complutense University of Madrid Spain Embedded Systems Laboratory (ESL) Ecole Polytechnique Fédérale de Lausanne Switzerland Microelectronics Systems Laboratory (LSM) EPF Lausanne Switzerland
Technology scaling has caused the feature sizes to shrink continuously, whereas interconnects, unlike transistors, have not followed the same trend. Designing 3D stack architectures is a recently proposed approach to ... 详细信息
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Comparison of fault-tolerance techniques for massively defective fine- and coarse-grained nanochips
Comparison of fault-tolerance techniques for massively defec...
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International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES)
作者: Jacques Henri Collet Mihalis Psarakis Piotr Zajac Dimitris Gizopoulos Andrzej Napieralski Laboratoire d'Analyse et d'Architecture des Systèmes du CNRS Université de Toulouse Toulouse France Computer Systems Laboratory Department of Informatics University of Piraeus Piraeus Greece Department of Microelectronics and Computer Science Technical University of Lodz Lodz Poland
The fundamental question addressed in this paper is how to maintain the operation dependability of future chips built from forthcoming nano- (or subnano-) technologies characterized by the reduction of component dimen... 详细信息
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Implementing a 1GHz Four-Issue Out-of-Order Execution Microprocessor in a Standard Cell ASIC Methodology
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Journal of computer Science & Technology 2007年 第1期22卷 1-14页
作者: 胡伟武 赵继业 钟石强 杨旭 Elio Guidetti 吴永强 Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China ST Microelectronics 39 Chemin du Camp-des-Filles 1228 Plan Les Ouates Geneva Switzerland
This paper introduces the microarchitecture and physical implementation of the Godson-2E processor, which is a four-issue superscalar RISC processor that supports the 64-bit MIPS instruction set. The adoption of the a... 详细信息
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Logic as energy: A SAT-based approach
Logic as energy: A SAT-based approach
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2nd International Symposium on Brain, Vision, and Artificial Intelligence, BVAI 2007
作者: Lima, Priscila M. V. Morveli-Espinoza, M. Mariela M. França, Felipe M. G. LAM - Computer Architecture and Microelectronics Laboratory Universidade Federal Do Rio de Janeiro Brazil Departament d'Informàtica Universitat Autònoma de Barcelona Spain COPPE - Systems Engineering and Computer Science Program Universidade Federal Do Rio de Janeiro Brazil
This paper presents the implementation of ARQ-PROP II, a limited-depth propositional reasoner, via the compilation of its specification into an exact formulation using the satyrus platform. satyrus' compiler takes... 详细信息
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Design, test, integration and packaging of MEMS/MOEMS, 2005
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ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING 2006年 第1期48卷 5-5页
作者: Courtois, B Laboratory of Techniques of Informatics and Microelectronics for Computer Architecture (TIMA) CMP Service France ACM ASME IEEE IMAPS IEEE Computer Society Technical University of Budapest Hungary
No abstract available
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