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Design, Automation and Test in Europe Conference and Exhibition

作者： Ayse K. Coskun Jose L. Ayala David Atienza Tajana Simunic Rosing Yusuf Leblebici Computer Science and Engineering Department (CSE) University of California San Diego USA Computer Architecture and Automation Department (DACYA) Complutense University of Madrid Spain Embedded Systems Laboratory (ESL) Ecole Polytechnique Fédérale de Lausanne Switzerland Microelectronics Systems Laboratory (LSM) EPF Lausanne Switzerland

ISBN: (纸本)9783981080155

Technology scaling has caused the feature sizes to shrink continuously, whereas interconnects, unlike transistors, have not followed the same trend. Designing 3D stack architectures is a recently proposed approach to overcome the power consumption and delay problems associated with the interconnects by reducing the length of the wires going across the chip. However, 3D integration introduces serious thermal challenges due to the high power density resulting from placing computational units on top of each other. In this work, we first investigate how the existing thermal management, power management and job scheduling policies affect the thermal behavior in 3D chips. We then propose a dynamic thermally-aware job scheduling technique for 3D systems to reduce the thermal problems at very low performance cost. Our approach can also be integrated with power management policies to reduce energy consumption while avoiding the thermal hot spots and large temperature variations.

关键词： Thermal management Multicore processing Energy management Power system management Energy consumption Processor scheduling Transistors computer architecture Delay Wires

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Comparison of fault-tolerance techniques for massively defective fine- and coarse-grained nanochips

Comparison of fault-tolerance techniques for massively defec...

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International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES)

作者： Jacques Henri Collet Mihalis Psarakis Piotr Zajac Dimitris Gizopoulos Andrzej Napieralski Laboratoire d'Analyse et d'Architecture des Systèmes du CNRS Université de Toulouse Toulouse France Computer Systems Laboratory Department of Informatics University of Piraeus Piraeus Greece Department of Microelectronics and Computer Science Technical University of Lodz Lodz Poland

The fundamental question addressed in this paper is how to maintain the operation dependability of future chips built from forthcoming nano- (or subnano-) technologies characterized by the reduction of component dimensions, the increase of atomic fluctuations and the massive occurrence of physical defects. We focus on fault tolerance at the architectural level, and especially on fault-tolerance approaches, which are based on chip self-diagnosis and self-reconfiguration. We study test and reconfiguration methodologies in massively defective nanoscale devices, either at fine granularity field programmable devices or at coarse granularity multi-core arrays. In particular, we address the important question of up to which point could future chips have self-organizing fault-tolerance mechanisms to autonomously ensure their own dependable operation. In the case of FPGAs, we present known fault tolerant approaches and discuss their limitations in future nanoscale devices. In the case of multicore arrays, we show that such properties as self-diagnosis, self-isolation of faulty elements and self-reorganization of communication routes are possible.

关键词： Fault tolerance Circuit testing Circuit faults Redundancy Protection Field programmable gate arrays CMOS technology Phased arrays Multicore processing Nanoscale devices

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A reconfigurable routing method for fault-tolerant mesh-based network on chip

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Journal of Information and Computational Science 2013年第1期10卷 157-165页

作者： Liu, Yanhua Ruan, Ying Lai, Zongsheng Sun, Ling Institute of Microelectronics Circuit and System East China Normal University Shanghai 200241 China Jiangsu Provincial Key Lab. of ASIC Design Nantong University Nantong 226019 China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China

As the semiconductor industry advances to nano-technology points, Network on Chip (NoC) components are becoming vulnerable to errors during the system operation. Consequently, fault-tolerant techniques for NoC are needed to achieve high reliability. In this paper, we present a fault-tolerant routing method to tolerate faulty routers in a two-dimension (2D) mesh-based NoC. With this method, the system can have a multi-router fault-tolerant capability and the routing path can be dynamically reconfigured to support different situations caused by faulty routers in NoC. Fault-tolerance capability and system performance of the proposed method are evaluated through analysis and simulations. Theoretical analysis and simulation results show that the proposed method can enhance the reliability of system and offer considerable fault-tolerance capability. © 2013 by Binary Information Press.

关键词： Network-on-chip

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A Parallel Ray Tracing architecture Suitable for Application-Specific Hardware and GPGPU Implementations

A Parallel Ray Tracing Architecture Suitable for Application...

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Euromicro Symposium on Digital System Design

作者： Alexandre S. Nery Nadia Nedjah Felipa M.G. Franca Lech Jozwiak LAM-Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal do Rio de Janeiro Brazil Department of Electrical Engineering-Electronic Systems Eindhoven University of Technology Netherlands Universidade do Estado do Rio de Janeiro Rio de Janeiro RJ BR

The Ray Tracing rendering algorithm can produce high-fidelity images of 3-D scenes, including shadow effects, as well as reflections and transparencies. This is currently done at a processing speed of at most 30 frames per second. Therefore, actual implementations of the algorithm are not yet suitable for interactive real-time rendering, which is required in games and virtual reality based applications. Fortunately, the algorithm allows for massive parallelization of its computations. In this paper, we present a parallel architecture for ray tracing based on a uniform spatial subdivision of the scene and exploiting an embedded computation of ray-triangle intersections. This approach allows for a significant acceleration of intersection computations, as well as, a reduction of the total number of the required intersections checks. Furthermore, it allows for these checks to be performed in parallel and in advance for each ray. In this paper we discuss and analyze an ASIP-based implementation using FPGAs and a GPGPU-based parallel implementation of the proposed architecture. The performance of both implementations are reported and compared.

关键词： Ray tracing Graphics processing unit Instruction sets computer architecture Registers Image color analysis Hardware

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Automatic complex instruction identification for efficient application mapping onto ASIPs

Automatic complex instruction identification for efficient a...

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IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： Alexandre S. Nery Nadia Nedjah Felipe M. G. França Lech Jozwiak Henk Corporaal Department of Electrical Engineering - Electronic Systems Eindhoven University of Technology The Netherlands Department of Electronics Engineering and Telecommunications Universidade do Estado do Rio de Janeiro Brazil LAM - Computer Architecture and Microelectronics Laboratory Universidade Federal do Rio de Janeiro Brazil

Instruction Set Customization is a well-known technique to enhance the performance and efficiency of Application-Specific Processors (ASIPs). An extensive application profiling can indicate which parts of a given application, or class of applications, are most frequently executed, enabling the implementation of such frequently executed parts in hardware as custom instructions. However, a naive ad hoc instruction set customization process may identify and select poor instruction extension candidates, which may not result in a significantly improved performance with low circuit-area and energy footprints. In this paper we propose and discuss an efficient instruction set customization method and automatic tool, which exploit the maximal common subgraphs (common operation patterns) of the most frequently executed basic blocks of a given application. The speed results from our tool for a VLIW ASIP are provided for a set of benchmark applications. The average execution time reduction ranges from 30% to 40%, with only a few custom instructions.

关键词： VLIW Hardware Ray tracing Program processors Registers Libraries Convolution

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A framework for automatic custom instruction identification on multi-issue ASIPs

A framework for automatic custom instruction identification ...

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IEEE International Conference on Industrial Informatics (INDIN)

作者： Alexandre S. Nery Nadia Nedjah Felipe M. G. França Lech Jozwiak Henk Corporaal LAM - Computer Architecture and Microelectronics Laboratory COPPE Universidade Federal do Rio de Janeiro Brazil Department of Electrical Engineering - Electronic Systems Eindhoven University of Technology The Netherlands Universidade do Estado do Rio de Janeiro Rio de Janeiro RJ BR

Custom Instruction Identification is an important part in the design of efficient Application-Specific Processors (ASIPs). It consists of profiling of a given application to find patterns of basic operations that are frequently executed. Operations of such patterns can be implemented together as a single custom instruction to speedup the execution of the application. Because of the problem's high complexity, several methods have been proposed for specific single-issue (RISC) processors and architectures, limiting the shape and size of custom instructions that can actually be identified and, possibly, implemented. In this paper, we propose and discuss an efficient custom instruction set identification method and corresponding automatic tool for multi-issue VLIW ASIPs, which search for the common operation patterns of the most frequently executed basic blocks of a given application, with different sizes and shapes. The speedup results for the custom instructions identified by our tool are provided for a set of benchmark applications. The speedup is up to 68%, with only a few custom instructions used.

关键词： VLIW Program processors Libraries Registers Ray tracing Hardware Shape

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A parallel architecture for ray-tracing with an embedded intersection algorithm

A parallel architecture for ray-tracing with an embedded int...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Alexandre S. Nery Nadia Nedjah Felipe M.G. França Lech Jozwiak LAM-Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal do Rio de Janeiro Brazil Department of Electrical Engineering-Electronic Systems Eindhovan University of Technology Netherlands Department of Electronics Engineering and Telecommunications-Faculty of Engineering Universidade do Estado do Rio de Janeiro (UERJ) Brazil

Real time rendering of three-dimensional scenes in Ray Tracing is a hard problem. However, parallel implementations have been enabling real time performance, as the algorithm can be highly parallelized. Thus, a custom parallel design in hardware is likely to achieve a good performance. In this paper, we further improve the GridRT architecture overall performance by embedding the ray-triangle intersection computation into the precessing elements that form the architecture. Low cost and high rendering performance are the main concerns in this novel design. The results show that the execution time of each intersection computation is reduced by at least 50%, while the area cost is practically unchanged or even reduced when compared to the original GridRT implementation.

关键词： Ray tracing Registers Equations USA Councils Mathematical model Parallel architectures

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An Ultra-Low Power 3-T Chaotic Map based True Random Number Generator

An Ultra-Low Power 3-T Chaotic Map based True Random Number ...

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IEEE Asian Hardware-Oriented Security and Trust (AsianHOST)

作者： Lijuan Han Yuan Cao Lei Qian Haodong Xie Chip-Hong Chang College of Internet of Tings Engineering Hohai University Chang Zhou China Changzhou Galaxy Century Microelectronics Co. Ltd. State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences School of Electrical and Electronic Engineering Nanyang Technological University Singapore

ISBN: (纸本)9781665441865

In this paper, discrete-time chaos generator is exploited for lightweight and energy-efficient true random number generator (TRNG) implementation. The chaos generator is realized with a two-stage tent map circuit with feedback. Each stage consists of three transistors. Its transient characteristics can be tuned over a range of bias voltage to realize a family of tent map functions. The chaotic output voltage amplitude of each stage is highly sensitive to the environmental noise. The difference signal between two such chaos generators at each stage is amplified to produce a random binary output. The output of the quantized sense amplifier is sampled at twice the bit rate of each stage of tent map circuit. The proposed design was simulated using a standard 55 nm 1.2 V CMOS process. The results show that it has a very low power consumption of 10.98 μW. It has an ultra-low energy consumption of only 5.49 pJ/bit at a throughput of 2 Mbps, which is 19x lower than the recently reported state-of-the-art and the most power efficient chaotic TRNGs. The random bit stream generated by the proposed TRNG has passed entropy, ACF and NIST randomness tests.

关键词： Chaos Voltage NIST Throughput CMOS process Generators Entropy

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Hardware Reuse in Modern Application-Specific Processors and Accelerators

Hardware Reuse in Modern Application-Specific Processors and...

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Euromicro Symposium on Digital System Design

作者： Alexandre S. Nery Lech Jozwiak Menno Lindwer Mauro Cocco Nadia Nedjah Felipe M.G. Franca LAM-Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal do Rio de Janeiro Brazil Department of Electrical Engineering-Electronic Systems Eindhoven University of Technology Netherlands Silicon Hive-Intel UMG Netherlands Department of Electronics Engineering and Telecommunications-Faculty of Engineering Universidade do Estado do Rio de Janeiro Brazil

Effective exploitation of the application-specific parallel patterns and computation operations through their direct implementation in hardware is the base for construction of high-quality application-specific (re-)configurable application specific instruction set processors (ASIPs) and hardware accelerators for modern highly-demanding applications. Although it receives a lot of attention from the researchers and practitioners, a very important problem of hardware reuse in ASIP and accelerator synthesis is clearly underestimated and does not get enough attention in the published research. This paper is an effect of an industry and academic collaborative research. It analyses the problem of hardware sharing, shows its high practical relevance, as well as a big influence of hardware sharing on the major circuit and system parameters, and its importance for the multi-objective optimization and tradeoff exploitation. It also demonstrates that the state-of-the-art synthesis tools do not sufficiently address this problem and gives several guidelines related to enhancement of the hardware reuse.

关键词： Hardware Resource management computer architecture Optimization Program processors Adders Delay

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Corrigendum to “Fast and scalable lock methods for video coding on many-core architecture” [J. Vis. Commun. Image R. 25(7) (2014) 1758–1762]

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Journal of Visual Communication and Image Representation 2015年 27卷 57-57页

作者： Weizhi Xu Hui Yu Dianjie Lu Fenglong Song Da Wang Xiaochun Ye Songwei Pei Dongrui Fan Hongtao Xie Institute of Microelectronics Tsinghua University Beijing China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Key Lab. of Intelligent Information Processing Institute of Computing Technology Chinese Academy of Sciences Beijing China School of Information Science and Engineering Shandong Normal University Jinan China Department of Computer Science and Technology Beijing University of Chemical Technology Beijing China Institute of Information Engineering Chinese Academy of Sciences National Engineering Laboratory for Information Security Technologies Beijing China

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